From patchwork Fri Oct 25 09:16:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Liu X-Patchwork-Id: 11211817 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 47C471390 for ; Fri, 25 Oct 2019 09:18:36 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 14D232070B for ; Fri, 25 Oct 2019 09:18:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jsfBjzWf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 14D232070B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iNviF-0007mX-Al; Fri, 25 Oct 2019 09:16:51 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iNviD-0007mP-NU for xen-devel@lists.xenproject.org; Fri, 25 Oct 2019 09:16:49 +0000 X-Inumbo-ID: 2a1ae05e-f708-11e9-beca-bc764e2007e4 Received: from mail-wr1-x433.google.com (unknown [2a00:1450:4864:20::433]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 2a1ae05e-f708-11e9-beca-bc764e2007e4; Fri, 25 Oct 2019 09:16:45 +0000 (UTC) Received: by mail-wr1-x433.google.com with SMTP id a11so1436709wra.6 for ; Fri, 25 Oct 2019 02:16:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IfHRaj/QBDu7K960ROGHf+NO+M2zK+27myHi7qUu4DY=; b=jsfBjzWfm2h1BgY/F+Ab7N0BLUfVIophB5j8fIs3fsn3fesEPniBsvziSbzxbb2s37 VE67nNODsp6BOKChety2T6xU9WHJY3tz9kmuZTRK+rS3htCfZ6s/EetZfVWOnRAijGji KWH1l1gPknNOdTZvjL85woGB121h3pu4yhGag8HrTJUqZtwXxIQtIeq2PT8pMsbHaW8Y sM2wKpE8Fsh4z1RGDKaTCDAGFUonEuUiIbfUDQggL70QeiobaaQQP8cXKYxo1CHntuTX gKBx34n4XwZHvSVsvs2Zc82wN+c12PupB0eJ9OrvfMZ6C4U853mHHp4HfqC1bDmz6zgq TrTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=IfHRaj/QBDu7K960ROGHf+NO+M2zK+27myHi7qUu4DY=; b=h2Q7jazUnsas9cAnqlbNQHtlSxIfwhqKkpk3OnD9gTu7TQ8X3NJTVNYXvZl5pJ7Rh4 qcTzac4br/mk+c8jEp5Qy7JL5NkSxUcDOPjsFxi/miPmnvARhPNuZXIvYlQb1eTSJ2hC 3FmGG1wOonyUKHLO5FpDYCcsID9DB1q/K366OPZTKVLki23ASYatejzjxD5MsNXVtDqd rXOIGGSdBXf8rfoonwDRMLtBDAAm5ZkcBagiUrY6CqrP+qLAfL7NRHmVyZfv5yGGel0r 7xMp9mwMBOju6K1EI6Dj95cx8XWvswhL2gxWn/SWOhH3e9OoENWCFbpYjDM6rkr+baSU rqyA== X-Gm-Message-State: APjAAAXvjjh2icMXqwdWsPGOd0uVuaHim4DWiTEZPAMCIRCivRTly0/4 Vb7qg8C6Rf7+pm//owqjLUxkbUOhoPI= X-Google-Smtp-Source: APXvYqy0CahoBBYwLEVAOE/BHK3oVhvkSLSK1sUgzyXUWh7EMlNskQAtsKD9mfv55WzNAgsXHX289g== X-Received: by 2002:adf:f152:: with SMTP id y18mr2027016wro.285.1571995003997; Fri, 25 Oct 2019 02:16:43 -0700 (PDT) Received: from debian.mshome.net (54.163.200.146.dyn.plus.net. [146.200.163.54]) by smtp.gmail.com with ESMTPSA id b62sm1873283wmc.13.2019.10.25.02.16.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2019 02:16:43 -0700 (PDT) From: Wei Liu X-Google-Original-From: Wei Liu To: Xen Development List Date: Fri, 25 Oct 2019 10:16:12 +0100 Message-Id: <20191025091618.10153-2-liuwe@microsoft.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191025091618.10153-1-liuwe@microsoft.com> References: <20191025091618.10153-1-liuwe@microsoft.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH for-next 1/7] x86: import hyperv-tlfs.h from Linux X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Wei Liu , Paul Durrant , Andrew Cooper , Michael Kelley , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Taken from Linux commit b2d8b167e15bb5ec2691d1119c025630a247f649. This is a pristine copy from Linux. It is not used yet and probably doesn't compile. Changes to make it work will come later. Signed-off-by: Wei Liu Acked-by: Jan Beulich --- xen/include/asm-x86/guest/hyperv-tlfs.h | 906 ++++++++++++++++++++++++ 1 file changed, 906 insertions(+) create mode 100644 xen/include/asm-x86/guest/hyperv-tlfs.h diff --git a/xen/include/asm-x86/guest/hyperv-tlfs.h b/xen/include/asm-x86/guest/hyperv-tlfs.h new file mode 100644 index 0000000000..7741e211f7 --- /dev/null +++ b/xen/include/asm-x86/guest/hyperv-tlfs.h @@ -0,0 +1,906 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* + * This file contains definitions from Hyper-V Hypervisor Top-Level Functional + * Specification (TLFS): + * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs + */ + +#ifndef _ASM_X86_HYPERV_TLFS_H +#define _ASM_X86_HYPERV_TLFS_H + +#include +#include + +/* + * While not explicitly listed in the TLFS, Hyper-V always runs with a page size + * of 4096. These definitions are used when communicating with Hyper-V using + * guest physical pages and guest physical page addresses, since the guest page + * size may not be 4096 on all architectures. + */ +#define HV_HYP_PAGE_SHIFT 12 +#define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) +#define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) + +/* + * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent + * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). + */ +#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 +#define HYPERV_CPUID_INTERFACE 0x40000001 +#define HYPERV_CPUID_VERSION 0x40000002 +#define HYPERV_CPUID_FEATURES 0x40000003 +#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 +#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 +#define HYPERV_CPUID_NESTED_FEATURES 0x4000000A + +#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 +#define HYPERV_CPUID_MIN 0x40000005 +#define HYPERV_CPUID_MAX 0x4000ffff + +/* + * Feature identification. EAX indicates which features are available + * to the partition based upon the current partition privileges. + * These are HYPERV_CPUID_FEATURES.EAX bits. + */ + +/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ +#define HV_X64_MSR_VP_RUNTIME_AVAILABLE BIT(0) +/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ +#define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) +/* + * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM + * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available + */ +#define HV_X64_MSR_SYNIC_AVAILABLE BIT(2) +/* + * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through + * HV_X64_MSR_STIMER3_COUNT) available + */ +#define HV_MSR_SYNTIMER_AVAILABLE BIT(3) +/* + * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) + * are available + */ +#define HV_X64_MSR_APIC_ACCESS_AVAILABLE BIT(4) +/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ +#define HV_X64_MSR_HYPERCALL_AVAILABLE BIT(5) +/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ +#define HV_X64_MSR_VP_INDEX_AVAILABLE BIT(6) +/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ +#define HV_X64_MSR_RESET_AVAILABLE BIT(7) +/* + * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, + * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, + * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available + */ +#define HV_X64_MSR_STAT_PAGES_AVAILABLE BIT(8) +/* Partition reference TSC MSR is available */ +#define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) +/* Partition Guest IDLE MSR is available */ +#define HV_X64_MSR_GUEST_IDLE_AVAILABLE BIT(10) +/* + * There is a single feature flag that signifies if the partition has access + * to MSRs with local APIC and TSC frequencies. + */ +#define HV_X64_ACCESS_FREQUENCY_MSRS BIT(11) +/* AccessReenlightenmentControls privilege */ +#define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) + +/* + * Feature identification: indicates which flags were specified at partition + * creation. The format is the same as the partition creation flag structure + * defined in section Partition Creation Flags. + * These are HYPERV_CPUID_FEATURES.EBX bits. + */ +#define HV_X64_CREATE_PARTITIONS BIT(0) +#define HV_X64_ACCESS_PARTITION_ID BIT(1) +#define HV_X64_ACCESS_MEMORY_POOL BIT(2) +#define HV_X64_ADJUST_MESSAGE_BUFFERS BIT(3) +#define HV_X64_POST_MESSAGES BIT(4) +#define HV_X64_SIGNAL_EVENTS BIT(5) +#define HV_X64_CREATE_PORT BIT(6) +#define HV_X64_CONNECT_PORT BIT(7) +#define HV_X64_ACCESS_STATS BIT(8) +#define HV_X64_DEBUGGING BIT(11) +#define HV_X64_CPU_POWER_MANAGEMENT BIT(12) + +/* + * Feature identification. EDX indicates which miscellaneous features + * are available to the partition. + * These are HYPERV_CPUID_FEATURES.EDX bits. + */ +/* The MWAIT instruction is available (per section MONITOR / MWAIT) */ +#define HV_X64_MWAIT_AVAILABLE BIT(0) +/* Guest debugging support is available */ +#define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) +/* Performance Monitor support is available*/ +#define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) +/* Support for physical CPU dynamic partitioning events is available*/ +#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) +/* + * Support for passing hypercall input parameter block via XMM + * registers is available + */ +#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4) +/* Support for a virtual guest idle state is available */ +#define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) +/* Frequency MSRs available */ +#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) +/* Crash MSR available */ +#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) +/* stimer Direct Mode is available */ +#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) + +/* + * Implementation recommendations. Indicates which behaviors the hypervisor + * recommends the OS implement for optimal performance. + * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. + */ +/* + * Recommend using hypercall for address space switches rather + * than MOV to CR3 instruction + */ +#define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) +/* Recommend using hypercall for local TLB flushes rather + * than INVLPG or MOV to CR3 instructions */ +#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) +/* + * Recommend using hypercall for remote TLB flushes rather + * than inter-processor interrupts + */ +#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) +/* + * Recommend using MSRs for accessing APIC registers + * EOI, ICR and TPR rather than their memory-mapped counterparts + */ +#define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) +/* Recommend using the hypervisor-provided MSR to initiate a system RESET */ +#define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) +/* + * Recommend using relaxed timing for this partition. If used, + * the VM should disable any watchdog timeouts that rely on the + * timely delivery of external interrupts + */ +#define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) + +/* + * Recommend not using Auto End-Of-Interrupt feature + */ +#define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) + +/* + * Recommend using cluster IPI hypercalls. + */ +#define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) + +/* Recommend using the newer ExProcessorMasks interface */ +#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) + +/* Recommend using enlightened VMCS */ +#define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) + +/* + * Virtual processor will never share a physical core with another virtual + * processor, except for virtual processors that are reported as sibling SMT + * threads. + */ +#define HV_X64_NO_NONARCH_CORESHARING BIT(18) + +/* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ +#define HV_X64_NESTED_DIRECT_FLUSH BIT(17) +#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) +#define HV_X64_NESTED_MSR_BITMAP BIT(19) + +/* Hyper-V specific model specific registers (MSRs) */ + +/* MSR used to identify the guest OS. */ +#define HV_X64_MSR_GUEST_OS_ID 0x40000000 + +/* MSR used to setup pages used to communicate with the hypervisor. */ +#define HV_X64_MSR_HYPERCALL 0x40000001 + +/* MSR used to provide vcpu index */ +#define HV_X64_MSR_VP_INDEX 0x40000002 + +/* MSR used to reset the guest OS. */ +#define HV_X64_MSR_RESET 0x40000003 + +/* MSR used to provide vcpu runtime in 100ns units */ +#define HV_X64_MSR_VP_RUNTIME 0x40000010 + +/* MSR used to read the per-partition time reference counter */ +#define HV_X64_MSR_TIME_REF_COUNT 0x40000020 + +/* A partition's reference time stamp counter (TSC) page */ +#define HV_X64_MSR_REFERENCE_TSC 0x40000021 + +/* MSR used to retrieve the TSC frequency */ +#define HV_X64_MSR_TSC_FREQUENCY 0x40000022 + +/* MSR used to retrieve the local APIC timer frequency */ +#define HV_X64_MSR_APIC_FREQUENCY 0x40000023 + +/* Define the virtual APIC registers */ +#define HV_X64_MSR_EOI 0x40000070 +#define HV_X64_MSR_ICR 0x40000071 +#define HV_X64_MSR_TPR 0x40000072 +#define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 + +/* Define synthetic interrupt controller model specific registers. */ +#define HV_X64_MSR_SCONTROL 0x40000080 +#define HV_X64_MSR_SVERSION 0x40000081 +#define HV_X64_MSR_SIEFP 0x40000082 +#define HV_X64_MSR_SIMP 0x40000083 +#define HV_X64_MSR_EOM 0x40000084 +#define HV_X64_MSR_SINT0 0x40000090 +#define HV_X64_MSR_SINT1 0x40000091 +#define HV_X64_MSR_SINT2 0x40000092 +#define HV_X64_MSR_SINT3 0x40000093 +#define HV_X64_MSR_SINT4 0x40000094 +#define HV_X64_MSR_SINT5 0x40000095 +#define HV_X64_MSR_SINT6 0x40000096 +#define HV_X64_MSR_SINT7 0x40000097 +#define HV_X64_MSR_SINT8 0x40000098 +#define HV_X64_MSR_SINT9 0x40000099 +#define HV_X64_MSR_SINT10 0x4000009A +#define HV_X64_MSR_SINT11 0x4000009B +#define HV_X64_MSR_SINT12 0x4000009C +#define HV_X64_MSR_SINT13 0x4000009D +#define HV_X64_MSR_SINT14 0x4000009E +#define HV_X64_MSR_SINT15 0x4000009F + +/* + * Synthetic Timer MSRs. Four timers per vcpu. + */ +#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 +#define HV_X64_MSR_STIMER0_COUNT 0x400000B1 +#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 +#define HV_X64_MSR_STIMER1_COUNT 0x400000B3 +#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 +#define HV_X64_MSR_STIMER2_COUNT 0x400000B5 +#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 +#define HV_X64_MSR_STIMER3_COUNT 0x400000B7 + +/* Hyper-V guest idle MSR */ +#define HV_X64_MSR_GUEST_IDLE 0x400000F0 + +/* Hyper-V guest crash notification MSR's */ +#define HV_X64_MSR_CRASH_P0 0x40000100 +#define HV_X64_MSR_CRASH_P1 0x40000101 +#define HV_X64_MSR_CRASH_P2 0x40000102 +#define HV_X64_MSR_CRASH_P3 0x40000103 +#define HV_X64_MSR_CRASH_P4 0x40000104 +#define HV_X64_MSR_CRASH_CTL 0x40000105 + +/* TSC emulation after migration */ +#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 +#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 +#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 + +/* + * Declare the MSR used to setup pages used to communicate with the hypervisor. + */ +union hv_x64_msr_hypercall_contents { + u64 as_uint64; + struct { + u64 enable:1; + u64 reserved:11; + u64 guest_physical_address:52; + } __packed; +}; + +/* + * TSC page layout. + */ +struct ms_hyperv_tsc_page { + volatile u32 tsc_sequence; + u32 reserved1; + volatile u64 tsc_scale; + volatile s64 tsc_offset; + u64 reserved2[509]; +} __packed; + +/* + * The guest OS needs to register the guest ID with the hypervisor. + * The guest ID is a 64 bit entity and the structure of this ID is + * specified in the Hyper-V specification: + * + * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx + * + * While the current guideline does not specify how Linux guest ID(s) + * need to be generated, our plan is to publish the guidelines for + * Linux and other guest operating systems that currently are hosted + * on Hyper-V. The implementation here conforms to this yet + * unpublished guidelines. + * + * + * Bit(s) + * 63 - Indicates if the OS is Open Source or not; 1 is Open Source + * 62:56 - Os Type; Linux is 0x100 + * 55:48 - Distro specific identification + * 47:16 - Linux kernel version number + * 15:0 - Distro specific identification + * + * + */ + +#define HV_LINUX_VENDOR_ID 0x8100 + +struct hv_reenlightenment_control { + __u64 vector:8; + __u64 reserved1:8; + __u64 enabled:1; + __u64 reserved2:15; + __u64 target_vp:32; +} __packed; + +struct hv_tsc_emulation_control { + __u64 enabled:1; + __u64 reserved:63; +} __packed; + +struct hv_tsc_emulation_status { + __u64 inprogress:1; + __u64 reserved:63; +} __packed; + +#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 +#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 +#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ + (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) + +/* + * Crash notification (HV_X64_MSR_CRASH_CTL) flags. + */ +#define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) +#define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) +#define HV_X64_MSR_CRASH_PARAMS \ + (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) + +#define HV_IPI_LOW_VECTOR 0x10 +#define HV_IPI_HIGH_VECTOR 0xff + +/* Declare the various hypercall operations. */ +#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 +#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 +#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 +#define HVCALL_SEND_IPI 0x000b +#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 +#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 +#define HVCALL_SEND_IPI_EX 0x0015 +#define HVCALL_POST_MESSAGE 0x005c +#define HVCALL_SIGNAL_EVENT 0x005d +#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af +#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0 + +#define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 +#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 +#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ + (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) + +/* Hyper-V Enlightened VMCS version mask in nested features CPUID */ +#define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff + +#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 +#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 + +#define HV_PROCESSOR_POWER_STATE_C0 0 +#define HV_PROCESSOR_POWER_STATE_C1 1 +#define HV_PROCESSOR_POWER_STATE_C2 2 +#define HV_PROCESSOR_POWER_STATE_C3 3 + +#define HV_FLUSH_ALL_PROCESSORS BIT(0) +#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) +#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) +#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) + +enum HV_GENERIC_SET_FORMAT { + HV_GENERIC_SET_SPARSE_4K, + HV_GENERIC_SET_ALL, +}; + +#define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) +#define HV_HYPERCALL_FAST_BIT BIT(16) +#define HV_HYPERCALL_VARHEAD_OFFSET 17 +#define HV_HYPERCALL_REP_COMP_OFFSET 32 +#define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) +#define HV_HYPERCALL_REP_START_OFFSET 48 +#define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) + +/* hypercall status code */ +#define HV_STATUS_SUCCESS 0 +#define HV_STATUS_INVALID_HYPERCALL_CODE 2 +#define HV_STATUS_INVALID_HYPERCALL_INPUT 3 +#define HV_STATUS_INVALID_ALIGNMENT 4 +#define HV_STATUS_INVALID_PARAMETER 5 +#define HV_STATUS_INSUFFICIENT_MEMORY 11 +#define HV_STATUS_INVALID_PORT_ID 17 +#define HV_STATUS_INVALID_CONNECTION_ID 18 +#define HV_STATUS_INSUFFICIENT_BUFFERS 19 + +/* + * The Hyper-V TimeRefCount register and the TSC + * page provide a guest VM clock with 100ns tick rate + */ +#define HV_CLOCK_HZ (NSEC_PER_SEC/100) + +typedef struct _HV_REFERENCE_TSC_PAGE { + __u32 tsc_sequence; + __u32 res1; + __u64 tsc_scale; + __s64 tsc_offset; +} __packed HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; + +/* Define the number of synthetic interrupt sources. */ +#define HV_SYNIC_SINT_COUNT (16) +/* Define the expected SynIC version. */ +#define HV_SYNIC_VERSION_1 (0x1) +/* Valid SynIC vectors are 16-255. */ +#define HV_SYNIC_FIRST_VALID_VECTOR (16) + +#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) +#define HV_SYNIC_SIMP_ENABLE (1ULL << 0) +#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) +#define HV_SYNIC_SINT_MASKED (1ULL << 16) +#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) +#define HV_SYNIC_SINT_VECTOR_MASK (0xFF) + +#define HV_SYNIC_STIMER_COUNT (4) + +/* Define synthetic interrupt controller message constants. */ +#define HV_MESSAGE_SIZE (256) +#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) +#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) + +/* Define hypervisor message types. */ +enum hv_message_type { + HVMSG_NONE = 0x00000000, + + /* Memory access messages. */ + HVMSG_UNMAPPED_GPA = 0x80000000, + HVMSG_GPA_INTERCEPT = 0x80000001, + + /* Timer notification messages. */ + HVMSG_TIMER_EXPIRED = 0x80000010, + + /* Error messages. */ + HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, + HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, + HVMSG_UNSUPPORTED_FEATURE = 0x80000022, + + /* Trace buffer complete messages. */ + HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, + + /* Platform-specific processor intercept messages. */ + HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, + HVMSG_X64_MSR_INTERCEPT = 0x80010001, + HVMSG_X64_CPUID_INTERCEPT = 0x80010002, + HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, + HVMSG_X64_APIC_EOI = 0x80010004, + HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 +}; + +/* Define synthetic interrupt controller message flags. */ +union hv_message_flags { + __u8 asu8; + struct { + __u8 msg_pending:1; + __u8 reserved:7; + } __packed; +}; + +/* Define port identifier type. */ +union hv_port_id { + __u32 asu32; + struct { + __u32 id:24; + __u32 reserved:8; + } __packed u; +}; + +/* Define synthetic interrupt controller message header. */ +struct hv_message_header { + __u32 message_type; + __u8 payload_size; + union hv_message_flags message_flags; + __u8 reserved[2]; + union { + __u64 sender; + union hv_port_id port; + }; +} __packed; + +/* Define synthetic interrupt controller message format. */ +struct hv_message { + struct hv_message_header header; + union { + __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; + } u; +} __packed; + +/* Define the synthetic interrupt message page layout. */ +struct hv_message_page { + struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; +} __packed; + +/* Define timer message payload structure. */ +struct hv_timer_message_payload { + __u32 timer_index; + __u32 reserved; + __u64 expiration_time; /* When the timer expired */ + __u64 delivery_time; /* When the message was delivered */ +} __packed; + +struct hv_nested_enlightenments_control { + struct { + __u32 directhypercall:1; + __u32 reserved:31; + } features; + struct { + __u32 reserved; + } hypercallControls; +} __packed; + +/* Define virtual processor assist page structure. */ +struct hv_vp_assist_page { + __u32 apic_assist; + __u32 reserved1; + __u64 vtl_control[3]; + struct hv_nested_enlightenments_control nested_control; + __u8 enlighten_vmentry; + __u8 reserved2[7]; + __u64 current_nested_vmcs; +} __packed; + +struct hv_enlightened_vmcs { + u32 revision_id; + u32 abort; + + u16 host_es_selector; + u16 host_cs_selector; + u16 host_ss_selector; + u16 host_ds_selector; + u16 host_fs_selector; + u16 host_gs_selector; + u16 host_tr_selector; + + u16 padding16_1; + + u64 host_ia32_pat; + u64 host_ia32_efer; + + u64 host_cr0; + u64 host_cr3; + u64 host_cr4; + + u64 host_ia32_sysenter_esp; + u64 host_ia32_sysenter_eip; + u64 host_rip; + u32 host_ia32_sysenter_cs; + + u32 pin_based_vm_exec_control; + u32 vm_exit_controls; + u32 secondary_vm_exec_control; + + u64 io_bitmap_a; + u64 io_bitmap_b; + u64 msr_bitmap; + + u16 guest_es_selector; + u16 guest_cs_selector; + u16 guest_ss_selector; + u16 guest_ds_selector; + u16 guest_fs_selector; + u16 guest_gs_selector; + u16 guest_ldtr_selector; + u16 guest_tr_selector; + + u32 guest_es_limit; + u32 guest_cs_limit; + u32 guest_ss_limit; + u32 guest_ds_limit; + u32 guest_fs_limit; + u32 guest_gs_limit; + u32 guest_ldtr_limit; + u32 guest_tr_limit; + u32 guest_gdtr_limit; + u32 guest_idtr_limit; + + u32 guest_es_ar_bytes; + u32 guest_cs_ar_bytes; + u32 guest_ss_ar_bytes; + u32 guest_ds_ar_bytes; + u32 guest_fs_ar_bytes; + u32 guest_gs_ar_bytes; + u32 guest_ldtr_ar_bytes; + u32 guest_tr_ar_bytes; + + u64 guest_es_base; + u64 guest_cs_base; + u64 guest_ss_base; + u64 guest_ds_base; + u64 guest_fs_base; + u64 guest_gs_base; + u64 guest_ldtr_base; + u64 guest_tr_base; + u64 guest_gdtr_base; + u64 guest_idtr_base; + + u64 padding64_1[3]; + + u64 vm_exit_msr_store_addr; + u64 vm_exit_msr_load_addr; + u64 vm_entry_msr_load_addr; + + u64 cr3_target_value0; + u64 cr3_target_value1; + u64 cr3_target_value2; + u64 cr3_target_value3; + + u32 page_fault_error_code_mask; + u32 page_fault_error_code_match; + + u32 cr3_target_count; + u32 vm_exit_msr_store_count; + u32 vm_exit_msr_load_count; + u32 vm_entry_msr_load_count; + + u64 tsc_offset; + u64 virtual_apic_page_addr; + u64 vmcs_link_pointer; + + u64 guest_ia32_debugctl; + u64 guest_ia32_pat; + u64 guest_ia32_efer; + + u64 guest_pdptr0; + u64 guest_pdptr1; + u64 guest_pdptr2; + u64 guest_pdptr3; + + u64 guest_pending_dbg_exceptions; + u64 guest_sysenter_esp; + u64 guest_sysenter_eip; + + u32 guest_activity_state; + u32 guest_sysenter_cs; + + u64 cr0_guest_host_mask; + u64 cr4_guest_host_mask; + u64 cr0_read_shadow; + u64 cr4_read_shadow; + u64 guest_cr0; + u64 guest_cr3; + u64 guest_cr4; + u64 guest_dr7; + + u64 host_fs_base; + u64 host_gs_base; + u64 host_tr_base; + u64 host_gdtr_base; + u64 host_idtr_base; + u64 host_rsp; + + u64 ept_pointer; + + u16 virtual_processor_id; + u16 padding16_2[3]; + + u64 padding64_2[5]; + u64 guest_physical_address; + + u32 vm_instruction_error; + u32 vm_exit_reason; + u32 vm_exit_intr_info; + u32 vm_exit_intr_error_code; + u32 idt_vectoring_info_field; + u32 idt_vectoring_error_code; + u32 vm_exit_instruction_len; + u32 vmx_instruction_info; + + u64 exit_qualification; + u64 exit_io_instruction_ecx; + u64 exit_io_instruction_esi; + u64 exit_io_instruction_edi; + u64 exit_io_instruction_eip; + + u64 guest_linear_address; + u64 guest_rsp; + u64 guest_rflags; + + u32 guest_interruptibility_info; + u32 cpu_based_vm_exec_control; + u32 exception_bitmap; + u32 vm_entry_controls; + u32 vm_entry_intr_info_field; + u32 vm_entry_exception_error_code; + u32 vm_entry_instruction_len; + u32 tpr_threshold; + + u64 guest_rip; + + u32 hv_clean_fields; + u32 hv_padding_32; + u32 hv_synthetic_controls; + struct { + u32 nested_flush_hypercall:1; + u32 msr_bitmap:1; + u32 reserved:30; + } __packed hv_enlightenments_control; + u32 hv_vp_id; + + u64 hv_vm_id; + u64 partition_assist_page; + u64 padding64_4[4]; + u64 guest_bndcfgs; + u64 padding64_5[7]; + u64 xss_exit_bitmap; + u64 padding64_6[7]; +} __packed; + +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) + +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF + +/* Define synthetic interrupt controller flag constants. */ +#define HV_EVENT_FLAGS_COUNT (256 * 8) +#define HV_EVENT_FLAGS_LONG_COUNT (256 / sizeof(unsigned long)) + +/* + * Synthetic timer configuration. + */ +union hv_stimer_config { + u64 as_uint64; + struct { + u64 enable:1; + u64 periodic:1; + u64 lazy:1; + u64 auto_enable:1; + u64 apic_vector:8; + u64 direct_mode:1; + u64 reserved_z0:3; + u64 sintx:4; + u64 reserved_z1:44; + } __packed; +}; + + +/* Define the synthetic interrupt controller event flags format. */ +union hv_synic_event_flags { + unsigned long flags[HV_EVENT_FLAGS_LONG_COUNT]; +}; + +/* Define SynIC control register. */ +union hv_synic_scontrol { + u64 as_uint64; + struct { + u64 enable:1; + u64 reserved:63; + } __packed; +}; + +/* Define synthetic interrupt source. */ +union hv_synic_sint { + u64 as_uint64; + struct { + u64 vector:8; + u64 reserved1:8; + u64 masked:1; + u64 auto_eoi:1; + u64 reserved2:46; + } __packed; +}; + +/* Define the format of the SIMP register */ +union hv_synic_simp { + u64 as_uint64; + struct { + u64 simp_enabled:1; + u64 preserved:11; + u64 base_simp_gpa:52; + } __packed; +}; + +/* Define the format of the SIEFP register */ +union hv_synic_siefp { + u64 as_uint64; + struct { + u64 siefp_enabled:1; + u64 preserved:11; + u64 base_siefp_gpa:52; + } __packed; +}; + +struct hv_vpset { + u64 format; + u64 valid_bank_mask; + u64 bank_contents[]; +} __packed; + +/* HvCallSendSyntheticClusterIpi hypercall */ +struct hv_send_ipi { + u32 vector; + u32 reserved; + u64 cpu_mask; +} __packed; + +/* HvCallSendSyntheticClusterIpiEx hypercall */ +struct hv_send_ipi_ex { + u32 vector; + u32 reserved; + struct hv_vpset vp_set; +} __packed; + +/* HvFlushGuestPhysicalAddressSpace hypercalls */ +struct hv_guest_mapping_flush { + u64 address_space; + u64 flags; +} __packed; + +/* + * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited + * by the bitwidth of "additional_pages" in union hv_gpa_page_range. + */ +#define HV_MAX_FLUSH_PAGES (2048) + +/* HvFlushGuestPhysicalAddressList hypercall */ +union hv_gpa_page_range { + u64 address_space; + struct { + u64 additional_pages:11; + u64 largepage:1; + u64 basepfn:52; + } page; +}; + +/* + * All input flush parameters should be in single page. The max flush + * count is equal with how many entries of union hv_gpa_page_range can + * be populated into the input parameter page. + */ +#define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \ + sizeof(union hv_gpa_page_range)) + +struct hv_guest_mapping_flush_list { + u64 address_space; + u64 flags; + union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT]; +}; + +/* HvFlushVirtualAddressSpace, HvFlushVirtualAddressList hypercalls */ +struct hv_tlb_flush { + u64 address_space; + u64 flags; + u64 processor_mask; + u64 gva_list[]; +} __packed; + +/* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */ +struct hv_tlb_flush_ex { + u64 address_space; + u64 flags; + struct hv_vpset hv_vp_set; + u64 gva_list[]; +} __packed; + +struct hv_partition_assist_pg { + u32 tlb_lock_count; +}; +#endif From patchwork Fri Oct 25 09:16:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Liu X-Patchwork-Id: 11211813 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 51A0913B1 for ; Fri, 25 Oct 2019 09:18:25 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F8DC2070B for ; Fri, 25 Oct 2019 09:18:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gDETHmi2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F8DC2070B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iNviK-0007nY-N0; Fri, 25 Oct 2019 09:16:56 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iNviI-0007nR-NU for xen-devel@lists.xenproject.org; Fri, 25 Oct 2019 09:16:54 +0000 X-Inumbo-ID: 2a6ff274-f708-11e9-a531-bc764e2007e4 Received: from mail-wm1-x341.google.com (unknown [2a00:1450:4864:20::341]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 2a6ff274-f708-11e9-a531-bc764e2007e4; Fri, 25 Oct 2019 09:16:46 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id 6so3826281wmf.0 for ; Fri, 25 Oct 2019 02:16:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oyowZildIl6aBfU2rN3LvR5y/oh3zpf0zr+JEVy59Do=; b=gDETHmi2XjQbx5sjjeB90uDdcqS307rUbKS1TAPmOqvM04ZgJNDoMTiRQ3nLtCifRL M9af2mYT9HKcPU5uU0MSKbYN7MBPCzj7XirbQIzBrLyjxf9MjBWCmmvtwJHtdlUtQwCF MwSiR/WyLIxKWqT5z12QiwDba40cIGtBo4wt+RV/qdEJ2vE3XfeR+7EIPvfiKJub50h2 sC2jY5icSdas/XKptN/TO5lWdBPmeZFhfwIi8fEPAw0b/SdjM6iFAZpeQnKyQc4bJ2pP 1pdyk6On+iwsqKCdPrDI6b8bifdJtiV/f8WnbHudBphIEoqOaaobqqdXipuZP2Yh/iCZ opEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=oyowZildIl6aBfU2rN3LvR5y/oh3zpf0zr+JEVy59Do=; b=WDdORcLaEQTAP5vBZXDtuUq34icxnrWujDga8I8lwxx/53EJQBvl0hUfFxi9ZRd++h gHvsvqr0cwYSkOYaeBWrg6SpwtAaASIuN/fySXnweUvHo5dlCUQiYMtDq3giR741Bv79 y10aYNUx3TQUsGVzYs+qW9xD9Ml0lAN7ZFKR+w6CK4HNsjb/7kbOuNilpHlbEyv+vA3A mbm5HITQzaUjEKRrnwJqMLP6fmER6VKDGO4sLmBX81/2S+40vR6XjF28lM7SqmDkAfJ9 f2ypH9Bmi9lRs59WQdnrmPRCKucAE0EvX6CeTy192LqpXw+ZsVr3kdfJBubAzG1J8QWG 38rw== X-Gm-Message-State: APjAAAW7NjD3rLsb8sEzWSPoncqd6gQAs5Rsoy2TFcUk2puqiQw87VTx safZG+ZEBWPedol7e3JexZEOkCfwDrU= X-Google-Smtp-Source: APXvYqzevSCZgwL/+PBuT/SnTzP2xltlt/va5z9uABmQru0O0leArOQ6+tu+AzlUW5MdWao8ckaVjw== X-Received: by 2002:a7b:cc6a:: with SMTP id n10mr2653982wmj.94.1571995004779; Fri, 25 Oct 2019 02:16:44 -0700 (PDT) Received: from debian.mshome.net (54.163.200.146.dyn.plus.net. [146.200.163.54]) by smtp.gmail.com with ESMTPSA id b62sm1873283wmc.13.2019.10.25.02.16.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2019 02:16:44 -0700 (PDT) From: Wei Liu X-Google-Original-From: Wei Liu To: Xen Development List Date: Fri, 25 Oct 2019 10:16:13 +0100 Message-Id: <20191025091618.10153-3-liuwe@microsoft.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191025091618.10153-1-liuwe@microsoft.com> References: <20191025091618.10153-1-liuwe@microsoft.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH for-next 2/7] x86: fix up hyperv-tlfs.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Wei Liu , Paul Durrant , Andrew Cooper , Michael Kelley , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Do the following: 1. include xen/types.h and xen/bitops.h 2. fix up invocations of BIT macro Signed-off-by: Wei Liu --- This can be squashed into previous patch if preferred. --- xen/include/asm-x86/guest/hyperv-tlfs.h | 141 ++++++++++++------------ 1 file changed, 71 insertions(+), 70 deletions(-) diff --git a/xen/include/asm-x86/guest/hyperv-tlfs.h b/xen/include/asm-x86/guest/hyperv-tlfs.h index 7741e211f7..ccd9850b27 100644 --- a/xen/include/asm-x86/guest/hyperv-tlfs.h +++ b/xen/include/asm-x86/guest/hyperv-tlfs.h @@ -9,7 +9,8 @@ #ifndef _ASM_X86_HYPERV_TLFS_H #define _ASM_X86_HYPERV_TLFS_H -#include +#include +#include #include /* @@ -19,7 +20,7 @@ * size may not be 4096 on all architectures. */ #define HV_HYP_PAGE_SHIFT 12 -#define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) +#define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT, UL) #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) /* @@ -45,47 +46,47 @@ */ /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ -#define HV_X64_MSR_VP_RUNTIME_AVAILABLE BIT(0) +#define HV_X64_MSR_VP_RUNTIME_AVAILABLE BIT(0, UL) /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ -#define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) +#define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1, UL) /* * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available */ -#define HV_X64_MSR_SYNIC_AVAILABLE BIT(2) +#define HV_X64_MSR_SYNIC_AVAILABLE BIT(2, UL) /* * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through * HV_X64_MSR_STIMER3_COUNT) available */ -#define HV_MSR_SYNTIMER_AVAILABLE BIT(3) +#define HV_MSR_SYNTIMER_AVAILABLE BIT(3, UL) /* * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) * are available */ -#define HV_X64_MSR_APIC_ACCESS_AVAILABLE BIT(4) +#define HV_X64_MSR_APIC_ACCESS_AVAILABLE BIT(4, UL) /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ -#define HV_X64_MSR_HYPERCALL_AVAILABLE BIT(5) +#define HV_X64_MSR_HYPERCALL_AVAILABLE BIT(5, UL) /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ -#define HV_X64_MSR_VP_INDEX_AVAILABLE BIT(6) +#define HV_X64_MSR_VP_INDEX_AVAILABLE BIT(6, UL) /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ -#define HV_X64_MSR_RESET_AVAILABLE BIT(7) +#define HV_X64_MSR_RESET_AVAILABLE BIT(7, UL) /* * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available */ -#define HV_X64_MSR_STAT_PAGES_AVAILABLE BIT(8) +#define HV_X64_MSR_STAT_PAGES_AVAILABLE BIT(8, UL) /* Partition reference TSC MSR is available */ -#define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) +#define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9, UL) /* Partition Guest IDLE MSR is available */ -#define HV_X64_MSR_GUEST_IDLE_AVAILABLE BIT(10) +#define HV_X64_MSR_GUEST_IDLE_AVAILABLE BIT(10, UL) /* * There is a single feature flag that signifies if the partition has access * to MSRs with local APIC and TSC frequencies. */ -#define HV_X64_ACCESS_FREQUENCY_MSRS BIT(11) +#define HV_X64_ACCESS_FREQUENCY_MSRS BIT(11, UL) /* AccessReenlightenmentControls privilege */ -#define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) +#define HV_X64_ACCESS_REENLIGHTENMENT BIT(13, UL) /* * Feature identification: indicates which flags were specified at partition @@ -93,17 +94,17 @@ * defined in section Partition Creation Flags. * These are HYPERV_CPUID_FEATURES.EBX bits. */ -#define HV_X64_CREATE_PARTITIONS BIT(0) -#define HV_X64_ACCESS_PARTITION_ID BIT(1) -#define HV_X64_ACCESS_MEMORY_POOL BIT(2) -#define HV_X64_ADJUST_MESSAGE_BUFFERS BIT(3) -#define HV_X64_POST_MESSAGES BIT(4) -#define HV_X64_SIGNAL_EVENTS BIT(5) -#define HV_X64_CREATE_PORT BIT(6) -#define HV_X64_CONNECT_PORT BIT(7) -#define HV_X64_ACCESS_STATS BIT(8) -#define HV_X64_DEBUGGING BIT(11) -#define HV_X64_CPU_POWER_MANAGEMENT BIT(12) +#define HV_X64_CREATE_PARTITIONS BIT(0, UL) +#define HV_X64_ACCESS_PARTITION_ID BIT(1, UL) +#define HV_X64_ACCESS_MEMORY_POOL BIT(2, UL) +#define HV_X64_ADJUST_MESSAGE_BUFFERS BIT(3, UL) +#define HV_X64_POST_MESSAGES BIT(4, UL) +#define HV_X64_SIGNAL_EVENTS BIT(5, UL) +#define HV_X64_CREATE_PORT BIT(6, UL) +#define HV_X64_CONNECT_PORT BIT(7, UL) +#define HV_X64_ACCESS_STATS BIT(8, UL) +#define HV_X64_DEBUGGING BIT(11, UL) +#define HV_X64_CPU_POWER_MANAGEMENT BIT(12, UL) /* * Feature identification. EDX indicates which miscellaneous features @@ -111,26 +112,26 @@ * These are HYPERV_CPUID_FEATURES.EDX bits. */ /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ -#define HV_X64_MWAIT_AVAILABLE BIT(0) +#define HV_X64_MWAIT_AVAILABLE BIT(0, UL) /* Guest debugging support is available */ -#define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) +#define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1, UL) /* Performance Monitor support is available*/ -#define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) +#define HV_X64_PERF_MONITOR_AVAILABLE BIT(2, UL) /* Support for physical CPU dynamic partitioning events is available*/ -#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) +#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3, UL) /* * Support for passing hypercall input parameter block via XMM * registers is available */ -#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4) +#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4, UL) /* Support for a virtual guest idle state is available */ -#define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) +#define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5, UL) /* Frequency MSRs available */ -#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) +#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8, UL) /* Crash MSR available */ -#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) +#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10, UL) /* stimer Direct Mode is available */ -#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) +#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19, UL) /* * Implementation recommendations. Indicates which behaviors the hypervisor @@ -141,56 +142,56 @@ * Recommend using hypercall for address space switches rather * than MOV to CR3 instruction */ -#define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) +#define HV_X64_AS_SWITCH_RECOMMENDED BIT(0, UL) /* Recommend using hypercall for local TLB flushes rather * than INVLPG or MOV to CR3 instructions */ -#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) +#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1, UL) /* * Recommend using hypercall for remote TLB flushes rather * than inter-processor interrupts */ -#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) +#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2, UL) /* * Recommend using MSRs for accessing APIC registers * EOI, ICR and TPR rather than their memory-mapped counterparts */ -#define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) +#define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3, UL) /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ -#define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) +#define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4, UL) /* * Recommend using relaxed timing for this partition. If used, * the VM should disable any watchdog timeouts that rely on the * timely delivery of external interrupts */ -#define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) +#define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5, UL) /* * Recommend not using Auto End-Of-Interrupt feature */ -#define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) +#define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9, UL) /* * Recommend using cluster IPI hypercalls. */ -#define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) +#define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10, UL) /* Recommend using the newer ExProcessorMasks interface */ -#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) +#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11, UL) /* Recommend using enlightened VMCS */ -#define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) +#define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14, UL) /* * Virtual processor will never share a physical core with another virtual * processor, except for virtual processors that are reported as sibling SMT * threads. */ -#define HV_X64_NO_NONARCH_CORESHARING BIT(18) +#define HV_X64_NO_NONARCH_CORESHARING BIT(18, UL) /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ -#define HV_X64_NESTED_DIRECT_FLUSH BIT(17) -#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) -#define HV_X64_NESTED_MSR_BITMAP BIT(19) +#define HV_X64_NESTED_DIRECT_FLUSH BIT(17, UL) +#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18, UL) +#define HV_X64_NESTED_MSR_BITMAP BIT(19, UL) /* Hyper-V specific model specific registers (MSRs) */ @@ -390,10 +391,10 @@ struct hv_tsc_emulation_status { #define HV_PROCESSOR_POWER_STATE_C2 2 #define HV_PROCESSOR_POWER_STATE_C3 3 -#define HV_FLUSH_ALL_PROCESSORS BIT(0) -#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) -#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) -#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) +#define HV_FLUSH_ALL_PROCESSORS BIT(0, UL) +#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1, UL) +#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2, UL) +#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3, UL) enum HV_GENERIC_SET_FORMAT { HV_GENERIC_SET_SPARSE_4K, @@ -401,7 +402,7 @@ enum HV_GENERIC_SET_FORMAT { }; #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) -#define HV_HYPERCALL_FAST_BIT BIT(16) +#define HV_HYPERCALL_FAST_BIT BIT(16, UL) #define HV_HYPERCALL_VARHEAD_OFFSET 17 #define HV_HYPERCALL_REP_COMP_OFFSET 32 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) @@ -740,22 +741,22 @@ struct hv_enlightened_vmcs { } __packed; #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) -#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14, UL) +#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15, UL) #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF From patchwork Fri Oct 25 09:16:14 2019 Content-Type: text/plain; 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[146.200.163.54]) by smtp.gmail.com with ESMTPSA id b62sm1873283wmc.13.2019.10.25.02.16.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2019 02:16:45 -0700 (PDT) From: Wei Liu X-Google-Original-From: Wei Liu To: Xen Development List Date: Fri, 25 Oct 2019 10:16:14 +0100 Message-Id: <20191025091618.10153-4-liuwe@microsoft.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191025091618.10153-1-liuwe@microsoft.com> References: <20191025091618.10153-1-liuwe@microsoft.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH for-next 3/7] x86/hyperv: extract more information from Hyper-V X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Wei Liu , Paul Durrant , Andrew Cooper , Michael Kelley , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Provide a structure to store that information. The structure will be accessed from other places later so make it public. Signed-off-by: Wei Liu Acked-by: Jan Beulich --- xen/arch/x86/guest/hyperv/hyperv.c | 14 ++++++++++++++ xen/include/asm-x86/guest/hyperv.h | 12 ++++++++++++ 2 files changed, 26 insertions(+) diff --git a/xen/arch/x86/guest/hyperv/hyperv.c b/xen/arch/x86/guest/hyperv/hyperv.c index 7ab4b127f3..041166f344 100644 --- a/xen/arch/x86/guest/hyperv/hyperv.c +++ b/xen/arch/x86/guest/hyperv/hyperv.c @@ -21,6 +21,9 @@ #include #include +#include + +struct ms_hyperv_info ms_hyperv; bool __init hyperv_probe(void) { @@ -36,6 +39,17 @@ bool __init hyperv_probe(void) if ( eax != 0x31237648 ) /* Hv#1 */ return false; + /* Extract more information from Hyper-V */ + ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES); + ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES); + ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO); + + if ( ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED ) + ms_hyperv.nested_features = cpuid_eax(HYPERV_CPUID_NESTED_FEATURES); + + ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS); + ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS); + return true; } diff --git a/xen/include/asm-x86/guest/hyperv.h b/xen/include/asm-x86/guest/hyperv.h index 4b9cc5a836..0f8800040a 100644 --- a/xen/include/asm-x86/guest/hyperv.h +++ b/xen/include/asm-x86/guest/hyperv.h @@ -21,8 +21,20 @@ #ifdef CONFIG_HYPERV_GUEST +#include + #include +struct ms_hyperv_info { + uint32_t features; + uint32_t misc_features; + uint32_t hints; + uint32_t nested_features; + uint32_t max_vp_index; + uint32_t max_lp_index; +}; +extern struct ms_hyperv_info ms_hyperv; + extern struct hypervisor_ops hyperv_ops; bool hyperv_probe(void); From patchwork Fri Oct 25 09:16:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Liu X-Patchwork-Id: 11211805 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2A9A21390 for ; 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[146.200.163.54]) by smtp.gmail.com with ESMTPSA id b62sm1873283wmc.13.2019.10.25.02.16.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2019 02:16:46 -0700 (PDT) From: Wei Liu X-Google-Original-From: Wei Liu To: Xen Development List Date: Fri, 25 Oct 2019 10:16:15 +0100 Message-Id: <20191025091618.10153-5-liuwe@microsoft.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191025091618.10153-1-liuwe@microsoft.com> References: <20191025091618.10153-1-liuwe@microsoft.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH for-next 4/7] x86: add a comment regarding the location of hypervisor_probe X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Wei Liu , Paul Durrant , Andrew Cooper , Michael Kelley , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Signed-off-by: Wei Liu Acked-by: Jan Beulich --- xen/arch/x86/setup.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index cf5a7b8e1e..4aa0af5a12 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -764,6 +764,10 @@ void __init noreturn __start_xen(unsigned long mbi_p) * allocing any xenheap structures wanted in lower memory. */ kexec_early_calculations(); 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[146.200.163.54]) by smtp.gmail.com with ESMTPSA id b62sm1873283wmc.13.2019.10.25.02.16.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2019 02:16:47 -0700 (PDT) From: Wei Liu X-Google-Original-From: Wei Liu To: Xen Development List Date: Fri, 25 Oct 2019 10:16:16 +0100 Message-Id: <20191025091618.10153-6-liuwe@microsoft.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191025091618.10153-1-liuwe@microsoft.com> References: <20191025091618.10153-1-liuwe@microsoft.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH for-next 5/7] x86: use running_on_hypervisor to gate hypervisor_setup X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Wei Liu , Paul Durrant , Andrew Cooper , Michael Kelley , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The hypervisor_setup method is not unique to Xen guest. Signed-off-by: Wei Liu --- xen/arch/x86/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 4aa0af5a12..044c45be36 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1577,7 +1577,7 @@ void __init noreturn __start_xen(unsigned long mbi_p) max_cpus = nr_cpu_ids; } - if ( xen_guest ) + if ( running_on_hypervisor ) hypervisor_setup(); /* Low mappings were only needed for some BIOS table parsing. */ From patchwork Fri Oct 25 09:16:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Liu X-Patchwork-Id: 11211815 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 001CE13B1 for ; Fri, 25 Oct 2019 09:18:29 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CDB732070B for ; Fri, 25 Oct 2019 09:18:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PrKAcuFc" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CDB732070B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iNvie-0007wB-4d; Fri, 25 Oct 2019 09:17:16 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iNvic-0007vZ-Os for xen-devel@lists.xenproject.org; Fri, 25 Oct 2019 09:17:14 +0000 X-Inumbo-ID: 2c831668-f708-11e9-a531-bc764e2007e4 Received: from mail-wm1-x341.google.com (unknown [2a00:1450:4864:20::341]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 2c831668-f708-11e9-a531-bc764e2007e4; Fri, 25 Oct 2019 09:16:49 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id r141so1229289wme.4 for ; Fri, 25 Oct 2019 02:16:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V5mtkW3wpHguw+wyMps6cF9wqpB+EbjhZMYROmJIuZI=; b=PrKAcuFcatKubYH6LW/hGrN6AhBmqb863KdvMZ+oVU9L5KAsgr/MdI1nIDHlrc3NbM 8AAx4OBkOC70lb9f+f8BKBGLvmsbR01JF1Uy3oFh6NsN9+MxBIwELcSsrAZs8/j7FGNE 4IQDyQHEZlUH7X9GXMdzsoIj83HgnrNk9EojFrbfocMUa5fLGff2IyenXlReQDW7JWix ni7M+wxBPXB+wMXiHRf00eCXN81U2LO7jw0SM0qmrwup8xRXMHFuK7PttkYS5bk3/C2g LNsDK6Bxt40Sd4gx5lF730Du6RNQPmodz+uHGmbljmlJ86SWsTc/lJx5wCgSgFSWL9ZO GJlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=V5mtkW3wpHguw+wyMps6cF9wqpB+EbjhZMYROmJIuZI=; b=XjdVD9AqLZsKolQVjOLkwK4XvdqW52rbpK0+A7PGfxuxnk+2oRZqNkmu8VYeufJ3/m Ic9vvaOA8Q87k3OHpwuTU+J1hD8Z+Vm+IrmRWu9uMmGANVhe/+B9iCwsCUg9M627kTTg Eic++EqKm7leQfPhRR/t6O8YHgtKw++IkTlP/v3rRwyznau5kAg2VrZEgmhdDT5OkmtB DxdC463cgVHmQ0q73ptR52GwKgJyYXoO/p2IzFKtucNW8ZBVBCmyfRomA4/CpSA9cml+ 9aLF1aTCPPU3mBqQm12MAvBgBOyHMQkBuTh0EAK5GNc2AiKG1yAvuf2FUw+LPI+bxB4B G/Bw== X-Gm-Message-State: APjAAAW1iClj+scmgvmDcWx69l/JHrWqJGel1WtihKrmaNhTPj4ADhi8 cW0WgLmLL5YmKdmQJBlp5LN4xRmGa6A= X-Google-Smtp-Source: APXvYqwujZ6UmIniBMmFGXl1CHDYKmbV17bB4OtRND/NvnGM+LVw+jq6EXmxS2UcOaQdXqoK9kH4RA== X-Received: by 2002:a05:600c:2152:: with SMTP id v18mr2590496wml.170.1571995008549; Fri, 25 Oct 2019 02:16:48 -0700 (PDT) Received: from debian.mshome.net (54.163.200.146.dyn.plus.net. [146.200.163.54]) by smtp.gmail.com with ESMTPSA id b62sm1873283wmc.13.2019.10.25.02.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2019 02:16:48 -0700 (PDT) From: Wei Liu X-Google-Original-From: Wei Liu To: Xen Development List Date: Fri, 25 Oct 2019 10:16:17 +0100 Message-Id: <20191025091618.10153-7-liuwe@microsoft.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191025091618.10153-1-liuwe@microsoft.com> References: <20191025091618.10153-1-liuwe@microsoft.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH for-next 6/7] x86/hyperv: provide hyperv_guest variable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Wei Liu , Paul Durrant , Andrew Cooper , Michael Kelley , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" It will be used to gate Hyper-V related code outside of the guest directory. No functional change. Signed-off-by: Wei Liu Acked-by: Jan Beulich --- xen/arch/x86/guest/hyperv/hyperv.c | 3 +++ xen/include/asm-x86/guest/hyperv.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/xen/arch/x86/guest/hyperv/hyperv.c b/xen/arch/x86/guest/hyperv/hyperv.c index 041166f344..ee649426ce 100644 --- a/xen/arch/x86/guest/hyperv/hyperv.c +++ b/xen/arch/x86/guest/hyperv/hyperv.c @@ -24,6 +24,7 @@ #include struct ms_hyperv_info ms_hyperv; +bool hyperv_guest; bool __init hyperv_probe(void) { @@ -50,6 +51,8 @@ bool __init hyperv_probe(void) ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS); ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS); + hyperv_guest = true; + return true; } diff --git a/xen/include/asm-x86/guest/hyperv.h b/xen/include/asm-x86/guest/hyperv.h index 0f8800040a..86f5c24ec6 100644 --- a/xen/include/asm-x86/guest/hyperv.h +++ b/xen/include/asm-x86/guest/hyperv.h @@ -35,6 +35,8 @@ struct ms_hyperv_info { }; extern struct ms_hyperv_info ms_hyperv; +extern bool hyperv_guest; + extern struct hypervisor_ops hyperv_ops; bool hyperv_probe(void); From patchwork Fri Oct 25 09:16:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Liu X-Patchwork-Id: 11211819 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A00C7139A for ; Fri, 25 Oct 2019 09:18:40 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 78CDC2070B for ; Fri, 25 Oct 2019 09:18:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="u1Mryk9C" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 78CDC2070B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iNvii-0007yc-DZ; Fri, 25 Oct 2019 09:17:20 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iNvih-0007yB-OO for xen-devel@lists.xenproject.org; Fri, 25 Oct 2019 09:17:19 +0000 X-Inumbo-ID: 2d12897e-f708-11e9-a531-bc764e2007e4 Received: from mail-wr1-x442.google.com (unknown [2a00:1450:4864:20::442]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 2d12897e-f708-11e9-a531-bc764e2007e4; Fri, 25 Oct 2019 09:16:50 +0000 (UTC) Received: by mail-wr1-x442.google.com with SMTP id z11so1408488wro.11 for ; Fri, 25 Oct 2019 02:16:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pFFSinDfDG+eojxO6ZAruZ5d2cmA+pbfzhrKVPc1pNc=; b=u1Mryk9C8zbqSKL/8xx1Kqo2EPGmIUWXfVgp3yUIyORHS2bOKn6TtB0nsdaO01IUOm Elk1yBJsEAgbhsQdOZVYMwYvqvyy7TQdCDeq0mWuy16Zz2bZijjFUZYr/DYFs+wqP6ji Vj3uXac7a1MqkXwNzuTVxIqCsYvQSelrYqrwZeo1LcXvF50KtHhYzjBd6Q6FcvZxKxH6 gfOVdkz2WxrmlhEzZd7H5++vCuIz6g62M66C4LFyf/bce5qld4t3y4rWGvB2EopGeF9g timXMRzellO/sBdJGvvC/yA0Y+eGiC/yp2rqOj/Wesm/eBKanakDmx7rS6I4N+cDji/a vl0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pFFSinDfDG+eojxO6ZAruZ5d2cmA+pbfzhrKVPc1pNc=; b=XjcTsB2jyR0XoS34F/DoeoP05Y7yp/BYSFRwLQv8d/6RkJweDOJtiFfQ0qV8oiGmyM jHZqkJqoOxWguI9afjMk9OkcvOmtufzmgzbOIMLPmlFcKj8nRFaVDUomujQLDsw/3elZ ytoUgGTVfZoNbahqIj1aSwDK4xyBA4hUA/F79lgoh7y4Zhfuq4FIR8M6h9FariuBRsAv Bvd6RccDiNyrMfXiyCurX+o0I9Wl/ovqd0Dlstcdj05Jf0pW4c9SsNYZFDH/q9Wu1sXu RbS5SG3BdT4fS0QUYLvFZciCkv1luVjO7ni3JOLsNyEpCeY16eR3Jc8aqYPrAUhISA0q /png== X-Gm-Message-State: APjAAAWXdsmPQAaIN8bwAxr1GVOT+bSmAcErMGC6iXsBek+Qj/kKbgeF nwzgm0RqjWEVlSes0waf8JxzsLNXyzs= X-Google-Smtp-Source: APXvYqzXA/psT/wMrYqnbfQ2J0JO5Is0SIQaysEdOkAobeYO2cnOUCH7oDIQ1KNuWFgl6A/9vlRUfg== X-Received: by 2002:a5d:6785:: with SMTP id v5mr1950190wru.174.1571995009404; Fri, 25 Oct 2019 02:16:49 -0700 (PDT) Received: from debian.mshome.net (54.163.200.146.dyn.plus.net. [146.200.163.54]) by smtp.gmail.com with ESMTPSA id b62sm1873283wmc.13.2019.10.25.02.16.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2019 02:16:48 -0700 (PDT) From: Wei Liu X-Google-Original-From: Wei Liu To: Xen Development List Date: Fri, 25 Oct 2019 10:16:18 +0100 Message-Id: <20191025091618.10153-8-liuwe@microsoft.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191025091618.10153-1-liuwe@microsoft.com> References: <20191025091618.10153-1-liuwe@microsoft.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH for-next 7/7] x86: implement Hyper-V clock source X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , Wei Liu , Paul Durrant , Andrew Cooper , Michael Kelley , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Implement a clock source using Hyper-V's reference TSC page. Signed-off-by: Wei Liu --- Relevant spec: https://github.com/MicrosoftDocs/Virtualization-Documentation/raw/live/tlfs/Hypervisor%20Top%20Level%20Functional%20Specification%20v5.0C.pdf Section 12.6. --- xen/arch/x86/time.c | 87 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c index d8242295ef..f7e93b8a1f 100644 --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -614,6 +615,89 @@ static struct platform_timesource __initdata plt_xen_timer = }; #endif +#ifdef CONFIG_HYPERV_GUEST +/************************************************************ + * PLATFORM TIMER 6: HYPER-V REFERENCE TSC + */ + +static struct ms_hyperv_tsc_page hyperv_tsc_page __aligned(PAGE_SIZE); + +static int64_t __init init_hyperv_timer(struct platform_timesource *pts) +{ + unsigned long maddr; + uint64_t tsc_msr, freq; + + if ( !hyperv_guest || + !(ms_hyperv.features & HV_MSR_REFERENCE_TSC_AVAILABLE) ) + return 0; + + maddr = virt_to_maddr(&hyperv_tsc_page); + + /* + * Per Hyper-V TLFS: + * 1. Read existing MSR value + * 2. Preserve bits [11:1] + * 3. Set bits [63:12] to be guest physical address of tsc page + * 4. Set enabled bit (0) + * 5. Write back new MSR value + */ + rdmsrl(HV_X64_MSR_REFERENCE_TSC, tsc_msr); + tsc_msr &= GENMASK_ULL(11, 1); + tsc_msr = tsc_msr | (uint64_t)maddr | 1 /* enabled */; + wrmsrl(HV_X64_MSR_REFERENCE_TSC, tsc_msr); + + /* Get TSC frequency from Hyper-V */ + rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); + pts->frequency = freq; + + return freq; +} + +static inline uint64_t read_hyperv_timer(void) +{ + uint64_t scale, offset, ret, tsc; + uint32_t seq; + struct ms_hyperv_tsc_page *tsc_page = &hyperv_tsc_page; + + do { + seq = tsc_page->tsc_sequence; + + /* Seq 0 is special. It means the TSC enlightenment is not + * available at the moment. The reference time can only be + * obtained from the Reference Counter MSR. + */ + if ( seq == 0 ) + { + rdmsrl(HV_X64_MSR_TIME_REF_COUNT, ret); + return ret; + } + + smp_rmb(); + + tsc = rdtsc_ordered(); + scale = tsc_page->tsc_scale; + offset = tsc_page->tsc_offset; + + smp_rmb(); + + } while (tsc_page->tsc_sequence != seq); + + /* x86 has ARCH_SUPPORTS_INT128 */ + ret = (uint64_t)(((__uint128_t)tsc * scale) >> 64) + offset; + + return ret; +} + +static struct platform_timesource __initdata plt_hyperv_timer = +{ + .id = "hyperv", + .name = "HYPER-V REFERENCE TSC", + .read_counter = read_hyperv_timer, + .init = init_hyperv_timer, + .counter_bits = 63, +}; +#endif + /************************************************************ * GENERIC PLATFORM TIMER INFRASTRUCTURE */ @@ -763,6 +847,9 @@ static u64 __init init_platform_timer(void) static struct platform_timesource * __initdata plt_timers[] = { #ifdef CONFIG_XEN_GUEST &plt_xen_timer, +#endif +#ifdef CONFIG_HYPERV_GUEST + &plt_hyperv_timer, #endif &plt_hpet, &plt_pmtimer, &plt_pit };