From patchwork Sat Oct 26 18:01:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213603 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 042C21951 for ; Sat, 26 Oct 2019 18:04:01 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D1A2A20663 for ; Sat, 26 Oct 2019 18:04:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="E9BV1O20" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D1A2A20663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQOJ-00056x-Ry; Sat, 26 Oct 2019 18:02:19 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQOI-00056s-QV for xen-devel@lists.xenproject.org; Sat, 26 Oct 2019 18:02:18 +0000 X-Inumbo-ID: bdf65750-f81a-11e9-beca-bc764e2007e4 Received: from us-smtp-delivery-1.mimecast.com (unknown [207.211.31.81]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id bdf65750-f81a-11e9-beca-bc764e2007e4; Sat, 26 Oct 2019 18:02:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572112934; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dp/nKQVZFywaOMixL/+A3VBgd7NuzQl0q2mvB/663P0=; b=E9BV1O20O3NPRNR+cuCWvbbzxK0fJf+p8cTr9FJvT2i8gx8n2hPEfiQL/65UTPAqInrn+Y b+naFwMJmh90/IzWa6Wl7idW1vgUbH1Ej6uRO1fMpYKLCgLBe1hidKE9SOCHlxOeJ14ngK tnc4KsPuF58+yFO+I8Yu5xP6eeG7UMI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-185-y_q8K36rNAuymAgbbQa5iw-1; Sat, 26 Oct 2019 14:02:10 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 399F5801E72; Sat, 26 Oct 2019 18:02:09 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id EA43A60C57; Sat, 26 Oct 2019 18:01:58 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:24 +0200 Message-Id: <20191026180143.7369-2-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: y_q8K36rNAuymAgbbQa5iw-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 01/20] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , Li Qiang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Philippe Mathieu-Daudé The PIIX4 Southbridge is not used by the PC machine, but by the Malta board (MIPS). Add a new section to keep it covered. Suggested-by: Michael S. Tsirkin Reviewed-by: Aleksandar Markovic Reviewed-by: Li Qiang Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 42e702f346..1f04502fac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c F: hw/pci-host/pam.c F: include/hw/pci-host/q35.h F: include/hw/pci-host/pam.h -F: hw/isa/piix4.c F: hw/isa/lpc_ich9.c F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c @@ -1730,6 +1729,12 @@ F: hw/display/edid* F: include/hw/display/edid.h F: qemu-edid.c +PIIX4 South Bridge (i82371AB) +M: Hervé Poussineau +M: Philippe Mathieu-Daudé +S: Maintained +F: hw/isa/piix4.c + Firmware configuration (fw_cfg) M: Philippe Mathieu-Daudé R: Laszlo Ersek From patchwork Sat Oct 26 18:01:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213605 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E06901920 for ; Sat, 26 Oct 2019 18:04:01 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BA98720663 for ; Sat, 26 Oct 2019 18:04:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="J1qBrkZy" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BA98720663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQOT-00057d-57; Sat, 26 Oct 2019 18:02:29 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQOR-00057U-SG for xen-devel@lists.xenproject.org; Sat, 26 Oct 2019 18:02:27 +0000 X-Inumbo-ID: c4a96acf-f81a-11e9-94d7-12813bfff9fa Received: from us-smtp-1.mimecast.com (unknown [205.139.110.120]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id c4a96acf-f81a-11e9-94d7-12813bfff9fa; Sat, 26 Oct 2019 18:02:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572112946; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=leKb+mxeE3Ab87XsOqKSMcG+BfzCOIRLFQX4loQ4eOE=; b=J1qBrkZymO4kI+AsqO4NLvn9Gqnu4QSf9aHAR2Tl34uvje4/SrtSPq1QlQIgMZMYk/suWt kA64f92Y6JVGLkzEXw+HdkIUw4FamtSFQzQPeVcO7Hz0uBJFOI45eEsjx1PCAQxDA80CTF uH+4ERLMeeRGHivvh2ZphyIQJRBM3OI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-358-sUwBDL4wNaSRj2Jzaozt5w-1; Sat, 26 Oct 2019 14:02:21 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 07D2E800D41; Sat, 26 Oct 2019 18:02:20 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 03ED460C57; Sat, 26 Oct 2019 18:02:09 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:25 +0200 Message-Id: <20191026180143.7369-3-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: sUwBDL4wNaSRj2Jzaozt5w-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 02/20] piix4: Add the Reset Control Register X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , Li Qiang , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Hervé Poussineau The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-7-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic Reviewed-by: Li Qiang [PMD: rebased, updated includes] Signed-off-by: Philippe Mathieu-Daudé --- v3: Use RCR_IOPORT (Li Qiang) --- hw/isa/piix4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 890d999abf..7a1361a9dd 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -2,6 +2,7 @@ * QEMU PIIX4 PCI Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Hervé Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -28,11 +29,17 @@ #include "hw/isa/isa.h" #include "hw/sysbus.h" #include "migration/vmstate.h" +#include "sysemu/reset.h" +#include "sysemu/runstate.h" PCIDevice *piix4_dev; typedef struct PIIX4State { PCIDevice dev; + + /* Reset Control Register */ + MemoryRegion rcr_mem; + uint8_t rcr; } PIIX4State; #define TYPE_PIIX4_PCI_DEVICE "PIIX4" @@ -87,15 +94,51 @@ static const VMStateDescription vmstate_piix4 = { } }; +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int len) +{ + PIIX4State *s = opaque; + + if (val & 4) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + } + + s->rcr = val & 2; /* keep System Reset type only */ +} + +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +{ + PIIX4State *s = opaque; + + return s->rcr; +} + +static const MemoryRegionOps piix4_rcr_ops = { + .read = piix4_rcr_read, + .write = piix4_rcr_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + static void piix4_realize(PCIDevice *dev, Error **errp) { - PIIX4State *d = PIIX4_PCI_DEVICE(dev); + PIIX4State *s = PIIX4_PCI_DEVICE(dev); - if (!isa_bus_new(DEVICE(d), pci_address_space(dev), + if (!isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp)) { return; } - piix4_dev = &d->dev; + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + RCR_IOPORT, &s->rcr_mem, 1); + + piix4_dev = dev; } int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn) From patchwork Sat Oct 26 18:01:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213607 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEF511951 for ; Sat, 26 Oct 2019 18:04:02 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8714E20863 for ; Sat, 26 Oct 2019 18:04:02 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Sat, 26 Oct 2019 18:02:20 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:26 +0200 Message-Id: <20191026180143.7369-4-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: FC2QpnJsMm-UVD5zSnaVRQ-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 03/20] piix4: Add an i8259 Interrupt Controller as specified in datasheet X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Hervé Poussineau Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out. Remove i8259 instanciated in malta board, to not have it twice. We can also remove the now unused piix4_init() function. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-8-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop] Signed-off-by: Philippe Mathieu-Daudé --- v3: - "Add a i8259 -> Add an i8259" in title (Aleksandar) - Changed 16 -> ISA_NUM_IRQS --- hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++----------- hw/mips/mips_malta.c | 32 +++++++++++++------------------- include/hw/i386/pc.h | 1 - 3 files changed, 45 insertions(+), 31 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 7a1361a9dd..7cf72e3118 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -24,6 +24,7 @@ */ #include "qemu/osdep.h" +#include "hw/irq.h" #include "hw/i386/pc.h" #include "hw/pci/pci.h" #include "hw/isa/isa.h" @@ -36,6 +37,8 @@ PCIDevice *piix4_dev; typedef struct PIIX4State { PCIDevice dev; + qemu_irq cpu_intr; + qemu_irq *isa; /* Reset Control Register */ MemoryRegion rcr_mem; @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = { } }; +static void piix4_request_i8259_irq(void *opaque, int irq, int level) +{ + PIIX4State *s = opaque; + qemu_set_irq(s->cpu_intr, level); +} + +static void piix4_set_i8259_irq(void *opaque, int irq, int level) +{ + PIIX4State *s = opaque; + qemu_set_irq(s->isa[irq], level); +} + static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = { static void piix4_realize(PCIDevice *dev, Error **errp) { PIIX4State *s = PIIX4_PCI_DEVICE(dev); + ISABus *isa_bus; + qemu_irq *i8259_out_irq; - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev), - pci_address_space_io(dev), errp)) { + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), + pci_address_space_io(dev), errp); + if (!isa_bus) { return; } + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq, + "isa", ISA_NUM_IRQS); + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr, + "intr", 1); + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT, &s->rcr_mem, 1); + /* initialize i8259 pic */ + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); + s->isa = i8259_init(isa_bus, *i8259_out_irq); + + /* initialize ISA irqs */ + isa_bus_irqs(isa_bus, s->isa); + piix4_dev = dev; } -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn) -{ - PCIDevice *d; - - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4"); - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); - return d->devfn; -} - static void piix4_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index c1c8810e71..6d9b230322 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -97,7 +97,7 @@ typedef struct { SysBusDevice parent_obj; MIPSCPSState cps; - qemu_irq *i8259; + qemu_irq i8259[ISA_NUM_IRQS]; } MaltaState; static ISADevice *pit; @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine) int64_t kernel_entry, bootloader_run_addr; PCIBus *pci_bus; ISABus *isa_bus; - qemu_irq *isa_irq; qemu_irq cbus_irq, i8259_irq; + PCIDevice *pci; int piix4_devfn; I2CBus *smbus; DriveInfo *dinfo; @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine) /* Board ID = 0x420 (Malta Board with CoreLV) */ stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); - /* - * We have a circular dependency problem: pci_bus depends on isa_irq, - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends - * on piix4, and piix4 depends on pci_bus. To stop the cycle we have - * qemu_irq_proxy() adds an extra bit of indirection, allowing us - * to resolve the isa_irq -> i8259 dependency after i8259 is initialized. - */ - isa_irq = qemu_irq_proxy(&s->i8259, 16); - /* Northbridge */ - pci_bus = gt64120_register(isa_irq); + pci_bus = gt64120_register(s->i8259); /* Southbridge */ ide_drive_get(hd, ARRAY_SIZE(hd)); - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80); + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), + true, "PIIX4"); + dev = DEVICE(pci); + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); + piix4_devfn = pci->devfn; - /* - * Interrupt controller - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 - */ - s->i8259 = i8259_init(isa_bus, i8259_irq); + /* Interrupt controller */ + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); + for (int i = 0; i < ISA_NUM_IRQS; i++) { + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i); + } - isa_bus_irqs(isa_bus, s->i8259); pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1); pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci"); smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index f040a72095..f553b29652 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -266,7 +266,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCIBus *find_i440fx(void); /* piix4.c */ extern PCIDevice *piix4_dev; -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); /* pc_sysfw.c */ void pc_system_flash_create(PCMachineState *pcms); From patchwork Sat Oct 26 18:01:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213609 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C6B514ED for ; Sat, 26 Oct 2019 18:04:03 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7714520663 for ; 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Sat, 26 Oct 2019 18:02:43 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5606D60C57; Sat, 26 Oct 2019 18:02:29 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:27 +0200 Message-Id: <20191026180143.7369-5-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: lY_riGLcNZ29LAoQqNPbHA-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 04/20] Revert "irq: introduce qemu_irq_proxy()" X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Esteban Bosse , Thomas Huth , Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , Li Qiang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Philippe Mathieu-Daudé This function isn't used anymore. This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92. Reviewed-by: Thomas Huth Reviewed-by: Li Qiang Reviewed-by: Esteban Bosse Signed-off-by: Philippe Mathieu-Daudé --- hw/core/irq.c | 14 -------------- include/hw/irq.h | 5 ----- 2 files changed, 19 deletions(-) diff --git a/hw/core/irq.c b/hw/core/irq.c index 7cc0295d0e..fb3045b912 100644 --- a/hw/core/irq.c +++ b/hw/core/irq.c @@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2) return qemu_allocate_irq(qemu_splitirq, s, 0); } -static void proxy_irq_handler(void *opaque, int n, int level) -{ - qemu_irq **target = opaque; - - if (*target) { - qemu_set_irq((*target)[n], level); - } -} - -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n) -{ - return qemu_allocate_irqs(proxy_irq_handler, target, n); -} - void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n) { int i; diff --git a/include/hw/irq.h b/include/hw/irq.h index fe527f6f51..24ba0ece11 100644 --- a/include/hw/irq.h +++ b/include/hw/irq.h @@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq); */ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); -/* Returns a new IRQ set which connects 1:1 to another IRQ set, which - * may be set later. - */ -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n); - /* For internal use in qtest. Similar to qemu_irq_split, but operating on an existing vector of qemu_irq. */ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n); From patchwork Sat Oct 26 18:01:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213613 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 792D11920 for ; Sat, 26 Oct 2019 18:04:21 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 539EC20663 for ; Sat, 26 Oct 2019 18:04:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Whx/9GXX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 539EC20663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQP8-0005Ju-6m; Sat, 26 Oct 2019 18:03:10 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQP7-0005Je-KX for xen-devel@lists.xenproject.org; Sat, 26 Oct 2019 18:03:09 +0000 X-Inumbo-ID: ddd145a8-f81a-11e9-bbab-bc764e2007e4 Received: from us-smtp-1.mimecast.com (unknown [207.211.31.81]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id ddd145a8-f81a-11e9-bbab-bc764e2007e4; Sat, 26 Oct 2019 18:03:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572112988; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=V+bPrM8zE9f2ZPzvcaB3nRFmrtGkwHQwxvCglyVobxE=; b=Whx/9GXXT+55XQIIXDRpcTbHNWnueqOktr7BtZ+ckKIbBeTlXj32XHvGC+WtloDAoRamdM Sc8R5RmCZa/DMrMUjgQTaBojHq1xWULfhetCkAjkXUWrxn1vx57XbBf76cHG/IfXQpW8kA uhAZs9RXgS6imKm4A8wCqBF/xkclmr0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-391-6OBl9SKQPDCw2CHjDSEwdQ-1; Sat, 26 Oct 2019 14:03:03 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 712441800DFD; Sat, 26 Oct 2019 18:03:01 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9920C60F82; Sat, 26 Oct 2019 18:02:44 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:28 +0200 Message-Id: <20191026180143.7369-6-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 6OBl9SKQPDCw2CHjDSEwdQ-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 05/20] piix4: Rename PIIX4 object to piix4-isa X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Esteban Bosse , Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , Li Qiang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Hervé Poussineau Other piix4 parts are already named piix4-ide and piix4-usb-uhci. Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-15-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic Reviewed-by: Li Qiang Reviewed-by: Esteban Bosse [PMD: rebased] Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 1 - hw/mips/mips_malta.c | 2 +- include/hw/isa/isa.h | 2 ++ 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 7cf72e3118..fa387919b5 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -45,7 +45,6 @@ typedef struct PIIX4State { uint8_t rcr; } PIIX4State; -#define TYPE_PIIX4_PCI_DEVICE "PIIX4" #define PIIX4_PCI_DEVICE(obj) \ OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 6d9b230322..5086024821 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine) ide_drive_get(hd, ARRAY_SIZE(hd)); pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), - true, "PIIX4"); + true, TYPE_PIIX4_PCI_DEVICE); dev = DEVICE(pci); isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); piix4_devfn = pci->devfn; diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h index 018ada4f6f..79f703fd6c 100644 --- a/include/hw/isa/isa.h +++ b/include/hw/isa/isa.h @@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d) return ISA_BUS(qdev_get_parent_bus(DEVICE(d))); } +#define TYPE_PIIX4_PCI_DEVICE "piix4-isa" + #endif From patchwork Sat Oct 26 18:01:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213615 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C9DE13B1 for ; Sat, 26 Oct 2019 18:04:39 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 727BF20863 for ; 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Sat, 26 Oct 2019 18:03:16 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 0902260C57; Sat, 26 Oct 2019 18:03:01 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:29 +0200 Message-Id: <20191026180143.7369-7-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: f_MbD3CDMIGYapwrrruiHw-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 06/20] piix4: Add an i8257 DMA Controller as specified in datasheet X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Esteban Bosse , Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Hervé Poussineau The i8257 is not a chipset on the Malta board, but is part of the PIIX4 chipset. Create the i8257 in the PIIX4 code, remove the one instantiated in malta board, to not have it twice. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-9-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic Reviewed-by: Esteban Bosse [PMD: rebased, reworded description] Signed-off-by: Philippe Mathieu-Daudé --- v3: Reworded commit description (Li Qiang) --- hw/isa/piix4.c | 4 ++++ hw/mips/mips_malta.c | 2 -- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index fa387919b5..9ebe98bdc3 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -29,6 +29,7 @@ #include "hw/pci/pci.h" #include "hw/isa/isa.h" #include "hw/sysbus.h" +#include "hw/dma/i8257.h" #include "migration/vmstate.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" @@ -167,6 +168,9 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* initialize ISA irqs */ isa_bus_irqs(isa_bus, s->isa); + /* DMA */ + i8257_dma_init(isa_bus, 0); + piix4_dev = dev; } diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 5086024821..44e5f8b26b 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -28,7 +28,6 @@ #include "cpu.h" #include "hw/i386/pc.h" #include "hw/isa/superio.h" -#include "hw/dma/i8257.h" #include "hw/char/serial.h" #include "net/net.h" #include "hw/boards.h" @@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine) smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(NULL, 9), NULL, 0, NULL); pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); - i8257_dma_init(isa_bus, 0); mc146818_rtc_init(isa_bus, 2000, NULL); /* generate SPD EEPROM data */ From patchwork Sat Oct 26 18:01:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213617 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7301113B1 for ; Sat, 26 Oct 2019 18:04:43 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D8B720663 for ; Sat, 26 Oct 2019 18:04:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="OqZQkHvC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4D8B720663 Authentication-Results: mail.kernel.org; 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bh=zOd0udsusP6PV9SSkD8zKTkS3mLJ/h//I9mB8ltdC+8=; b=OqZQkHvCmg2NhmWGc9LT3/aTrpUgP9UTpRb7Ag5rKkLGrQQHySBAbeqKNJjJ37cf50IhE7 JD7rVMly1L14XrzW1saNughHCAGmfiAElgmyPkAbmDNh2h7jwTd0WwgSR7qlowcpBH53Y9 PDIwxNyAj1Kqh+W63PWPl8DuDCZh4R8= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-265-uTTQ-BWHNRq0tavASywL-w-1; Sat, 26 Oct 2019 14:03:23 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1A916107AD25; Sat, 26 Oct 2019 18:03:22 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9C4E760C57; Sat, 26 Oct 2019 18:03:16 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:30 +0200 Message-Id: <20191026180143.7369-8-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: uTTQ-BWHNRq0tavASywL-w-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 07/20] piix4: Add an i8254 PIT Controller as specified in datasheet X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Hervé Poussineau Remove i8254 instanciated in malta board, to not have it twice. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-10-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- v2: Fixed typo (thuth) --- hw/isa/piix4.c | 4 ++++ hw/mips/mips_malta.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 9ebe98bdc3..c07a1e14a8 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -30,6 +30,7 @@ #include "hw/isa/isa.h" #include "hw/sysbus.h" #include "hw/dma/i8257.h" +#include "hw/timer/i8254.h" #include "migration/vmstate.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" @@ -168,6 +169,9 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* initialize ISA irqs */ isa_bus_irqs(isa_bus, s->isa); + /* initialize pit */ + i8254_pit_init(isa_bus, 0x40, 0, NULL); + /* DMA */ i8257_dma_init(isa_bus, 0); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 44e5f8b26b..9af486c77c 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -45,7 +45,6 @@ #include "hw/loader.h" #include "elf.h" #include "hw/rtc/mc146818rtc.h" -#include "hw/timer/i8254.h" #include "exec/address-spaces.h" #include "hw/sysbus.h" /* SysBusDevice */ #include "qemu/host-utils.h" @@ -99,8 +98,6 @@ typedef struct { qemu_irq i8259[ISA_NUM_IRQS]; } MaltaState; -static ISADevice *pit; - static struct _loaderparams { int ram_size, ram_low_size; const char *kernel_filename; @@ -1428,7 +1425,6 @@ void mips_malta_init(MachineState *machine) pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci"); smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(NULL, 9), NULL, 0, NULL); - pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); mc146818_rtc_init(isa_bus, 2000, NULL); /* generate SPD EEPROM data */ From patchwork Sat Oct 26 18:01:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A528D13B1 for ; Sat, 26 Oct 2019 18:04:57 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71DFA20863 for ; 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Sat, 26 Oct 2019 18:03:30 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9557D60F82; Sat, 26 Oct 2019 18:03:22 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:31 +0200 Message-Id: <20191026180143.7369-9-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 04pa6g25PVmIWihwN2uAeA-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 08/20] piix4: Add a MC146818 RTC Controller as specified in datasheet X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Philippe Mathieu-Daudé Remove mc146818rtc instanciated in malta board, to not have it twice. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-13-hpoussin@reactos.org> [PMD: rebased, set RTC base_year to 2000] Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 3 ++- hw/acpi/piix4.c | 2 +- hw/i386/acpi-build.c | 3 +-- hw/i386/pc_piix.c | 1 + hw/isa/piix4.c | 22 ++++++++++++++++++++++ hw/mips/mips_malta.c | 4 +--- include/hw/acpi/piix4.h | 6 ------ include/hw/i386/pc.h | 6 ------ include/hw/southbridge/piix.h | 20 ++++++++++++++++++++ 9 files changed, 48 insertions(+), 19 deletions(-) delete mode 100644 include/hw/acpi/piix4.h create mode 100644 include/hw/southbridge/piix.h diff --git a/MAINTAINERS b/MAINTAINERS index 1f04502fac..90c5ece04b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1235,7 +1235,7 @@ F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c F: hw/acpi/ich9.c F: include/hw/acpi/ich9.h -F: include/hw/acpi/piix4.h +F: include/hw/southbridge/piix.h F: hw/misc/sga.c F: hw/isa/apm.c F: include/hw/isa/apm.h @@ -1734,6 +1734,7 @@ M: Hervé Poussineau M: Philippe Mathieu-Daudé S: Maintained F: hw/isa/piix4.c +F: include/hw/southbridge/piix.h Firmware configuration (fw_cfg) M: Philippe Mathieu-Daudé diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 4e079b39bd..2efd1605b8 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "hw/i386/pc.h" +#include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/isa/apm.h" #include "hw/i2c/pm_smbus.h" @@ -32,7 +33,6 @@ #include "qapi/error.h" #include "qemu/range.h" #include "exec/address-spaces.h" -#include "hw/acpi/piix4.h" #include "hw/acpi/pcihp.h" #include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/cpu.h" diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 9dd3dbb16c..b1b050d8e2 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -34,7 +34,6 @@ #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" #include "hw/acpi/cpu.h" -#include "hw/acpi/piix4.h" #include "hw/nvram/fw_cfg.h" #include "hw/acpi/bios-linker-loader.h" #include "hw/isa/isa.h" @@ -52,7 +51,7 @@ #include "sysemu/reset.h" /* Supported chipsets: */ -#include "hw/acpi/piix4.h" +#include "hw/southbridge/piix.h" #include "hw/acpi/pcihp.h" #include "hw/i386/ich9.h" #include "hw/pci/pci_bus.h" diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index c15929a1f5..a96ede19b2 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -30,6 +30,7 @@ #include "hw/i386/x86.h" #include "hw/i386/pc.h" #include "hw/i386/apic.h" +#include "hw/southbridge/piix.h" #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" #include "hw/pci/pci.h" diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index c07a1e14a8..6bf6f0c5d9 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -24,6 +24,7 @@ */ #include "qemu/osdep.h" +#include "qapi/error.h" #include "hw/irq.h" #include "hw/i386/pc.h" #include "hw/pci/pci.h" @@ -31,6 +32,7 @@ #include "hw/sysbus.h" #include "hw/dma/i8257.h" #include "hw/timer/i8254.h" +#include "hw/rtc/mc146818rtc.h" #include "migration/vmstate.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" @@ -42,6 +44,7 @@ typedef struct PIIX4State { qemu_irq cpu_intr; qemu_irq *isa; + RTCState rtc; /* Reset Control Register */ MemoryRegion rcr_mem; uint8_t rcr; @@ -145,6 +148,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) PIIX4State *s = PIIX4_PCI_DEVICE(dev); ISABus *isa_bus; qemu_irq *i8259_out_irq; + Error *err = NULL; isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev), pci_address_space_io(dev), errp); @@ -175,9 +179,26 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* DMA */ i8257_dma_init(isa_bus, 0); + /* RTC */ + qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus)); + qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); + object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ); + piix4_dev = dev; } +static void piix4_init(Object *obj) +{ + PIIX4State *s = PIIX4_PCI_DEVICE(obj); + + object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC); +} + static void piix4_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -202,6 +223,7 @@ static const TypeInfo piix4_info = { .name = TYPE_PIIX4_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PIIX4State), + .instance_init = piix4_init, .class_init = piix4_class_init, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 9af486c77c..645c223edb 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -26,7 +26,7 @@ #include "qemu/units.h" #include "qemu-common.h" #include "cpu.h" -#include "hw/i386/pc.h" +#include "hw/southbridge/piix.h" #include "hw/isa/superio.h" #include "hw/char/serial.h" #include "net/net.h" @@ -44,7 +44,6 @@ #include "hw/irq.h" #include "hw/loader.h" #include "elf.h" -#include "hw/rtc/mc146818rtc.h" #include "exec/address-spaces.h" #include "hw/sysbus.h" /* SysBusDevice */ #include "qemu/host-utils.h" @@ -1425,7 +1424,6 @@ void mips_malta_init(MachineState *machine) pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci"); smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(NULL, 9), NULL, 0, NULL); - mc146818_rtc_init(isa_bus, 2000, NULL); /* generate SPD EEPROM data */ generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h deleted file mode 100644 index 028bb53e3d..0000000000 --- a/include/hw/acpi/piix4.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef HW_ACPI_PIIX4_H -#define HW_ACPI_PIIX4_H - -#define TYPE_PIIX4_PM "PIIX4_PM" - -#endif diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index f553b29652..c933c0d3a1 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -228,12 +228,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0); #define PORT92_A20_LINE "a20" -/* acpi_piix.c */ - -I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - int smm_enabled, DeviceState **piix4_pm); - /* hpet.c */ extern int no_hpet; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h new file mode 100644 index 0000000000..b8ce26fec4 --- /dev/null +++ b/include/hw/southbridge/piix.h @@ -0,0 +1,20 @@ +/* + * QEMU PIIX South Bridge Emulation + * + * Copyright (c) 2006 Fabrice Bellard + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_SOUTHBRIDGE_PIIX_H +#define HW_SOUTHBRIDGE_PIIX_H + +#define TYPE_PIIX4_PM "PIIX4_PM" + +I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, + qemu_irq sci_irq, qemu_irq smi_irq, + int smm_enabled, DeviceState **piix4_pm); + +#endif From patchwork Sat Oct 26 18:01:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213623 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 017F71515 for ; Sat, 26 Oct 2019 18:05:25 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D025920663 for ; Sat, 26 Oct 2019 18:05:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="cmYmMxTn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D025920663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQPl-0005aT-JN; Sat, 26 Oct 2019 18:03:49 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQPk-0005ZO-7c for xen-devel@lists.xenproject.org; Sat, 26 Oct 2019 18:03:48 +0000 X-Inumbo-ID: f2f54809-f81a-11e9-94d7-12813bfff9fa Received: from us-smtp-1.mimecast.com (unknown [207.211.31.120]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id f2f54809-f81a-11e9-94d7-12813bfff9fa; Sat, 26 Oct 2019 18:03:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572113023; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Lt5h0tf7aQi9H+UHQOfKlnMmiCztk0u8qFBuajQLpTc=; b=cmYmMxTn2sbqERY5JQgmI8OtOSdvId0X5vPppErWxs36QA5mCPy8E2jv6D7RUUsH7Mv5aS 6wYUb0hJMSd/gOOc0KmLrHwO9QNDTlnJYTVUjMXqyzkPz5MT4g3pAWB4t4UlKIGvx64oLX oDbUSY1EzVnArTfh9Z3t1r79+s/hocw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-341-FIb2hg0IP66tzJR3pTmWow-1; Sat, 26 Oct 2019 14:03:40 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id B39BF5E6; Sat, 26 Oct 2019 18:03:38 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2451B60F82; Sat, 26 Oct 2019 18:03:30 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:32 +0200 Message-Id: <20191026180143.7369-10-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: FIb2hg0IP66tzJR3pTmWow-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 09/20] hw/mips/mips_malta: Create IDE hard drive array dynamically X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , Li Qiang , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" In the next commit we'll refactor the PIIX4 code out of mips_malta_init(). As a preliminary step, add the 'ide_drives' variable and create the drive array dynamically. Reviewed-by: Aleksandar Markovic Reviewed-by: Li Qiang Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/mips_malta.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 645c223edb..239ea98ef8 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine) int piix4_devfn; I2CBus *smbus; DriveInfo *dinfo; - DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; + const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS; + DriveInfo **hd; int fl_idx = 0; int be; @@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine) pci_bus = gt64120_register(s->i8259); /* Southbridge */ - ide_drive_get(hd, ARRAY_SIZE(hd)); + hd = g_new(DriveInfo *, ide_drives); + ide_drive_get(hd, ide_drives); pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, TYPE_PIIX4_PCI_DEVICE); @@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine) } pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1); + g_free(hd); pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci"); smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_get_irq(NULL, 9), NULL, 0, NULL); From patchwork Sat Oct 26 18:01:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213621 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8E4C91951 for ; Sat, 26 Oct 2019 18:05:11 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 68B7520663 for ; Sat, 26 Oct 2019 18:05:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="SgusqDay" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 68B7520663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQPu-0005fI-TS; Sat, 26 Oct 2019 18:03:58 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQPt-0005eV-0v for xen-devel@lists.xenproject.org; Sat, 26 Oct 2019 18:03:57 +0000 X-Inumbo-ID: f6ac4c44-f81a-11e9-bbab-bc764e2007e4 Received: from us-smtp-delivery-1.mimecast.com (unknown [205.139.110.61]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id f6ac4c44-f81a-11e9-bbab-bc764e2007e4; Sat, 26 Oct 2019 18:03:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572113029; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4J3P2UfFCzOddbSMsyW2LgzLAlP7e/TG1wlFn/qvUL0=; b=SgusqDay645e31LzxjS//s2yXvv/S7IEtmZgoZ6BqON9FPimuvljFohAGN7ncc20fMwxLs c/fdkhxnCfakup6D+E3A8PNiQSZYBniSJwMwfYlIj9rhJbL4rqK9wCKdsHWMMyQ/whx5dt dHLwFwI0PpiznHsBVRSNPg/tn54Qm4M= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-288-FS2Vq82NMNu9l-_oFimI0A-1; Sat, 26 Oct 2019 14:03:46 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id DB7D6801E6F; Sat, 26 Oct 2019 18:03:44 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4C47C60C80; Sat, 26 Oct 2019 18:03:38 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:33 +0200 Message-Id: <20191026180143.7369-11-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: FS2Vq82NMNu9l-_oFimI0A-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 10/20] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The Malta board instantiate a PIIX4 chipset doing various calls. Refactor all those related calls into a single function: piix4_create(). Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/mips_malta.c | 47 +++++++++++++++++++++++++++----------------- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 239ea98ef8..9014d77b7a 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1210,6 +1210,34 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s, } } +static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, + I2CBus **smbus, size_t ide_buses) +{ + const size_t ide_drives = ide_buses * MAX_IDE_DEVS; + DriveInfo **hd; + PCIDevice *pci; + DeviceState *dev; + + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), + true, TYPE_PIIX4_PCI_DEVICE); + dev = DEVICE(pci); + if (isa_bus) { + *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); + } + + hd = g_new(DriveInfo *, ide_drives); + ide_drive_get(hd, ide_drives); + pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1); + g_free(hd); + pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci"); + if (smbus) { + *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100, + isa_get_irq(NULL, 9), NULL, 0, NULL); + } + + return dev; +} + static void mips_malta_init(MachineState *machine) { @@ -1231,12 +1259,8 @@ void mips_malta_init(MachineState *machine) PCIBus *pci_bus; ISABus *isa_bus; qemu_irq cbus_irq, i8259_irq; - PCIDevice *pci; - int piix4_devfn; I2CBus *smbus; DriveInfo *dinfo; - const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS; - DriveInfo **hd; int fl_idx = 0; int be; @@ -1407,14 +1431,7 @@ void mips_malta_init(MachineState *machine) pci_bus = gt64120_register(s->i8259); /* Southbridge */ - hd = g_new(DriveInfo *, ide_drives); - ide_drive_get(hd, ide_drives); - - pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), - true, TYPE_PIIX4_PCI_DEVICE); - dev = DEVICE(pci); - isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); - piix4_devfn = pci->devfn; + dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS); /* Interrupt controller */ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); @@ -1422,12 +1439,6 @@ void mips_malta_init(MachineState *machine) s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i); } - pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1); - g_free(hd); - pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci"); - smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, - isa_get_irq(NULL, 9), NULL, 0, NULL); - /* generate SPD EEPROM data */ generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]); From patchwork Sat Oct 26 18:01:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213627 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AE9ED13BD for ; Sat, 26 Oct 2019 18:05:35 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 86F3C20663 for ; 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Sat, 26 Oct 2019 18:03:57 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A11A660C57; Sat, 26 Oct 2019 18:03:45 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:34 +0200 Message-Id: <20191026180143.7369-12-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: NGRn1jszN-WVVLXS3MXkEA-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 11/20] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Philippe Mathieu-Daudé Now that we properly refactored the piix4_create() function, let's move it to hw/isa/piix4.c where it belongs, so it can be reused on other places. Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 30 ++++++++++++++++++++++++++++++ hw/mips/gt64xxx_pci.c | 1 + hw/mips/mips_malta.c | 28 ---------------------------- include/hw/i386/pc.h | 2 -- include/hw/southbridge/piix.h | 6 ++++++ 5 files changed, 37 insertions(+), 30 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 6bf6f0c5d9..f3e21ea76d 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -27,12 +27,14 @@ #include "qapi/error.h" #include "hw/irq.h" #include "hw/i386/pc.h" +#include "hw/southbridge/piix.h" #include "hw/pci/pci.h" #include "hw/isa/isa.h" #include "hw/sysbus.h" #include "hw/dma/i8257.h" #include "hw/timer/i8254.h" #include "hw/rtc/mc146818rtc.h" +#include "hw/ide.h" #include "migration/vmstate.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" @@ -237,3 +239,31 @@ static void piix4_register_types(void) } type_init(piix4_register_types) + +DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, + I2CBus **smbus, size_t ide_buses) +{ + size_t ide_drives = ide_buses * MAX_IDE_DEVS; + DriveInfo **hd; + PCIDevice *pci; + DeviceState *dev; + + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), + true, TYPE_PIIX4_PCI_DEVICE); + dev = DEVICE(pci); + if (isa_bus) { + *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); + } + + hd = g_new(DriveInfo *, ide_drives); + ide_drive_get(hd, ide_drives); + pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1); + g_free(hd); + pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci"); + if (smbus) { + *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100, + isa_get_irq(NULL, 9), NULL, 0, NULL); + } + + return dev; +} diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index f325bd6c1c..c277398c0d 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -28,6 +28,7 @@ #include "hw/mips/mips.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" +#include "hw/southbridge/piix.h" #include "migration/vmstate.h" #include "hw/i386/pc.h" #include "hw/irq.h" diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 9014d77b7a..92e9ca5bfa 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1210,34 +1210,6 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s, } } -static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, - I2CBus **smbus, size_t ide_buses) -{ - const size_t ide_drives = ide_buses * MAX_IDE_DEVS; - DriveInfo **hd; - PCIDevice *pci; - DeviceState *dev; - - pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), - true, TYPE_PIIX4_PCI_DEVICE); - dev = DEVICE(pci); - if (isa_bus) { - *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); - } - - hd = g_new(DriveInfo *, ide_drives); - ide_drive_get(hd, ide_drives); - pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1); - g_free(hd); - pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci"); - if (smbus) { - *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100, - isa_get_irq(NULL, 9), NULL, 0, NULL); - } - - return dev; -} - static void mips_malta_init(MachineState *machine) { diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index c933c0d3a1..2fd40ceebe 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -258,8 +258,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type, MemoryRegion *ram_memory); PCIBus *find_i440fx(void); -/* piix4.c */ -extern PCIDevice *piix4_dev; /* pc_sysfw.c */ void pc_system_flash_create(PCMachineState *pcms); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b8ce26fec4..add352456b 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -2,6 +2,7 @@ * QEMU PIIX South Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Hervé Poussineau * * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. @@ -17,4 +18,9 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, int smm_enabled, DeviceState **piix4_pm); +extern PCIDevice *piix4_dev; + +DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, + I2CBus **smbus, size_t ide_buses); + #endif From patchwork Sat Oct 26 18:01:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213625 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 04A201515 for ; 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Sat, 26 Oct 2019 14:04:07 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 89BD3801E6F; Sat, 26 Oct 2019 18:04:05 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A158C60F82; Sat, 26 Oct 2019 18:03:58 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:35 +0200 Message-Id: <20191026180143.7369-13-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: Wf1yjgEwPvmw7DXlBTwPrA-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 12/20] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" These devices implemented their load_state_old() handler 10 years ago, previous to QEMU v0.12. Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines, we can drop this code. Note: the mips_r4k machine started to use the i8254 device just after QEMU v0.5.0, but the MIPS machine types are not versioned, so there is no migration compatibility issue removing this handler. Suggested-by: Peter Maydell Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- hw/acpi/piix4.c | 40 --------------------------------- hw/intc/apic_common.c | 49 ----------------------------------------- hw/pci-host/piix.c | 25 --------------------- hw/timer/i8254_common.c | 40 --------------------------------- 4 files changed, 154 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 2efd1605b8..93aec2dd2c 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -41,7 +41,6 @@ #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/acpi_dev_interface.h" #include "hw/xen/xen.h" -#include "migration/qemu-file-types.h" #include "migration/vmstate.h" #include "hw/core/cpu.h" #include "trace.h" @@ -204,43 +203,6 @@ static const VMStateDescription vmstate_pci_status = { } }; -static int acpi_load_old(QEMUFile *f, void *opaque, int version_id) -{ - PIIX4PMState *s = opaque; - int ret, i; - uint16_t temp; - - ret = pci_device_load(PCI_DEVICE(s), f); - if (ret < 0) { - return ret; - } - qemu_get_be16s(f, &s->ar.pm1.evt.sts); - qemu_get_be16s(f, &s->ar.pm1.evt.en); - qemu_get_be16s(f, &s->ar.pm1.cnt.cnt); - - ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1); - if (ret) { - return ret; - } - - timer_get(f, s->ar.tmr.timer); - qemu_get_sbe64s(f, &s->ar.tmr.overflow_time); - - qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts); - for (i = 0; i < 3; i++) { - qemu_get_be16s(f, &temp); - } - - qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en); - for (i = 0; i < 3; i++) { - qemu_get_be16s(f, &temp); - } - - ret = vmstate_load_state(f, &vmstate_pci_status, - &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1); - return ret; -} - static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id) { PIIX4PMState *s = opaque; @@ -312,8 +274,6 @@ static const VMStateDescription vmstate_acpi = { .name = "piix4_pm", .version_id = 3, .minimum_version_id = 3, - .minimum_version_id_old = 1, - .load_state_old = acpi_load_old, .post_load = vmstate_acpi_post_load, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index aafd8e0e33..375cb6abe9 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -31,7 +31,6 @@ #include "sysemu/kvm.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" -#include "migration/qemu-file-types.h" #include "migration/vmstate.h" static int apic_irq_delivered; @@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev) apic_init_reset(dev); } -/* This function is only used for old state version 1 and 2 */ -static int apic_load_old(QEMUFile *f, void *opaque, int version_id) -{ - APICCommonState *s = opaque; - APICCommonClass *info = APIC_COMMON_GET_CLASS(s); - int i; - - if (version_id > 2) { - return -EINVAL; - } - - /* XXX: what if the base changes? (registered memory regions) */ - qemu_get_be32s(f, &s->apicbase); - qemu_get_8s(f, &s->id); - qemu_get_8s(f, &s->arb_id); - qemu_get_8s(f, &s->tpr); - qemu_get_be32s(f, &s->spurious_vec); - qemu_get_8s(f, &s->log_dest); - qemu_get_8s(f, &s->dest_mode); - for (i = 0; i < 8; i++) { - qemu_get_be32s(f, &s->isr[i]); - qemu_get_be32s(f, &s->tmr[i]); - qemu_get_be32s(f, &s->irr[i]); - } - for (i = 0; i < APIC_LVT_NB; i++) { - qemu_get_be32s(f, &s->lvt[i]); - } - qemu_get_be32s(f, &s->esr); - qemu_get_be32s(f, &s->icr[0]); - qemu_get_be32s(f, &s->icr[1]); - qemu_get_be32s(f, &s->divide_conf); - s->count_shift = qemu_get_be32(f); - qemu_get_be32s(f, &s->initial_count); - s->initial_count_load_time = qemu_get_be64(f); - s->next_time = qemu_get_be64(f); - - if (version_id >= 2) { - s->timer_expiry = qemu_get_be64(f); - } - - if (info->post_load) { - info->post_load(s); - } - return 0; -} - static const VMStateDescription vmstate_apic_common; static void apic_common_realize(DeviceState *dev, Error **errp) @@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = { .name = "apic", .version_id = 3, .minimum_version_id = 3, - .minimum_version_id_old = 1, - .load_state_old = apic_load_old, .pre_load = apic_pre_load, .pre_save = apic_dispatch_pre_save, .post_load = apic_dispatch_post_load, diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 135c645535..2f4cbcbfe9 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -33,7 +33,6 @@ #include "qapi/error.h" #include "qemu/range.h" #include "hw/xen/xen.h" -#include "migration/qemu-file-types.h" #include "migration/vmstate.h" #include "hw/pci-host/pam.h" #include "sysemu/reset.h" @@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev, } } -static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) -{ - PCII440FXState *d = opaque; - PCIDevice *pd = PCI_DEVICE(d); - int ret, i; - uint8_t smm_enabled; - - ret = pci_device_load(pd, f); - if (ret < 0) - return ret; - i440fx_update_memory_mappings(d); - qemu_get_8s(f, &smm_enabled); - - if (version_id == 2) { - for (i = 0; i < PIIX_NUM_PIRQS; i++) { - qemu_get_be32(f); /* dummy load for compatibility */ - } - } - - return 0; -} - static int i440fx_post_load(void *opaque, int version_id) { PCII440FXState *d = opaque; @@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = { .name = "I440FX", .version_id = 3, .minimum_version_id = 3, - .minimum_version_id_old = 1, - .load_state_old = i440fx_load_old, .post_load = i440fx_post_load, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState), diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c index 57bf10cc94..050875b497 100644 --- a/hw/timer/i8254_common.c +++ b/hw/timer/i8254_common.c @@ -29,7 +29,6 @@ #include "qemu/timer.h" #include "hw/timer/i8254.h" #include "hw/timer/i8254_internal.h" -#include "migration/qemu-file-types.h" #include "migration/vmstate.h" /* val must be 0 or 1 */ @@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = { } }; -static int pit_load_old(QEMUFile *f, void *opaque, int version_id) -{ - PITCommonState *pit = opaque; - PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); - PITChannelState *s; - int i; - - if (version_id != 1) { - return -EINVAL; - } - - for (i = 0; i < 3; i++) { - s = &pit->channels[i]; - s->count = qemu_get_be32(f); - qemu_get_be16s(f, &s->latched_count); - qemu_get_8s(f, &s->count_latched); - qemu_get_8s(f, &s->status_latched); - qemu_get_8s(f, &s->status); - qemu_get_8s(f, &s->read_state); - qemu_get_8s(f, &s->write_state); - qemu_get_8s(f, &s->write_latch); - qemu_get_8s(f, &s->rw_mode); - qemu_get_8s(f, &s->mode); - qemu_get_8s(f, &s->bcd); - qemu_get_8s(f, &s->gate); - s->count_load_time = qemu_get_be64(f); - s->irq_disabled = 0; - if (i == 0) { - s->next_transition_time = qemu_get_be64(f); - } - } - if (c->post_load) { - c->post_load(pit); - } - return 0; -} - static int pit_dispatch_pre_save(void *opaque) { PITCommonState *s = opaque; @@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = { .name = "i8254", .version_id = 3, .minimum_version_id = 2, - .minimum_version_id_old = 1, - .load_state_old = pit_load_old, .pre_save = pit_dispatch_pre_save, .post_load = pit_dispatch_post_load, .fields = (VMStateField[]) { From patchwork Sat Oct 26 18:01:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213631 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BD1461515 for ; Sat, 26 Oct 2019 18:05:42 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9760A20663 for ; Sat, 26 Oct 2019 18:05:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="esoYuUUu" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9760A20663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; 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bh=S/Dx+PbxKqebN9kqK3yoqBeSkpzxICQMpRExQnwgy+Q=; b=esoYuUUuzl4aS6rhaNwso9hAqAtgmvEW0OUYglGImXZsG7jqORua197YVvHd20GEsyJD0S 6pwz/qFd1odNTeamZUXyakcPK322ufDrksnffkkKSH/eILhAHQd7+AWzHG10TeGOXsvgX0 FKcdFVeOWoBeV5FhJKV5864lotA5Itk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-6-Tkh2DuxaOcK2hmL4G70YLw-1; Sat, 26 Oct 2019 14:04:20 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id BAEAB5E6; Sat, 26 Oct 2019 18:04:18 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2E3DF60C80; Sat, 26 Oct 2019 18:04:05 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:36 +0200 Message-Id: <20191026180143.7369-14-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: Tkh2DuxaOcK2hmL4G70YLw-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 13/20] hw/pci-host/piix: Extract piix3_create() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Esteban Bosse , Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Extract the PIIX3 creation code from the i440fx_init() function. Reviewed-by: Aleksandar Markovic Reviewed-by: Esteban Bosse Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 20 deletions(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 2f4cbcbfe9..3292703de7 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error **errp) } } +static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) +{ + PIIX3State *piix3; + PCIDevice *pci_dev; + + /* + * Xen supports additional interrupt routes from the PCI devices to + * the IOAPIC: the four pins of each PCI device on the bus are also + * connected to the IOAPIC directly. + * These additional routes can be discovered through ACPI. + */ + if (xen_enabled()) { + pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, + TYPE_PIIX3_XEN_DEVICE); + piix3 = PIIX3_PCI_DEVICE(pci_dev); + pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, + piix3, XEN_PIIX_NUM_PIRQS); + } else { + pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, + TYPE_PIIX3_DEVICE); + piix3 = PIIX3_PCI_DEVICE(pci_dev); + pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, + piix3, PIIX_NUM_PIRQS); + pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); + } + *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + + return piix3; +} + PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCII440FXState **pi440fx_state, int *piix3_devfn, @@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type, PAM_EXPAN_SIZE); } - /* Xen supports additional interrupt routes from the PCI devices to - * the IOAPIC: the four pins of each PCI device on the bus are also - * connected to the IOAPIC directly. - * These additional routes can be discovered through ACPI. */ - if (xen_enabled()) { - PCIDevice *pci_dev = pci_create_simple_multifunction(b, - -1, true, TYPE_PIIX3_XEN_DEVICE); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, - piix3, XEN_PIIX_NUM_PIRQS); - } else { - PCIDevice *pci_dev = pci_create_simple_multifunction(b, - -1, true, TYPE_PIIX3_DEVICE); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, - PIIX_NUM_PIRQS); - pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq); - } + piix3 = piix3_create(b, isa_bus); piix3->pic = pic; - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); - *piix3_devfn = piix3->dev.devfn; ram_size = ram_size / 8 / 1024 / 1024; From patchwork Sat Oct 26 18:01:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213635 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7A11C1515 for ; Sat, 26 Oct 2019 18:06:00 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 545E020663 for ; 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Sat, 26 Oct 2019 18:04:25 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5AB6B60F82; Sat, 26 Oct 2019 18:04:19 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:37 +0200 Message-Id: <20191026180143.7369-15-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: qWviySrFN8a-Vf41-bibzQ-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 14/20] hw/pci-host/piix: Move RCR_IOPORT register definition X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Philippe Mathieu-Daudé The RCR_IOPORT register belongs to the PIIX chipset. Move the definition to "piix.h", and prepend the PIIX prefix. Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- v2: prepend PIIX prefix (Aleksandar) --- hw/i386/acpi-build.c | 2 +- hw/isa/piix4.c | 2 +- hw/pci-host/piix.c | 7 ++++--- include/hw/i386/pc.h | 6 ------ include/hw/southbridge/piix.h | 6 ++++++ 5 files changed, 12 insertions(+), 11 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index b1b050d8e2..266d9b534b 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -209,7 +209,7 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) /* The above need not be conditional on machine type because the reset port * happens to be the same on PIIX (pc) and ICH9 (q35). */ - QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT); + QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT); /* Fill in optional s3/s4 related properties */ o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index f3e21ea76d..86678e6829 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -166,7 +166,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(dev), - RCR_IOPORT, &s->rcr_mem, 1); + PIIX_RCR_IOPORT, &s->rcr_mem, 1); /* initialize i8259 pic */ i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 3292703de7..6548d9a4b5 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -27,6 +27,7 @@ #include "hw/irq.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" +#include "hw/southbridge/piix.h" #include "hw/qdev-properties.h" #include "hw/isa/isa.h" #include "hw/sysbus.h" @@ -87,7 +88,7 @@ typedef struct PIIX3State { /* Reset Control Register contents */ uint8_t rcr; - /* IO memory region for Reset Control Register (RCR_IOPORT) */ + /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ MemoryRegion rcr_mem; } PIIX3State; @@ -695,8 +696,8 @@ static void piix3_realize(PCIDevice *dev, Error **errp) memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, "piix3-reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT, - &d->rcr_mem, 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + PIIX_RCR_IOPORT, &d->rcr_mem, 1); qemu_register_reset(piix3_reset, d); } diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 2fd40ceebe..d6ff95e047 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -240,12 +240,6 @@ typedef struct PCII440FXState PCII440FXState; #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" -/* - * Reset Control Register: PCI-accessible ISA-Compatible Register at address - * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). - */ -#define RCR_IOPORT 0xcf9 - PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCII440FXState **pi440fx_state, int *piix_devfn, ISABus **isa_bus, qemu_irq *pic, diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index add352456b..e49d4a6bbe 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, int smm_enabled, DeviceState **piix4_pm); +/* + * Reset Control Register: PCI-accessible ISA-Compatible Register at address + * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). + */ +#define PIIX_RCR_IOPORT 0xcf9 + extern PCIDevice *piix4_dev; DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, From patchwork Sat Oct 26 18:01:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213633 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3980713BD for ; Sat, 26 Oct 2019 18:05:55 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 13BF520863 for ; Sat, 26 Oct 2019 18:05:55 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Sat, 26 Oct 2019 18:04:37 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3CE2C60F8A; Sat, 26 Oct 2019 18:04:25 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:38 +0200 Message-Id: <20191026180143.7369-16-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: _6dW5Q9nMMG2wCbMLACq5w-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 15/20] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The IRQ Route Control registers definitions belong to the PIIX chipset. We were only defining the 'A' register. Define the other B, C and D registers, and use them. Acked-by: Paul Durrant Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/xen/xen-hvm.c | 5 +++-- hw/mips/gt64xxx_pci.c | 4 ++-- hw/pci-host/piix.c | 9 ++++----- include/hw/southbridge/piix.h | 6 ++++++ 4 files changed, 15 insertions(+), 9 deletions(-) diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 95f23a263c..82ece6b9e7 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -14,6 +14,7 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" #include "hw/i386/pc.h" +#include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/hw.h" #include "hw/i386/apic-msidef.h" @@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len) v = 0; } v &= 0xf; - if (((address + i) >= 0x60) && ((address + i) <= 0x63)) { - xen_set_pci_link_route(xen_domid, address + i - 0x60, v); + if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) { + xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v); } } } diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index c277398c0d..5cab9c1ee1 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ - pic_irq = piix4_dev->config[0x60 + irq_num]; + pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; if (pic_irq < 16) { /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; for (i = 0; i < 4; i++) { - if (pic_irq == piix4_dev->config[0x60 + i]) { + if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { pic_level |= pci_irq_levels[i]; } } diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 6548d9a4b5..390fb9ceba 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -61,7 +61,6 @@ typedef struct I440FXState { #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ #define XEN_PIIX_NUM_PIRQS 128ULL -#define PIIX_PIRQC 0x60 typedef struct PIIX3State { PCIDevice dev; @@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) int pic_irq; uint64_t mask; - pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; + pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >= PIIX_NUM_PIC_IRQS) { return; } @@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) { int pic_irq; - pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; + pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; if (pic_irq >= PIIX_NUM_PIC_IRQS) { return; } @@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level) static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIX3State *piix3 = opaque; - int irq = piix3->dev.config[PIIX_PIRQC + pin]; + int irq = piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; if (irq < PIIX_NUM_PIC_IRQS) { @@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev, uint32_t address, uint32_t val, int len) { pci_default_write_config(dev, address, val, len); - if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { + if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); int pic_irq; diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index e49d4a6bbe..094508b928 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, int smm_enabled, DeviceState **piix4_pm); +/* PIRQRC[A:D]: PIRQx Route Control Registers */ +#define PIIX_PIRQCA 0x60 +#define PIIX_PIRQCB 0x61 +#define PIIX_PIRQCC 0x62 +#define PIIX_PIRQCD 0x63 + /* * Reset Control Register: PCI-accessible ISA-Compatible Register at address * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). From patchwork Sat Oct 26 18:01:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213637 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3AEC71515 for ; Sat, 26 Oct 2019 18:06:12 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 10D5220663 for ; Sat, 26 Oct 2019 18:06:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="YcnMtTyI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 10D5220663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQQv-0006EI-5N; Sat, 26 Oct 2019 18:05:01 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQQt-0006DN-FY for xen-devel@lists.xenproject.org; Sat, 26 Oct 2019 18:04:59 +0000 X-Inumbo-ID: 1a97aedc-f81b-11e9-94d7-12813bfff9fa Received: from us-smtp-1.mimecast.com (unknown [205.139.110.61]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 1a97aedc-f81b-11e9-94d7-12813bfff9fa; Sat, 26 Oct 2019 18:04:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572113090; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=R2lfwmmQaDVAvDlyXppwXQpJKOOvmj7Yic9wf+wTvS4=; b=YcnMtTyI5YBYJHFWCHOiqdtOfBs4A/O7s5qZcJTxKmeZp1pKWgutp6Pf6J2kE+aI448Yeh VrXc8pSB3b66qPORaJcxybmI4hp+yYqNTaiZDexa3bvjmEf3JoUYW4SJHNmkERV3C3FGdL DwJBi2nh+V+tKkL9DB9zrIzOxJU2QJI= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-412-6n8HPc_4M1ehrOinR98oaQ-1; Sat, 26 Oct 2019 14:04:45 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0F8C5100550E; Sat, 26 Oct 2019 18:04:44 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7A2A960C57; Sat, 26 Oct 2019 18:04:38 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:39 +0200 Message-Id: <20191026180143.7369-17-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 6n8HPc_4M1ehrOinR98oaQ-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 16/20] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Philippe Mathieu-Daudé The hw/pci-host/piix.c contains a mix of PIIX3 and i440FX chipsets functions. To be able to split it, we need to export some declarations first. Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + hw/acpi/pcihp.c | 2 +- hw/i386/pc_piix.c | 1 + hw/pci-host/piix.c | 1 + include/hw/i386/pc.h | 22 --------------------- include/hw/pci-host/i440fx.h | 37 ++++++++++++++++++++++++++++++++++++ stubs/pci-host-piix.c | 3 ++- 7 files changed, 43 insertions(+), 24 deletions(-) create mode 100644 include/hw/pci-host/i440fx.h diff --git a/MAINTAINERS b/MAINTAINERS index 90c5ece04b..a48daf0615 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1228,6 +1228,7 @@ F: hw/i386/ F: hw/pci-host/piix.c F: hw/pci-host/q35.c F: hw/pci-host/pam.c +F: include/hw/pci-host/i440fx.h F: include/hw/pci-host/q35.h F: include/hw/pci-host/pam.h F: hw/isa/lpc_ich9.c diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index 82d295b6e8..8413348a33 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "hw/acpi/pcihp.h" -#include "hw/i386/pc.h" +#include "hw/pci-host/i440fx.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bridge.h" #include "hw/acpi/acpi.h" diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index a96ede19b2..ba35d5685e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -30,6 +30,7 @@ #include "hw/i386/x86.h" #include "hw/i386/pc.h" #include "hw/i386/apic.h" +#include "hw/pci-host/i440fx.h" #include "hw/southbridge/piix.h" #include "hw/display/ramfb.h" #include "hw/firmware/smbios.h" diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 390fb9ceba..95b04122fa 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -27,6 +27,7 @@ #include "hw/irq.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" +#include "hw/pci-host/i440fx.h" #include "hw/southbridge/piix.h" #include "hw/qdev-properties.h" #include "hw/isa/isa.h" diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index d6ff95e047..e6fa8418ca 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -231,28 +231,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0); /* hpet.c */ extern int no_hpet; -/* piix_pci.c */ -struct PCII440FXState; -typedef struct PCII440FXState PCII440FXState; - -#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" -#define TYPE_I440FX_PCI_DEVICE "i440FX" - -#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" - -PCIBus *i440fx_init(const char *host_type, const char *pci_type, - PCII440FXState **pi440fx_state, int *piix_devfn, - ISABus **isa_bus, qemu_irq *pic, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io, - ram_addr_t ram_size, - ram_addr_t below_4g_mem_size, - ram_addr_t above_4g_mem_size, - MemoryRegion *pci_memory, - MemoryRegion *ram_memory); - -PCIBus *find_i440fx(void); - /* pc_sysfw.c */ void pc_system_flash_create(PCMachineState *pcms); void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h new file mode 100644 index 0000000000..e327f9bf87 --- /dev/null +++ b/include/hw/pci-host/i440fx.h @@ -0,0 +1,37 @@ +/* + * QEMU i440FX North Bridge Emulation + * + * Copyright (c) 2006 Fabrice Bellard + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef HW_PCI_I440FX_H +#define HW_PCI_I440FX_H + +#include "hw/hw.h" +#include "hw/pci/pci_bus.h" + +typedef struct PCII440FXState PCII440FXState; + +#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" +#define TYPE_I440FX_PCI_DEVICE "i440FX" + +#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" + +PCIBus *i440fx_init(const char *host_type, const char *pci_type, + PCII440FXState **pi440fx_state, int *piix_devfn, + ISABus **isa_bus, qemu_irq *pic, + MemoryRegion *address_space_mem, + MemoryRegion *address_space_io, + ram_addr_t ram_size, + ram_addr_t below_4g_mem_size, + ram_addr_t above_4g_mem_size, + MemoryRegion *pci_memory, + MemoryRegion *ram_memory); + +PCIBus *find_i440fx(void); + +#endif diff --git a/stubs/pci-host-piix.c b/stubs/pci-host-piix.c index 6ed81b1f21..93975adbfe 100644 --- a/stubs/pci-host-piix.c +++ b/stubs/pci-host-piix.c @@ -1,5 +1,6 @@ #include "qemu/osdep.h" -#include "hw/i386/pc.h" +#include "hw/pci-host/i440fx.h" + PCIBus *find_i440fx(void) { return NULL; From patchwork Sat Oct 26 18:01:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213639 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 342A413BD for ; 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Sat, 26 Oct 2019 14:04:55 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A948A100550E; Sat, 26 Oct 2019 18:04:53 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id CF16760F82; Sat, 26 Oct 2019 18:04:44 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:40 +0200 Message-Id: <20191026180143.7369-18-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: f5EgBfXaOa-DEHWA8rl4gg-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 17/20] hw/pci-host/piix: Fix code style issues X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Esteban Bosse , Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" We will move this code, fix its style first. Reviewed-by: Aleksandar Markovic Reviewed-by: Esteban Bosse Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/piix.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 95b04122fa..1544c4726b 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -133,9 +133,10 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); static void piix3_write_config_xen(PCIDevice *dev, uint32_t address, uint32_t val, int len); -/* return the global irq number corresponding to a given device irq - pin. We could also use the bus number to have a more precise - mapping. */ +/* + * Return the global irq number corresponding to a given device irq + * pin. We could also use the bus number to have a more precise mapping. + */ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) { int slot_addend; From patchwork Sat Oct 26 18:01:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213643 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 639E31920 for ; Sat, 26 Oct 2019 18:06:40 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2719420663 for ; Sat, 26 Oct 2019 18:06:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="MelMChvp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2719420663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQR9-0006OR-UZ; Sat, 26 Oct 2019 18:05:15 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQR8-0006Ne-ND for xen-devel@lists.xenproject.org; Sat, 26 Oct 2019 18:05:14 +0000 X-Inumbo-ID: 2788623a-f81b-11e9-beca-bc764e2007e4 Received: from us-smtp-delivery-1.mimecast.com (unknown [205.139.110.61]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 2788623a-f81b-11e9-beca-bc764e2007e4; Sat, 26 Oct 2019 18:05:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572113111; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gEU2sa8mNPEqXZ2spTNDPC26hISKsYbuIvN3+CkX648=; b=MelMChvphYSvVfoztuePtHyer15ol5vd+Or7YwfTO/S6XOMq1zdFyKcg07OlJThfiIqMny OZ6Ekzj0bcoLVbt+WYt/P0h+g0jgQqTKs0bP0aV+QMzy1ptqFqAn7ixPxiaYHWkHAAjDaA 8v4DBxV837mxFCXUjmCDnHVSXxHZ18I= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-226-cRVelFBENyaKSG1Yu-5Lhg-1; Sat, 26 Oct 2019 14:05:04 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1B20B107AD25; Sat, 26 Oct 2019 18:05:03 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 41F5F60C57; Sat, 26 Oct 2019 18:04:54 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:41 +0200 Message-Id: <20191026180143.7369-19-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: cRVelFBENyaKSG1Yu-5Lhg-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 18/20] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Philippe Mathieu-Daudé Move all the PIIX3 functions to a new file: hw/isa/piix3.c. Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- Checkpatch warning: ERROR: spaces required around that '*' (ctx:VxV) #312: FILE: hw/isa/piix3.c:248: + .subsections = (const VMStateDescription*[]) { ^ --- MAINTAINERS | 1 + hw/i386/Kconfig | 1 + hw/isa/Kconfig | 4 + hw/isa/Makefile.objs | 1 + hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++++++ hw/pci-host/Kconfig | 1 - hw/pci-host/piix.c | 402 ---------------------------------- include/hw/southbridge/piix.h | 36 +++ 8 files changed, 442 insertions(+), 403 deletions(-) create mode 100644 hw/isa/piix3.c diff --git a/MAINTAINERS b/MAINTAINERS index a48daf0615..e7e7bfc890 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1231,6 +1231,7 @@ F: hw/pci-host/pam.c F: include/hw/pci-host/i440fx.h F: include/hw/pci-host/q35.h F: include/hw/pci-host/pam.h +F: hw/isa/piix3.c F: hw/isa/lpc_ich9.c F: hw/i2c/smbus_ich9.c F: hw/acpi/piix4.c diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index b25bb6d78a..d420b35548 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -61,6 +61,7 @@ config I440FX select PC_ACPI select ACPI_SMBUS select PCI_PIIX + select PIIX3 select IDE_PIIX select DIMM select SMBIOS diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig index 98a289957e..8a38813cc1 100644 --- a/hw/isa/Kconfig +++ b/hw/isa/Kconfig @@ -29,6 +29,10 @@ config PC87312 select FDC select IDE_ISA +config PIIX3 + bool + select ISA_BUS + config PIIX4 bool # For historical reasons, SuperIO devices are created in the board diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs index ff97485504..8e73960a75 100644 --- a/hw/isa/Makefile.objs +++ b/hw/isa/Makefile.objs @@ -3,6 +3,7 @@ common-obj-$(CONFIG_ISA_SUPERIO) += isa-superio.o common-obj-$(CONFIG_APM) += apm.o common-obj-$(CONFIG_I82378) += i82378.o common-obj-$(CONFIG_PC87312) += pc87312.o +common-obj-$(CONFIG_PIIX3) += piix3.o common-obj-$(CONFIG_PIIX4) += piix4.o common-obj-$(CONFIG_VT82C686) += vt82c686.o common-obj-$(CONFIG_SMC37C669) += smc37c669-superio.o diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c new file mode 100644 index 0000000000..fd1c78879f --- /dev/null +++ b/hw/isa/piix3.c @@ -0,0 +1,399 @@ +/* + * QEMU PIIX PCI ISA Bridge Emulation + * + * Copyright (c) 2006 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/range.h" +#include "hw/southbridge/piix.h" +#include "hw/irq.h" +#include "hw/isa/isa.h" +#include "hw/xen/xen.h" +#include "sysemu/sysemu.h" +#include "sysemu/reset.h" +#include "sysemu/runstate.h" +#include "migration/vmstate.h" + +#define XEN_PIIX_NUM_PIRQS 128ULL + +#define TYPE_PIIX3_PCI_DEVICE "pci-piix3" +#define PIIX3_PCI_DEVICE(obj) \ + OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE) + +#define TYPE_PIIX3_DEVICE "PIIX3" +#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" + +static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) +{ + qemu_set_irq(piix3->pic[pic_irq], + !!(piix3->pic_levels & + (((1ULL << PIIX_NUM_PIRQS) - 1) << + (pic_irq * PIIX_NUM_PIRQS)))); +} + +static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) +{ + int pic_irq; + uint64_t mask; + + pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; + if (pic_irq >= PIIX_NUM_PIC_IRQS) { + return; + } + + mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); + piix3->pic_levels &= ~mask; + piix3->pic_levels |= mask * !!level; +} + +static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +{ + int pic_irq; + + pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; + if (pic_irq >= PIIX_NUM_PIC_IRQS) { + return; + } + + piix3_set_irq_level_internal(piix3, pirq, level); + + piix3_set_irq_pic(piix3, pic_irq); +} + +static void piix3_set_irq(void *opaque, int pirq, int level) +{ + PIIX3State *piix3 = opaque; + piix3_set_irq_level(piix3, pirq, level); +} + +static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) +{ + PIIX3State *piix3 = opaque; + int irq = piix3->dev.config[PIIX_PIRQCA + pin]; + PCIINTxRoute route; + + if (irq < PIIX_NUM_PIC_IRQS) { + route.mode = PCI_INTX_ENABLED; + route.irq = irq; + } else { + route.mode = PCI_INTX_DISABLED; + route.irq = -1; + } + return route; +} + +/* irq routing is changed. so rebuild bitmap */ +static void piix3_update_irq_levels(PIIX3State *piix3) +{ + PCIBus *bus = pci_get_bus(&piix3->dev); + int pirq; + + piix3->pic_levels = 0; + for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { + piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); + } +} + +static void piix3_write_config(PCIDevice *dev, + uint32_t address, uint32_t val, int len) +{ + pci_default_write_config(dev, address, val, len); + if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { + PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); + int pic_irq; + + pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); + piix3_update_irq_levels(piix3); + for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { + piix3_set_irq_pic(piix3, pic_irq); + } + } +} + +static void piix3_write_config_xen(PCIDevice *dev, + uint32_t address, uint32_t val, int len) +{ + xen_piix_pci_write_config_client(address, val, len); + piix3_write_config(dev, address, val, len); +} + +static void piix3_reset(void *opaque) +{ + PIIX3State *d = opaque; + uint8_t *pci_conf = d->dev.config; + + pci_conf[0x04] = 0x07; /* master, memory and I/O */ + pci_conf[0x05] = 0x00; + pci_conf[0x06] = 0x00; + pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ + pci_conf[0x4c] = 0x4d; + pci_conf[0x4e] = 0x03; + pci_conf[0x4f] = 0x00; + pci_conf[0x60] = 0x80; + pci_conf[0x61] = 0x80; + pci_conf[0x62] = 0x80; + pci_conf[0x63] = 0x80; + pci_conf[0x69] = 0x02; + pci_conf[0x70] = 0x80; + pci_conf[0x76] = 0x0c; + pci_conf[0x77] = 0x0c; + pci_conf[0x78] = 0x02; + pci_conf[0x79] = 0x00; + pci_conf[0x80] = 0x00; + pci_conf[0x82] = 0x00; + pci_conf[0xa0] = 0x08; + pci_conf[0xa2] = 0x00; + pci_conf[0xa3] = 0x00; + pci_conf[0xa4] = 0x00; + pci_conf[0xa5] = 0x00; + pci_conf[0xa6] = 0x00; + pci_conf[0xa7] = 0x00; + pci_conf[0xa8] = 0x0f; + pci_conf[0xaa] = 0x00; + pci_conf[0xab] = 0x00; + pci_conf[0xac] = 0x00; + pci_conf[0xae] = 0x00; + + d->pic_levels = 0; + d->rcr = 0; +} + +static int piix3_post_load(void *opaque, int version_id) +{ + PIIX3State *piix3 = opaque; + int pirq; + + /* + * Because the i8259 has not been deserialized yet, qemu_irq_raise + * might bring the system to a different state than the saved one; + * for example, the interrupt could be masked but the i8259 would + * not know that yet and would trigger an interrupt in the CPU. + * + * Here, we update irq levels without raising the interrupt. + * Interrupt state will be deserialized separately through the i8259. + */ + piix3->pic_levels = 0; + for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { + piix3_set_irq_level_internal(piix3, pirq, + pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); + } + return 0; +} + +static int piix3_pre_save(void *opaque) +{ + int i; + PIIX3State *piix3 = opaque; + + for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { + piix3->pci_irq_levels_vmstate[i] = + pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i); + } + + return 0; +} + +static bool piix3_rcr_needed(void *opaque) +{ + PIIX3State *piix3 = opaque; + + return (piix3->rcr != 0); +} + +static const VMStateDescription vmstate_piix3_rcr = { + .name = "PIIX3/rcr", + .version_id = 1, + .minimum_version_id = 1, + .needed = piix3_rcr_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT8(rcr, PIIX3State), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_piix3 = { + .name = "PIIX3", + .version_id = 3, + .minimum_version_id = 2, + .post_load = piix3_post_load, + .pre_save = piix3_pre_save, + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, PIIX3State), + VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, + PIIX_NUM_PIRQS, 3), + VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription*[]) { + &vmstate_piix3_rcr, + NULL + } +}; + + +static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) +{ + PIIX3State *d = opaque; + + if (val & 4) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + } + d->rcr = val & 2; /* keep System Reset type only */ +} + +static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) +{ + PIIX3State *d = opaque; + + return d->rcr; +} + +static const MemoryRegionOps rcr_ops = { + .read = rcr_read, + .write = rcr_write, + .endianness = DEVICE_LITTLE_ENDIAN +}; + +static void piix3_realize(PCIDevice *dev, Error **errp) +{ + PIIX3State *d = PIIX3_PCI_DEVICE(dev); + + if (!isa_bus_new(DEVICE(d), get_system_memory(), + pci_address_space_io(dev), errp)) { + return; + } + + memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, + "piix3-reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(dev), + PIIX_RCR_IOPORT, &d->rcr_mem, 1); + + qemu_register_reset(piix3_reset, d); +} + +static void pci_piix3_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + dc->desc = "ISA bridge"; + dc->vmsd = &vmstate_piix3; + dc->hotpluggable = false; + k->realize = piix3_realize; + k->vendor_id = PCI_VENDOR_ID_INTEL; + /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ + k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; + k->class_id = PCI_CLASS_BRIDGE_ISA; + /* + * Reason: part of PIIX3 southbridge, needs to be wired up by + * pc_piix.c's pc_init1() + */ + dc->user_creatable = false; +} + +static const TypeInfo piix3_pci_type_info = { + .name = TYPE_PIIX3_PCI_DEVICE, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(PIIX3State), + .abstract = true, + .class_init = pci_piix3_class_init, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + +static void piix3_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->config_write = piix3_write_config; +} + +static const TypeInfo piix3_info = { + .name = TYPE_PIIX3_DEVICE, + .parent = TYPE_PIIX3_PCI_DEVICE, + .class_init = piix3_class_init, +}; + +static void piix3_xen_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->config_write = piix3_write_config_xen; +}; + +static const TypeInfo piix3_xen_info = { + .name = TYPE_PIIX3_XEN_DEVICE, + .parent = TYPE_PIIX3_PCI_DEVICE, + .class_init = piix3_xen_class_init, +}; + +static void piix3_register_types(void) +{ + type_register_static(&piix3_pci_type_info); + type_register_static(&piix3_info); + type_register_static(&piix3_xen_info); +} + +type_init(piix3_register_types) + +/* + * Return the global irq number corresponding to a given device irq + * pin. We could also use the bus number to have a more precise mapping. + */ +static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) +{ + int slot_addend; + slot_addend = (pci_dev->devfn >> 3) - 1; + return (pci_intx + slot_addend) & 3; +} + +PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) +{ + PIIX3State *piix3; + PCIDevice *pci_dev; + + /* + * Xen supports additional interrupt routes from the PCI devices to + * the IOAPIC: the four pins of each PCI device on the bus are also + * connected to the IOAPIC directly. + * These additional routes can be discovered through ACPI. + */ + if (xen_enabled()) { + pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, + TYPE_PIIX3_XEN_DEVICE); + piix3 = PIIX3_PCI_DEVICE(pci_dev); + pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, + piix3, XEN_PIIX_NUM_PIRQS); + } else { + pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, + TYPE_PIIX3_DEVICE); + piix3 = PIIX3_PCI_DEVICE(pci_dev); + pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, + piix3, PIIX_NUM_PIRQS); + pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); + } + *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); + + return piix3; +} diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig index 1edc1a31d4..397043b289 100644 --- a/hw/pci-host/Kconfig +++ b/hw/pci-host/Kconfig @@ -32,7 +32,6 @@ config PCI_PIIX bool select PCI select PAM - select ISA_BUS config PCI_EXPRESS_Q35 bool diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 1544c4726b..79ecd58a2b 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -24,22 +24,15 @@ #include "qemu/osdep.h" #include "hw/i386/pc.h" -#include "hw/irq.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" #include "hw/pci-host/i440fx.h" #include "hw/southbridge/piix.h" #include "hw/qdev-properties.h" -#include "hw/isa/isa.h" #include "hw/sysbus.h" #include "qapi/error.h" -#include "qemu/range.h" -#include "hw/xen/xen.h" #include "migration/vmstate.h" #include "hw/pci-host/pam.h" -#include "sysemu/reset.h" -#include "sysemu/runstate.h" -#include "hw/i386/ioapic.h" #include "qapi/visitor.h" #include "qemu/error-report.h" @@ -59,49 +52,9 @@ typedef struct I440FXState { uint32_t short_root_bus; } I440FXState; -#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ -#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ -#define XEN_PIIX_NUM_PIRQS 128ULL - -typedef struct PIIX3State { - PCIDevice dev; - - /* - * bitmap to track pic levels. - * The pic level is the logical OR of all the PCI irqs mapped to it - * So one PIC level is tracked by PIIX_NUM_PIRQS bits. - * - * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with - * pic_irq * PIIX_NUM_PIRQS + pirq - */ -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 -#error "unable to encode pic state in 64bit in pic_levels." -#endif - uint64_t pic_levels; - - qemu_irq *pic; - - /* This member isn't used. Just for save/load compatibility */ - int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; - - /* Reset Control Register contents */ - uint8_t rcr; - - /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ - MemoryRegion rcr_mem; -} PIIX3State; - -#define TYPE_PIIX3_PCI_DEVICE "pci-piix3" -#define PIIX3_PCI_DEVICE(obj) \ - OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE) - #define I440FX_PCI_DEVICE(obj) \ OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE) -#define TYPE_PIIX3_DEVICE "PIIX3" -#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen" - struct PCII440FXState { /*< private >*/ PCIDevice parent_obj; @@ -128,22 +81,6 @@ struct PCII440FXState { */ #define I440FX_COREBOOT_RAM_SIZE 0x57 -static void piix3_set_irq(void *opaque, int pirq, int level); -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx); -static void piix3_write_config_xen(PCIDevice *dev, - uint32_t address, uint32_t val, int len); - -/* - * Return the global irq number corresponding to a given device irq - * pin. We could also use the bus number to have a more precise mapping. - */ -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) -{ - int slot_addend; - slot_addend = (pci_dev->devfn >> 3) - 1; - return (pci_intx + slot_addend) & 3; -} - static void i440fx_update_memory_mappings(PCII440FXState *d) { int i; @@ -333,36 +270,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp) } } -static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) -{ - PIIX3State *piix3; - PCIDevice *pci_dev; - - /* - * Xen supports additional interrupt routes from the PCI devices to - * the IOAPIC: the four pins of each PCI device on the bus are also - * connected to the IOAPIC directly. - * These additional routes can be discovered through ACPI. - */ - if (xen_enabled()) { - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, - TYPE_PIIX3_XEN_DEVICE); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, - piix3, XEN_PIIX_NUM_PIRQS); - } else { - pci_dev = pci_create_simple_multifunction(pci_bus, -1, true, - TYPE_PIIX3_DEVICE); - piix3 = PIIX3_PCI_DEVICE(pci_dev); - pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, - piix3, PIIX_NUM_PIRQS); - pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); - } - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); - - return piix3; -} - PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCII440FXState **pi440fx_state, int *piix3_devfn, @@ -455,312 +362,6 @@ PCIBus *find_i440fx(void) return s ? s->bus : NULL; } -/* PIIX3 PCI to ISA bridge */ -static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) -{ - qemu_set_irq(piix3->pic[pic_irq], - !!(piix3->pic_levels & - (((1ULL << PIIX_NUM_PIRQS) - 1) << - (pic_irq * PIIX_NUM_PIRQS)))); -} - -static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) -{ - int pic_irq; - uint64_t mask; - - pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >= PIIX_NUM_PIC_IRQS) { - return; - } - - mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); - piix3->pic_levels &= ~mask; - piix3->pic_levels |= mask * !!level; -} - -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) -{ - int pic_irq; - - pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >= PIIX_NUM_PIC_IRQS) { - return; - } - - piix3_set_irq_level_internal(piix3, pirq, level); - - piix3_set_irq_pic(piix3, pic_irq); -} - -static void piix3_set_irq(void *opaque, int pirq, int level) -{ - PIIX3State *piix3 = opaque; - piix3_set_irq_level(piix3, pirq, level); -} - -static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) -{ - PIIX3State *piix3 = opaque; - int irq = piix3->dev.config[PIIX_PIRQCA + pin]; - PCIINTxRoute route; - - if (irq < PIIX_NUM_PIC_IRQS) { - route.mode = PCI_INTX_ENABLED; - route.irq = irq; - } else { - route.mode = PCI_INTX_DISABLED; - route.irq = -1; - } - return route; -} - -/* irq routing is changed. so rebuild bitmap */ -static void piix3_update_irq_levels(PIIX3State *piix3) -{ - PCIBus *bus = pci_get_bus(&piix3->dev); - int pirq; - - piix3->pic_levels = 0; - for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq)); - } -} - -static void piix3_write_config(PCIDevice *dev, - uint32_t address, uint32_t val, int len) -{ - pci_default_write_config(dev, address, val, len); - if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { - PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); - int pic_irq; - - pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); - piix3_update_irq_levels(piix3); - for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { - piix3_set_irq_pic(piix3, pic_irq); - } - } -} - -static void piix3_write_config_xen(PCIDevice *dev, - uint32_t address, uint32_t val, int len) -{ - xen_piix_pci_write_config_client(address, val, len); - piix3_write_config(dev, address, val, len); -} - -static void piix3_reset(void *opaque) -{ - PIIX3State *d = opaque; - uint8_t *pci_conf = d->dev.config; - - pci_conf[0x04] = 0x07; /* master, memory and I/O */ - pci_conf[0x05] = 0x00; - pci_conf[0x06] = 0x00; - pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */ - pci_conf[0x4c] = 0x4d; - pci_conf[0x4e] = 0x03; - pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x80; - pci_conf[0x61] = 0x80; - pci_conf[0x62] = 0x80; - pci_conf[0x63] = 0x80; - pci_conf[0x69] = 0x02; - pci_conf[0x70] = 0x80; - pci_conf[0x76] = 0x0c; - pci_conf[0x77] = 0x0c; - pci_conf[0x78] = 0x02; - pci_conf[0x79] = 0x00; - pci_conf[0x80] = 0x00; - pci_conf[0x82] = 0x00; - pci_conf[0xa0] = 0x08; - pci_conf[0xa2] = 0x00; - pci_conf[0xa3] = 0x00; - pci_conf[0xa4] = 0x00; - pci_conf[0xa5] = 0x00; - pci_conf[0xa6] = 0x00; - pci_conf[0xa7] = 0x00; - pci_conf[0xa8] = 0x0f; - pci_conf[0xaa] = 0x00; - pci_conf[0xab] = 0x00; - pci_conf[0xac] = 0x00; - pci_conf[0xae] = 0x00; - - d->pic_levels = 0; - d->rcr = 0; -} - -static int piix3_post_load(void *opaque, int version_id) -{ - PIIX3State *piix3 = opaque; - int pirq; - - /* Because the i8259 has not been deserialized yet, qemu_irq_raise - * might bring the system to a different state than the saved one; - * for example, the interrupt could be masked but the i8259 would - * not know that yet and would trigger an interrupt in the CPU. - * - * Here, we update irq levels without raising the interrupt. - * Interrupt state will be deserialized separately through the i8259. - */ - piix3->pic_levels = 0; - for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { - piix3_set_irq_level_internal(piix3, pirq, - pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq)); - } - return 0; -} - -static int piix3_pre_save(void *opaque) -{ - int i; - PIIX3State *piix3 = opaque; - - for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { - piix3->pci_irq_levels_vmstate[i] = - pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i); - } - - return 0; -} - -static bool piix3_rcr_needed(void *opaque) -{ - PIIX3State *piix3 = opaque; - - return (piix3->rcr != 0); -} - -static const VMStateDescription vmstate_piix3_rcr = { - .name = "PIIX3/rcr", - .version_id = 1, - .minimum_version_id = 1, - .needed = piix3_rcr_needed, - .fields = (VMStateField[]) { - VMSTATE_UINT8(rcr, PIIX3State), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription vmstate_piix3 = { - .name = "PIIX3", - .version_id = 3, - .minimum_version_id = 2, - .post_load = piix3_post_load, - .pre_save = piix3_pre_save, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX3State), - VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, - PIIX_NUM_PIRQS, 3), - VMSTATE_END_OF_LIST() - }, - .subsections = (const VMStateDescription*[]) { - &vmstate_piix3_rcr, - NULL - } -}; - - -static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) -{ - PIIX3State *d = opaque; - - if (val & 4) { - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - return; - } - d->rcr = val & 2; /* keep System Reset type only */ -} - -static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) -{ - PIIX3State *d = opaque; - - return d->rcr; -} - -static const MemoryRegionOps rcr_ops = { - .read = rcr_read, - .write = rcr_write, - .endianness = DEVICE_LITTLE_ENDIAN -}; - -static void piix3_realize(PCIDevice *dev, Error **errp) -{ - PIIX3State *d = PIIX3_PCI_DEVICE(dev); - - if (!isa_bus_new(DEVICE(d), get_system_memory(), - pci_address_space_io(dev), errp)) { - return; - } - - memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d, - "piix3-reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(dev), - PIIX_RCR_IOPORT, &d->rcr_mem, 1); - - qemu_register_reset(piix3_reset, d); -} - -static void pci_piix3_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - dc->desc = "ISA bridge"; - dc->vmsd = &vmstate_piix3; - dc->hotpluggable = false; - k->realize = piix3_realize; - k->vendor_id = PCI_VENDOR_ID_INTEL; - /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ - k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; - k->class_id = PCI_CLASS_BRIDGE_ISA; - /* - * Reason: part of PIIX3 southbridge, needs to be wired up by - * pc_piix.c's pc_init1() - */ - dc->user_creatable = false; -} - -static const TypeInfo piix3_pci_type_info = { - .name = TYPE_PIIX3_PCI_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIX3State), - .abstract = true, - .class_init = pci_piix3_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - -static void piix3_class_init(ObjectClass *klass, void *data) -{ - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->config_write = piix3_write_config; -} - -static const TypeInfo piix3_info = { - .name = TYPE_PIIX3_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, - .class_init = piix3_class_init, -}; - -static void piix3_xen_class_init(ObjectClass *klass, void *data) -{ - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->config_write = piix3_write_config_xen; -}; - -static const TypeInfo piix3_xen_info = { - .name = TYPE_PIIX3_XEN_DEVICE, - .parent = TYPE_PIIX3_PCI_DEVICE, - .class_init = piix3_xen_class_init, -}; - static void i440fx_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -922,9 +523,6 @@ static void i440fx_register_types(void) { type_register_static(&i440fx_info); type_register_static(&igd_passthrough_i440fx_info); - type_register_static(&piix3_pci_type_info); - type_register_static(&piix3_info); - type_register_static(&piix3_xen_info); type_register_static(&i440fx_pcihost_info); } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 094508b928..152628c6d9 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -12,6 +12,8 @@ #ifndef HW_SOUTHBRIDGE_PIIX_H #define HW_SOUTHBRIDGE_PIIX_H +#include "hw/pci/pci.h" + #define TYPE_PIIX4_PM "PIIX4_PM" I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, @@ -30,8 +32,42 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, */ #define PIIX_RCR_IOPORT 0xcf9 +#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ +#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ + +typedef struct PIIXState { + PCIDevice dev; + + /* + * bitmap to track pic levels. + * The pic level is the logical OR of all the PCI irqs mapped to it + * So one PIC level is tracked by PIIX_NUM_PIRQS bits. + * + * PIRQ is mapped to PIC pins, we track it by + * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with + * pic_irq * PIIX_NUM_PIRQS + pirq + */ +#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 +#error "unable to encode pic state in 64bit in pic_levels." +#endif + uint64_t pic_levels; + + qemu_irq *pic; + + /* This member isn't used. Just for save/load compatibility */ + int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; + + /* Reset Control Register contents */ + uint8_t rcr; + + /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */ + MemoryRegion rcr_mem; +} PIIX3State; + extern PCIDevice *piix4_dev; +PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); + DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus, size_t ide_buses); From patchwork Sat Oct 26 18:01:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213645 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D96213BD for ; Sat, 26 Oct 2019 18:06:42 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DC9C520663 for ; Sat, 26 Oct 2019 18:06:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="PwJmEDct" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DC9C520663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQRO-0006Yl-Fb; Sat, 26 Oct 2019 18:05:30 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iOQRN-0006Y6-Gf for xen-devel@lists.xenproject.org; Sat, 26 Oct 2019 18:05:29 +0000 X-Inumbo-ID: 2e3c41aa-f81b-11e9-94d7-12813bfff9fa Received: from us-smtp-delivery-1.mimecast.com (unknown [205.139.110.61]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 2e3c41aa-f81b-11e9-94d7-12813bfff9fa; Sat, 26 Oct 2019 18:05:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1572113123; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=j8Ov6K9gjAmVTeZvfxxVP3jRwrZORnzk/ILSZphq89g=; b=PwJmEDctsDpdJtc4GRteVT9CvV6qcyzmdsS2QNA2ZVpt/Uj8h8kMpQsZHXXWWuTTTV38N4 e6oTrXnhscL4eyftUdLzebrDZukiwg9RIDnr+zrUquwx13q2uGYb/RUgiagnp7ZvqHlKhL ITWCyekeJ9ceGA/dgsCxGPTH0cu78WM= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-264-3CIxaGxPOjetHYqQ8eIT6A-1; Sat, 26 Oct 2019 14:05:19 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 9DE5E1800E00; Sat, 26 Oct 2019 18:05:17 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C12AD60F8A; Sat, 26 Oct 2019 18:05:03 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:42 +0200 Message-Id: <20191026180143.7369-20-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 3CIxaGxPOjetHYqQ8eIT6A-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 19/20] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx' X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Philippe Mathieu-Daudé We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c, it now only contains i440FX northbridge code. Rename it to match the chipset modelled. Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- hw/i386/Kconfig | 2 +- hw/pci-host/Kconfig | 2 +- hw/pci-host/Makefile.objs | 2 +- hw/pci-host/{piix.c => i440fx.c} | 0 5 files changed, 4 insertions(+), 4 deletions(-) rename hw/pci-host/{piix.c => i440fx.c} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index e7e7bfc890..87e7fb1a65 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1225,7 +1225,7 @@ M: Marcel Apfelbaum S: Supported F: include/hw/i386/ F: hw/i386/ -F: hw/pci-host/piix.c +F: hw/pci-host/i440fx.c F: hw/pci-host/q35.c F: hw/pci-host/pam.c F: include/hw/pci-host/i440fx.h diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d420b35548..5a494342ea 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -60,7 +60,7 @@ config I440FX select PC_PCI select PC_ACPI select ACPI_SMBUS - select PCI_PIIX + select PCI_I440FX select PIIX3 select IDE_PIIX select DIMM diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig index 397043b289..b0aa8351c4 100644 --- a/hw/pci-host/Kconfig +++ b/hw/pci-host/Kconfig @@ -28,7 +28,7 @@ config PCI_SABRE select PCI bool -config PCI_PIIX +config PCI_I440FX bool select PCI select PAM diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs index a9cd3e022d..efd752b766 100644 --- a/hw/pci-host/Makefile.objs +++ b/hw/pci-host/Makefile.objs @@ -13,7 +13,7 @@ common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o common-obj-$(CONFIG_PCI_SABRE) += sabre.o common-obj-$(CONFIG_FULONG) += bonito.o -common-obj-$(CONFIG_PCI_PIIX) += piix.o +common-obj-$(CONFIG_PCI_I440FX) += i440fx.o common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o diff --git a/hw/pci-host/piix.c b/hw/pci-host/i440fx.c similarity index 100% rename from hw/pci-host/piix.c rename to hw/pci-host/i440fx.c From patchwork Sat Oct 26 18:01:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11213649 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8A3751515 for ; Sat, 26 Oct 2019 18:06:50 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 650FA20663 for ; Sat, 26 Oct 2019 18:06:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="gjvbuaCv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 650FA20663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; 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bh=WQsFUyLAwDljpdipMYVdl0GqrBsJ3XrvhlsEYkdcey4=; b=gjvbuaCvY68k0tG73B0o8YxEku85CRaX2rxLRRszoqJFdMA/p64FAhoML6qsVHXDOGJTy4 n0W+IbwOyY3BHc8Keh/4+zZImBbDnCkjrOHJK5w6sUqHO9xuh67meCOsGCH3cIVcfGyFfF s+Q39GGO9MzBHyKREKN3jx5OOol4GFg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-34-DrSHE9VQP-SzjnH1n34PiQ-1; Sat, 26 Oct 2019 14:05:34 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C37B71800E00; Sat, 26 Oct 2019 18:05:32 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-39.brq.redhat.com [10.40.204.39]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6A27A60C83; Sat, 26 Oct 2019 18:05:18 +0000 (UTC) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Sat, 26 Oct 2019 20:01:43 +0200 Message-Id: <20191026180143.7369-21-philmd@redhat.com> In-Reply-To: <20191026180143.7369-1-philmd@redhat.com> References: <20191026180143.7369-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: DrSHE9VQP-SzjnH1n34PiQ-1 X-Mimecast-Spam-Score: 0 Subject: [Xen-devel] [PATCH v3 20/20] hw/pci-host/i440fx: Remove the last PIIX3 traces X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Eduardo Habkost , Paul Durrant , Aleksandar Markovic , "Michael S. Tsirkin" , xen-devel@lists.xenproject.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Marcel Apfelbaum , Igor Mammedov , Anthony Perard , Paolo Bonzini , Aleksandar Rikalo , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The PIIX3 is not tied to the i440FX and can even be used without it. Move its creation to the machine code (pc_piix.c). We have now removed the last trace of southbridge code in the i440FX northbridge. Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc_piix.c | 8 +++++++- hw/pci-host/i440fx.c | 8 -------- include/hw/pci-host/i440fx.h | 3 +-- 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index ba35d5685e..2aefa3b8df 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -192,14 +192,20 @@ static void pc_init1(MachineState *machine, gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); if (pcmc->pci_enabled) { + PIIX3State *piix3; + pci_bus = i440fx_init(host_type, pci_type, - &i440fx_state, &piix3_devfn, &isa_bus, x86ms->gsi, + &i440fx_state, system_memory, system_io, machine->ram_size, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size, pci_memory, ram_memory); pcms->bus = pci_bus; + + piix3 = piix3_create(pci_bus, &isa_bus); + piix3->pic = x86ms->gsi; + piix3_devfn = piix3->dev.devfn; } else { pci_bus = NULL; i440fx_state = NULL; diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index 79ecd58a2b..f27131102d 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -27,7 +27,6 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" #include "hw/pci-host/i440fx.h" -#include "hw/southbridge/piix.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "qapi/error.h" @@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp) PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCII440FXState **pi440fx_state, - int *piix3_devfn, - ISABus **isa_bus, qemu_irq *pic, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, ram_addr_t ram_size, @@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCIBus *b; PCIDevice *d; PCIHostState *s; - PIIX3State *piix3; PCII440FXState *f; unsigned i; I440FXState *i440fx; @@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type, PAM_EXPAN_SIZE); } - piix3 = piix3_create(b, isa_bus); - piix3->pic = pic; - *piix3_devfn = piix3->dev.devfn; - ram_size = ram_size / 8 / 1024 / 1024; if (ram_size > 255) { ram_size = 255; diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h index e327f9bf87..f54e6466e4 100644 --- a/include/hw/pci-host/i440fx.h +++ b/include/hw/pci-host/i440fx.h @@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState; #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" PCIBus *i440fx_init(const char *host_type, const char *pci_type, - PCII440FXState **pi440fx_state, int *piix_devfn, - ISABus **isa_bus, qemu_irq *pic, + PCII440FXState **pi440fx_state, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, ram_addr_t ram_size,