From patchwork Sun Oct 27 16:18:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214187 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B515112C for ; Sun, 27 Oct 2019 16:18:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D546C214AF for ; Sun, 27 Oct 2019 16:18:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="fuZKY1Gw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727295AbfJ0QSQ (ORCPT ); Sun, 27 Oct 2019 12:18:16 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:39843 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727008AbfJ0QSQ (ORCPT ); Sun, 27 Oct 2019 12:18:16 -0400 Received: by mail-wm1-f67.google.com with SMTP id r141so6674233wme.4; Sun, 27 Oct 2019 09:18:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l2pKUClZPs6kJxYKVc9s3ay4DPVtu8eC20YF9cqpcPI=; b=fuZKY1Gwot9PXbdi2F0wFKeeUjfJaM8qcBUEEIAcOoEfGOkP8ISPg68uLOAqKjU/zV gxOYOedqSMEtXUZ/eVc8E3Z4snEmY16p65SFrIFEZ+ssrsOhiQIp8qEW988N7tm4j+v8 GKm3RY37S7u35/GOsMJcLlw7oHLwyN1CIZJJdQ6aVEXHYHe3fgzAhztZ0+dMg0sMb5Dd NS8ced3UpEBqX+np36zo2dGDKSrgrbr/e4ibJhaaxF40LwkbsNHnTl6mbCVIXgL6tpdG fQnKelPXoQs/met8AQg2y3NtSoU4xbqyKSYTagtJpy+89PYHPkwqKy/NbM6IintphWGW hSaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l2pKUClZPs6kJxYKVc9s3ay4DPVtu8eC20YF9cqpcPI=; b=OTyxTu7LH42QKVt/8NomroryCbdzd1423CsCnZQeTOxncmixnHW/KMrRhbMYCk9+WR je+R1FpbGilCTysEgM2sv8uWdCRO/qQ9HBqkl2SvlSsL+Gw6txQGBVG7Myvj9J/921aC qUF2piUToP4ZKpfB/eGD5cH4fODH5xPZR+CdywA738OorkWwLSqC7lKPWuKGFms7DG1+ n26S9RfuY7u0JdM0xzma0QanOWEmiTj30OT7irzX4S2z9+K5QoHlgzu8nK0WOHGIvJm4 xJ3fkJ62DXtpED4j5YOGtte2H2IqaBQKbKGyuqSQ1hF8QBZnlLnIoGRxUDit41Jjqjbx KBmg== X-Gm-Message-State: APjAAAVXnIMa1tSxP4mLscCqk3pROROXHBBgWI6+yN/6ruKMqaEMthbo vx3SamuCFC/WjrVMMkXxSuk= X-Google-Smtp-Source: APXvYqzdDF+BTs3CmnmqR/OMrHlFL2KK0vQNMdUQU2ukI3jHraGwiggiPz8BvE9c9Q3Z2hXogtSkKg== X-Received: by 2002:a1c:6146:: with SMTP id v67mr12265207wmb.102.1572193093558; Sun, 27 Oct 2019 09:18:13 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id j14sm9585014wrj.35.2019.10.27.09.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:18:12 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl , Rob Herring Subject: [PATCH v2 1/5] dt-bindings: clock: meson8b: add the clock inputs Date: Sun, 27 Oct 2019 17:18:01 +0100 Message-Id: <20191027161805.1176321-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> References: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The clock controller on Meson8/Meson8b/Meson8m2 has three (known) inputs: - "xtal": the main 24MHz crystal - "ddr_pll": some of the audio clocks use the output of the DDR PLL as input - "clk_32k": an optional clock signal which can be connected to GPIOAO_6 (which then has to be switched to the CLK_32K_IN function) Add the inputs to the documentation so we can wire up these inputs in a follow-up patch. Reviewed-by: Rob Herring Signed-off-by: Martin Blumenstingl --- .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt index 4d94091c1d2d..cc51e4746b3b 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt @@ -11,6 +11,11 @@ Required Properties: - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs - #clock-cells: should be 1. - #reset-cells: should be 1. +- clocks: list of clock phandles, one for each entry in clock-names +- clock-names: should contain the following: + * "xtal": the 24MHz system oscillator + * "ddr_pll": the DDR PLL clock + * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN) Parent node should have the following properties : - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" From patchwork Sun Oct 27 16:18:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214201 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D371A1864 for ; Sun, 27 Oct 2019 16:18:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B195821D80 for ; Sun, 27 Oct 2019 16:18:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="eh1WeQJU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727670AbfJ0QSS (ORCPT ); Sun, 27 Oct 2019 12:18:18 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:36339 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727280AbfJ0QSR (ORCPT ); Sun, 27 Oct 2019 12:18:17 -0400 Received: by mail-wm1-f65.google.com with SMTP id c22so6694626wmd.1; Sun, 27 Oct 2019 09:18:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CPQNzivuVZNWDtPwgDvWYp9o/YTaW3TY1ny0gNcTyh8=; b=eh1WeQJUqLqmNq7P5g77WEfxAuW9neRhh+Met5oYqfM/347j8sLtzsTSeh334FZcke mdSDPnwhvk9xiHA8r404dwDpMZQfA+3v7HOFnzcNVF01PiBTcW7xaRUBKAAVPPffJWUp n8TH/PSO82uFK1dIBcVzajImWj23r6JJmJOMKLXqwoXG7ycIbJj2vbn/2K5OInyOFCMc e4ePBKVK8O5xCHy8FQoUhdTP0Hz9TL4fFH0sLCzwsorlgV9cD3GbHGCnv9Qw9Bv/Mvd8 TAjg0bZuKIGThrBMSx2Wj03CnIsphlJsMouXd2kqscALnb1TFq/oDfoZHP8HdCOJCYRX 8Tcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CPQNzivuVZNWDtPwgDvWYp9o/YTaW3TY1ny0gNcTyh8=; b=eogpjbzX8qnPiypKVhb4O6j/HLSiFkLLA1/LM3wLLrUxueQhvCFofzko6z7+af5+LU FP/PFte15i6NyjKgTrX00/uIvXK5pkJl4tGBY495illKZswdrOV9mJ+O/6jPZS5IXwbc zVnUZq1RzZwk8J78qIqXb6QCyMCaXKszVeyohjOJmzG4AXVox/5mAYrwkUHBLR0D/n87 p2xspfoLI+34EVsRFKd9pYmh53n39w0aRGMQVyS7t3kXMaDLw2uqRe3WWZMgfzeIX7NJ 8Qmg3bcWhlEjk5PLPHZEK2zCTFYMl1Wzkim9Ykb2kZFp+MGNLI0k0SdMJ+jbeRRrqfCV O5uw== X-Gm-Message-State: APjAAAUo7QKr3qcwHMfHEc9DEhmBidMAw1cxmYSvvEmoZuQXerfTn9ve Tiz4G+cH+25N85gOZA2gcas= X-Google-Smtp-Source: APXvYqz30NtrWX/wc/G4NZzRKZdUoiVvN3FqVKpNKl42zjz3/qQTlrYB1xwMJ+Fi2jVmhppWcoPaMQ== X-Received: by 2002:a1c:b4c2:: with SMTP id d185mr11147241wmf.159.1572193094673; Sun, 27 Oct 2019 09:18:14 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id j14sm9585014wrj.35.2019.10.27.09.18.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:18:14 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 2/5] clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier Date: Sun, 27 Oct 2019 17:18:02 +0100 Message-Id: <20191027161805.1176321-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> References: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Switch from clk_set_parent() to clk_hw_set_parent() now that we have a way to configure a mux clock based on clk_hw pointers. This simplifies the meson8b_cpu_clk_notifier_cb logic. No functional changes. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 67e6691e080c..d376f80e806d 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3585,7 +3585,7 @@ static const struct reset_control_ops meson8b_clk_reset_ops = { struct meson8b_nb_data { struct notifier_block nb; - struct clk_hw_onecell_data *onecell_data; + struct clk_hw *cpu_clk; }; static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb, @@ -3593,30 +3593,25 @@ static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb, { struct meson8b_nb_data *nb_data = container_of(nb, struct meson8b_nb_data, nb); - struct clk_hw **hws = nb_data->onecell_data->hws; - struct clk_hw *cpu_clk_hw, *parent_clk_hw; - struct clk *cpu_clk, *parent_clk; + struct clk_hw *parent_clk; int ret; switch (event) { case PRE_RATE_CHANGE: - parent_clk_hw = hws[CLKID_XTAL]; + /* xtal */ + parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0); break; case POST_RATE_CHANGE: - parent_clk_hw = hws[CLKID_CPU_SCALE_OUT_SEL]; + /* cpu_scale_out_sel */ + parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1); break; default: return NOTIFY_DONE; } - cpu_clk_hw = hws[CLKID_CPUCLK]; - cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw)); - - parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw)); - - ret = clk_set_parent(cpu_clk, parent_clk); + ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk); if (ret) return notifier_from_errno(ret); @@ -3695,7 +3690,7 @@ static void __init meson8b_clkc_init_common(struct device_node *np, return; } - meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data; + meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK]; /* * FIXME we shouldn't program the muxes in notifier handlers. The From patchwork Sun Oct 27 16:18:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214197 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 12717112C for ; Sun, 27 Oct 2019 16:18:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DA4A521D7F for ; Sun, 27 Oct 2019 16:18:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="bdPbhc4O" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727728AbfJ0QSa (ORCPT ); Sun, 27 Oct 2019 12:18:30 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:37257 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727008AbfJ0QSS (ORCPT ); Sun, 27 Oct 2019 12:18:18 -0400 Received: by mail-wm1-f65.google.com with SMTP id q130so6693357wme.2; Sun, 27 Oct 2019 09:18:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+ELKKDirjp0oZPBJ44VpnYEwyvsV3MSi9kYfRjT4vis=; b=bdPbhc4OqjdEq4Y+pgsjRiDeliZB157wJfKIzj+AJrpxZ6o4UT9EOSAFZVR63LQkB6 t4pdEo8HWxpZ43uX4pDzgpHoRw9Dq9KTQyHowOPRhNvU3/WByYQYWpCKKakGz0KQzDMd 661DcknhVvnOX7Q5jiY4bFIBeGjCzCC4MNkUQW4AF2VwPyZmFwqksRXVgViTztlyRpTM t6UOKoq56CiYlEE4tUKLH0DPG0ptvUcs+rC+LVJyLItruxLiTFPnTsZb4evV/QaDhKAT 7NIVSHGZElnuTptOHZkmP6rRXb/35cnlwpwQ/q+3LwNfEC/4x4IALzM7OeJysMuHE4WD MlyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ELKKDirjp0oZPBJ44VpnYEwyvsV3MSi9kYfRjT4vis=; b=YIbNGH8juH4uaFHRX7if3bltVmsWSeonXoDLEhkCX0DCPZ8TGAwELqswwHuPYs4VGs pVgVwrY0Q+uS4hvfnZXIQJYjOUu14fuX578Sn5v5sh6apZIq7Whh3ZaOiLFP8IbkOhwt dWyhqYVU60iId9be2+DDKcSSDHNNOrZlOhMGsDAlMCtnKwVptgTTzOWP1QxiY2kNMWyI 8odLe4eLaNVK+3YKWoSgMbpXB60mqHMDBLAh4v1J7uwbFjLQI1cQcZJ8jowZnEfxmZ01 s8TX9CAd70zqCr1zkeecvRY7SBmD9oZbbWkSGCBDKLhEjkEYm46pJyoqLlmBrzpYOgrG mrcw== X-Gm-Message-State: APjAAAXOpe/DNb6vinINdZSB8KZr3LSCCrHkV25GliOyEon2DG2ylTE/ wwu4WxznCayUCMC+QnMGcFk= X-Google-Smtp-Source: APXvYqzYzg6sKc3cDWdXql+bGhHA9n8UawIXHVxcqwjHlZ0xvQiwjrziZqNi1JNlyIGoX4qHoiK1xA== X-Received: by 2002:a1c:1901:: with SMTP id 1mr11970983wmz.28.1572193095906; Sun, 27 Oct 2019 09:18:15 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id j14sm9585014wrj.35.2019.10.27.09.18.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:18:15 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 3/5] clk: meson: meson8b: change references to the XTAL clock to use the name Date: Sun, 27 Oct 2019 17:18:03 +0100 Message-Id: <20191027161805.1176321-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> References: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The XTAL clock is an actual crystal which is mounted on the PCB. Thus the meson8b clock controller driver should not provide the XTAL clock. The meson8b clock controller driver must not use references to the meson8b_xtal clock anymore before we can provide the XTAL clock via OF. Replace the references to the meson8b_xtal.hw by using clk_parent_data.name = "xtal" (along with index = -1) because this works regardless how the XTAL clock is registered (either as fixed-clock in the .dtb or - if missing - when registered in the meson8b clock controller driver). Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 73 ++++++++++++++++++++----------------- 1 file changed, 39 insertions(+), 34 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index d376f80e806d..b785b67baf2b 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -97,8 +97,9 @@ static struct clk_regmap meson8b_fixed_pll_dco = { .hw.init = &(struct clk_init_data){ .name = "fixed_pll_dco", .ops = &meson_clk_pll_ro_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .name = "xtal", + .index = -1, }, .num_parents = 1, }, @@ -162,8 +163,9 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { /* sometimes also called "HPLL" or "HPLL PLL" */ .name = "hdmi_pll_dco", .ops = &meson_clk_pll_ro_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .name = "xtal", + .index = -1, }, .num_parents = 1, }, @@ -237,8 +239,9 @@ static struct clk_regmap meson8b_sys_pll_dco = { .hw.init = &(struct clk_init_data){ .name = "sys_pll_dco", .ops = &meson_clk_pll_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .name = "xtal", + .index = -1, }, .num_parents = 1, }, @@ -631,9 +634,9 @@ static struct clk_regmap meson8b_cpu_in_sel = { .hw.init = &(struct clk_init_data){ .name = "cpu_in_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw, - &meson8b_sys_pll.hw, + .parent_data = (const struct clk_parent_data[]) { + { .name = "xtal", .index = -1, }, + { .hw = &meson8b_sys_pll.hw, }, }, .num_parents = 2, .flags = (CLK_SET_RATE_PARENT | @@ -736,9 +739,9 @@ static struct clk_regmap meson8b_cpu_clk = { .hw.init = &(struct clk_init_data){ .name = "cpu_clk", .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw, - &meson8b_cpu_scale_out_sel.hw, + .parent_data = (const struct clk_parent_data[]) { + { .name = "xtal", .index = -1, }, + { .hw = &meson8b_cpu_scale_out_sel.hw, }, }, .num_parents = 2, .flags = (CLK_SET_RATE_PARENT | @@ -758,12 +761,12 @@ static struct clk_regmap meson8b_nand_clk_sel = { .name = "nand_clk_sel", .ops = &clk_regmap_mux_ops, /* FIXME all other parents are unknown: */ - .parent_hws = (const struct clk_hw *[]) { - &meson8b_fclk_div4.hw, - &meson8b_fclk_div3.hw, - &meson8b_fclk_div5.hw, - &meson8b_fclk_div7.hw, - &meson8b_xtal.hw, + .parent_data = (const struct clk_parent_data[]) { + { .hw = &meson8b_fclk_div4.hw, }, + { .hw = &meson8b_fclk_div3.hw, }, + { .hw = &meson8b_fclk_div5.hw, }, + { .hw = &meson8b_fclk_div7.hw, }, + { .name = "xtal", .index = -1, }, }, .num_parents = 5, .flags = CLK_SET_RATE_PARENT, @@ -1721,8 +1724,9 @@ static struct clk_regmap meson8b_hdmi_sys_sel = { .name = "hdmi_sys_sel", .ops = &clk_regmap_mux_ro_ops, /* FIXME: all other parents are unknown */ - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .name = "xtal", + .index = -1, }, .num_parents = 1, .flags = CLK_SET_RATE_NO_REPARENT, @@ -1767,14 +1771,14 @@ static struct clk_regmap meson8b_hdmi_sys = { * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only * has mali_0 and no glitch-free mux. */ -static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = { - &meson8b_xtal.hw, - &meson8b_mpll2.hw, - &meson8b_mpll1.hw, - &meson8b_fclk_div7.hw, - &meson8b_fclk_div4.hw, - &meson8b_fclk_div3.hw, - &meson8b_fclk_div5.hw, +static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = { + { .name = "xtal", .index = -1, }, + { .hw = &meson8b_mpll2.hw, }, + { .hw = &meson8b_mpll1.hw, }, + { .hw = &meson8b_fclk_div7.hw, }, + { .hw = &meson8b_fclk_div4.hw, }, + { .hw = &meson8b_fclk_div3.hw, }, + { .hw = &meson8b_fclk_div5.hw, }, }; static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 }; @@ -1789,8 +1793,8 @@ static struct clk_regmap meson8b_mali_0_sel = { .hw.init = &(struct clk_init_data){ .name = "mali_0_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_mali_0_1_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws), + .parent_data = meson8b_mali_0_1_parent_data, + .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data), /* * Don't propagate rate changes up because the only changeable * parents are mpll1 and mpll2 but we need those for audio and @@ -1844,8 +1848,8 @@ static struct clk_regmap meson8b_mali_1_sel = { .hw.init = &(struct clk_init_data){ .name = "mali_1_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_mali_0_1_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws), + .parent_data = meson8b_mali_0_1_parent_data, + .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data), /* * Don't propagate rate changes up because the only changeable * parents are mpll1 and mpll2 but we need those for audio and @@ -1944,8 +1948,9 @@ static struct clk_regmap meson8m2_gp_pll_dco = { .hw.init = &(struct clk_init_data){ .name = "gp_pll_dco", .ops = &meson_clk_pll_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .name = "xtal", + .index = -1, }, .num_parents = 1, }, From patchwork Sun Oct 27 16:18:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC7DE1515 for ; Sun, 27 Oct 2019 16:18:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B98B521D7F for ; Sun, 27 Oct 2019 16:18:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="Y8fcd9UW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727280AbfJ0QST (ORCPT ); Sun, 27 Oct 2019 12:18:19 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:40519 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727668AbfJ0QST (ORCPT ); Sun, 27 Oct 2019 12:18:19 -0400 Received: by mail-wr1-f66.google.com with SMTP id o28so7367722wro.7; Sun, 27 Oct 2019 09:18:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bQ1b11JrQMPNCzMJaz+y6q1nSpUtkZ5R8/joJD6Qz18=; b=Y8fcd9UWEz8ZhI1HAXrUApECbzToLMV/0EZ4fsDzW1oo4Ol5ePz6Mm0IxAvoezYzkd s2HnNydcCJv30Wka6Ei4vvbv3sGYXS3vGn+EIkzxzyoLPVuQLSHdgpH1Wt2d4Z/B8BdC vwy9UVXLVY+1ivTt5j5Mrczx1aYKocrKk/+TbT1TbTqnhFBbm4pt41AwNWMWy/2loU6R 8MwwkEwMHjYrTq9P+STJ9fu5Khe5PQf3VSDGkdNDMRq8nQGh21rnLrjwEztWyVtuhWfP 6ktxynw0Cn3bBFAzb+sXi8HpEnJ81eQ/yyXQHCve4AtjTzyGmCGDpVzZGdFqSRzriwA7 Sz5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bQ1b11JrQMPNCzMJaz+y6q1nSpUtkZ5R8/joJD6Qz18=; b=Rr/pFyba/EcsSziZ9hOPFcOPbPMVQLkQU0xEg85FHmUvY2rO6NUPNtOxxBtU0ACpLV eWhZaJ8AveDxAScrzcKAbIAOpaY66wogtS0mB15ffssXz00wWGeZO/wC3H5WsTNGckU9 Vx27S4u3XbsorDVQtOxuiLEw09YIbEfv1vmIPfi/bee0aPkC1pUsLfK46dbHoHGa/Gpl NZ2SeEYqGBDRjBrD5VhjDSxWj3saX/BZJ5stLiMuYiV3rTgY2rGAPq7CvPPoZ5GNDV5Z Q3d0KXaZOwQp50M+Jt61c2+b3QCMs5WDYBBJX2kVlDISO/Sfw4ry3ndD7Lr/FK64n5R2 YvrA== X-Gm-Message-State: APjAAAWK1N3LzTxHtYLgN8JrhBm59oaOock/WqM8T+llyY7FVHwxerHK I5CqeSjaFMNE5ls2QaJDkIs7+Zlb94UEpg== X-Google-Smtp-Source: APXvYqysISP879oRde/djghIAdFy/7j14R2KbsTb23U1GvaSj/8vP8LRd3LHDN3ZcXn4lnSWEN3ZWg== X-Received: by 2002:adf:dec7:: with SMTP id i7mr2473253wrn.134.1572193096993; Sun, 27 Oct 2019 09:18:16 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id j14sm9585014wrj.35.2019.10.27.09.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:18:16 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 4/5] clk: meson: meson8b: don't register the XTAL clock when provided via OF Date: Sun, 27 Oct 2019 17:18:04 +0100 Message-Id: <20191027161805.1176321-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> References: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The XTAL clock is an actual crystal on the PCB. Thus the meson8b clock driver should not register the XTAL clock - instead it should be provided via .dts and then passed to the clock controller. Skip the registration of the XTAL clock if a parent clock is provided via OF. Fall back to registering the XTAL clock if this is not the case to keep support for old .dtbs. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index b785b67baf2b..70ac6755607e 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3682,10 +3682,16 @@ static void __init meson8b_clkc_init_common(struct device_node *np, meson8b_clk_regmaps[i]->map = map; /* - * register all clks - * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 + * always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the + * XTAL clock as input. */ - for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) { + if (!IS_ERR(of_clk_get_by_name(np, "xtal"))) + i = CLKID_PLL_FIXED; + else + i = CLKID_XTAL; + + /* register all clks */ + for (; i < CLK_NR_CLKS; i++) { /* array might be sparse */ if (!clk_hw_onecell_data->hws[i]) continue; From patchwork Sun Oct 27 16:18:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214193 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3192E1515 for ; Sun, 27 Oct 2019 16:18:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0559A21850 for ; Sun, 27 Oct 2019 16:18:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="efsrM2L5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727709AbfJ0QSW (ORCPT ); Sun, 27 Oct 2019 12:18:22 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:35607 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727693AbfJ0QSV (ORCPT ); Sun, 27 Oct 2019 12:18:21 -0400 Received: by mail-wm1-f67.google.com with SMTP id v6so6706831wmj.0; Sun, 27 Oct 2019 09:18:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FLfO/KxjQrMiblT1/Pl6tSGizwnToQmABBG15vNjp4k=; b=efsrM2L5u58xFefwyRkML00CgeJKs665otWTyjbA2/ddI+1FTIC5bCoiYJ3dLqCbk5 9Jj+1rgdcQjZvwk0HpeVxT97hjQ7QTUoH43jqmlSQt/YSq5nuymzxS3XWU8bWpvUvsU3 bUlNzLbT9ZGAjvdUr8mLjT7/59ebbwMRaEzIZmd+22YNY8dyhQ8OYdzvSTadFdlipOz1 I+jMzks8pkqYHLa28CwBBowmr68LB1OUP3W8fWAqjU636SO0ryrIdpJhwpeAYTFdCFRS VQuPoAKs3/7846wSlaBTTpUcDnJGnGRqMwWKvUFqOO/I6INNbYFGwEjzMLHTG+2Mpvvn /rZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FLfO/KxjQrMiblT1/Pl6tSGizwnToQmABBG15vNjp4k=; b=FvII2T3J9qLMN4nifJ8Slj8GNuyPfIOXlZnxEf2KrxN472b4N91A5st4YKppBG34mI Usu+e+vh7njAd0rndReEnBD6qqIRA6AGG01xZtbchyzf0E3WW8elTzOlpiuREvpYJg7b IavoiUJzkwk+WE2jQvS++dk6MjzMtIntj02WpUvqCOD2FDxOgWNUR1ANk4SyhlqQcZpu +1YsIHrB/ATpkEcn/Zs6hCcjVCurQOs7dhcbXktO7R5RoGxwXda+PEhTSgwDKAHtyi08 wWkkucKXV6bxPu3pDu09tZ9cggXcwsaOBqWXR2iC5k0e9f1nVEtf5brfV6br2pBgf3fU 6kjQ== X-Gm-Message-State: APjAAAUY+eZsp+jCGCIDeAIGKW7xg7mCcnrB8dpP7bn1jKHfaNIHcbOW wHVwBfc1EXbAu/W0Qi8wKTk= X-Google-Smtp-Source: APXvYqxcOwu2+Gf57BhS5TKGfe523w4Dkovl72D5JIuM/RKVfzS8lFfJXOVG73aoyklxUxyiYLJVyg== X-Received: by 2002:a1c:4907:: with SMTP id w7mr11688747wma.62.1572193098092; Sun, 27 Oct 2019 09:18:18 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id j14sm9585014wrj.35.2019.10.27.09.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:18:17 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 5/5] ARM: dts: meson: provide the XTAL clock using a fixed-clock Date: Sun, 27 Oct 2019 17:18:05 +0100 Message-Id: <20191027161805.1176321-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> References: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The clock controller driver has provided the XTAL clock so far. This does not match how the hardware actually works because the XTAL clock is an actual crystal which is mounted on the PCB. Add the "xtal" clock to meson.dtsi and replace all references to the clock controller's CLKID_XTAL with the new xtal clock node. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson.dtsi | 7 +++++++ arch/arm/boot/dts/meson6.dtsi | 7 ------- arch/arm/boot/dts/meson8.dtsi | 15 ++++++++------- arch/arm/boot/dts/meson8b-ec100.dts | 2 +- arch/arm/boot/dts/meson8b-mxq.dts | 2 +- arch/arm/boot/dts/meson8b-odroidc1.dts | 2 +- arch/arm/boot/dts/meson8b.dtsi | 15 ++++++++------- 7 files changed, 26 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index c4447f6c8b2c..5d198309058a 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -282,4 +282,11 @@ }; }; }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; }; /* end of / */ diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index 2d31b7ce3f8c..4716030a48d0 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -36,13 +36,6 @@ ranges = <0x0 0xd0000000 0x40000>; }; - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - clk81: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 5a7e3e5caebe..4f59a4c8f036 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -455,6 +455,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -529,8 +531,7 @@ &saradc { compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; - clocks = <&clkc CLKID_XTAL>, - <&clkc CLKID_SAR_ADC>; + clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; amlogic,hhi-sysctrl = <&hhi>; nvmem-cells = <&temperature_calib>; @@ -548,31 +549,31 @@ }; &timer_abcde { - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk"; }; &uart_AO { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; clock-names = "baud", "xtal", "pclk"; }; &uart_A { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; clock-names = "baud", "xtal", "pclk"; }; &uart_B { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; clock-names = "baud", "xtal", "pclk"; }; &uart_C { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; clock-names = "baud", "xtal", "pclk"; }; diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index bed1dfef1985..163a200d5a7b 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -377,7 +377,7 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>; + clocks = <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1"; }; diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts index 6e39ad52e42d..33037ef62d0a 100644 --- a/arch/arm/boot/dts/meson8b-mxq.dts +++ b/arch/arm/boot/dts/meson8b-mxq.dts @@ -165,7 +165,7 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>; + clocks = <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1"; }; diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index a24eccc354b9..a2a47804fc4a 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -340,7 +340,7 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>; + clocks = <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1"; }; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 099bf8e711c9..1934666ff60f 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -434,6 +434,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -508,8 +510,7 @@ &saradc { compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; - clocks = <&clkc CLKID_XTAL>, - <&clkc CLKID_SAR_ADC>; + clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; amlogic,hhi-sysctrl = <&hhi>; nvmem-cells = <&temperature_calib>; @@ -523,31 +524,31 @@ }; &timer_abcde { - clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk"; }; &uart_AO { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; clock-names = "baud", "xtal", "pclk"; }; &uart_A { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; clock-names = "baud", "xtal", "pclk"; }; &uart_B { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; clock-names = "baud", "xtal", "pclk"; }; &uart_C { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; + clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; clock-names = "baud", "xtal", "pclk"; };