From patchwork Sun Oct 27 16:23:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214241 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50E571515 for ; Sun, 27 Oct 2019 16:24:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2E25821D80 for ; Sun, 27 Oct 2019 16:24:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="pCgUOiR/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727436AbfJ0QXp (ORCPT ); Sun, 27 Oct 2019 12:23:45 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:43824 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727024AbfJ0QXn (ORCPT ); Sun, 27 Oct 2019 12:23:43 -0400 Received: by mail-wr1-f66.google.com with SMTP id c2so7362610wrr.10; Sun, 27 Oct 2019 09:23:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GWbTlN2rWt2ied7AfeNCro8kNhdCw9BqWl6E/dShDHM=; b=pCgUOiR/1l5Uat1i9ODdivZgGrUR8Pa1WmVT+96e3Io7y6zNE8LiPpSLbneTIFPDpS RhL1RIlEFtXXqBNKZlHkkUOgflEhYPq2hMiZp+ko8yo5lADiImaWyuWsECR3uT6UDOhi tmPjdhrI3bX+bNcTc+oRxSCqEb45PFWrXjBu7TpDXbBarGEudlmDdfx2eLIlOUOcTNaA 5NyA49hZ35RznaDd7fBTq2Y5Hmu2+oM8iIrc2NUO7VOzXrpq1bRx9b3aY60rW7mDSg+f ltmja1byUvCyRGdFdiBdixcM070kcvyClAfl/BkQyLcOWpm0voT5BOXIXtXLPvwzODmz Ed5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GWbTlN2rWt2ied7AfeNCro8kNhdCw9BqWl6E/dShDHM=; b=L9yxu5Obtnr3eNx+PMsDRxwaz3qqBO76HSX3fZRozrh9FYWoamGV+d8uB8r88vCBRy lUwWmwRucQ0go3BaFzZhi33DP3J8qFv6/R/AJlAFTPDyGMLh4iCwuB4D4Orhe9+JKkTJ t9nlitfPdtPQlqFTfuyRtd+ZHVauWinOW85685aCUuTWwrU5bCpZ7dEy7pFJRxi9XCYO qqcISSmr5gjDR9mE4IGVkd5nU3N/OZbuZMJ8kOfegaAWG2rP23i/r4oSo27LyGd81TIG VqzDDSidL5/n2KU+GZgKJZdf5NNtkKu2OOQKZM5NKYq47a/1XOTLYE1FnOYzzXS1ZyMQ pi8w== X-Gm-Message-State: APjAAAXpcDffoX7cJiUGQtoEyRO6ZiHKF3ppuLx87xefEswUXqIkFNWt HILNZ05dm/wjk0r5jRnRXoU= X-Google-Smtp-Source: APXvYqwiHWUOdqyOryfoxyoMSXW3biIYINgbbr5FI/oRW27dSCoa7yemhpwRw0z73LhgcDRjGmNbMg== X-Received: by 2002:adf:e403:: with SMTP id g3mr11120841wrm.128.1572193421194; Sun, 27 Oct 2019 09:23:41 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id 1sm8243299wrr.16.2019.10.27.09.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:23:40 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl , Rob Herring Subject: [PATCH v2 1/5] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Date: Sun, 27 Oct 2019 17:23:24 +0100 Message-Id: <20191027162328.1177402-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> References: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in the MMCBUS registers. There is no public documentation on this, but the GPL u-boot sources from the Amlogic BSP show that: - it uses the same XTAL input as the main clock controller - it contains a PLL which seems to be implemented just like the other PLLs in this SoC - there is a power-of-two PLL post-divider Add the documentation and header file for this DDR clock controller. Reviewed-by: Rob Herring Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd --- .../clock/amlogic,meson8-ddr-clkc.yaml | 50 +++++++++++++++++++ include/dt-bindings/clock/meson8-ddr-clkc.h | 4 ++ 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml new file mode 100644 index 000000000000..4b8669f870ec --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic DDR Clock Controller Device Tree Bindings + +maintainers: + - Martin Blumenstingl + +properties: + compatible: + enum: + - amlogic,meson8-ddr-clkc + - amlogic,meson8b-ddr-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/meson8-ddr-clkc.h b/include/dt-bindings/clock/meson8-ddr-clkc.h new file mode 100644 index 000000000000..a8e0fa2987ab --- /dev/null +++ b/include/dt-bindings/clock/meson8-ddr-clkc.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#define DDR_CLKID_DDR_PLL_DCO 0 +#define DDR_CLKID_DDR_PLL 1 From patchwork Sun Oct 27 16:23:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214239 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 42A411515 for ; Sun, 27 Oct 2019 16:24:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 164C1222BD for ; Sun, 27 Oct 2019 16:24:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="p3DvkN8/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727484AbfJ0QXp (ORCPT ); Sun, 27 Oct 2019 12:23:45 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:52629 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727008AbfJ0QXp (ORCPT ); Sun, 27 Oct 2019 12:23:45 -0400 Received: by mail-wm1-f67.google.com with SMTP id p21so6974126wmg.2; Sun, 27 Oct 2019 09:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4cl+dZXejhJavAZN1eT4Wu2Q0Fzk13sYf46Kt3kWw1M=; b=p3DvkN8/1iD2167WDvhYafeKuPYVe8tz5S5epRfeTq7ZkNCsNpq3Uluhz9iWCKLZWL xOuAmlHbPQ9ca6CbhKmNtQQdBB/2cUyockUCxM6wHuIDeliPevzT1GyHSP2wTVlV83/U GdihgLOW9/jaijDXyfEhTzcGnl1z/pdWJRb+lpWkJerRO251V5UImm4ocvKGKxfbSNTQ T/Mch0I4e5xxvXxrpmP3r/T6VaoEkPvSTAB662IW56HnxruXREahzoat83t7vY2CCykr wDuuwdpoep8sjYMG4HPzIM4vNbrxe3LgDYKMHhlufqBePVGu9biyszKlHPo4RgZAeMUi EbVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4cl+dZXejhJavAZN1eT4Wu2Q0Fzk13sYf46Kt3kWw1M=; b=DF8mlaYhx1ubL7EU1yfD7sP13YnhnJVHrxpf9ccc2aQM/Su7PyM/7VgMZOpbl2iVQq z1skuRNBLYInDeoIqo9I0wOwIlbyFmF687w9it79PEYSKQXSCM/Lzu1q6+P98TSI+qlE yg/aF2m3WCaK5ylSGY777oaUJd+DWBemdvqG+Z/xMkkt1HDAc/Wwoh1snJOhf5fXSc6L C38TkPffW98F0zhhpuuwzOGPVWY75zmwtQdMnptYYbl1wGqEAlLyhZ6paagszoC/uWqM nvAfYpDU3M9V8EBMvYic/raJa+dB5T4OdZyntxTM7hwmqnMMBPeAOY7dlINeyKfkxb6z +yuQ== X-Gm-Message-State: APjAAAV4o/jQWdF8zBTIVT0SOjj2ybWmGu4L4Ie7+fkAde0vEcRJduUr JxdxjUtBKMXYeopNrkC7GdA= X-Google-Smtp-Source: APXvYqzn7vhKxUlQfVQclnPfIeVnHDCiOk+8gFADXx8hFYhf6KlRq5h69nc3R06XV+FQ+vJ0y3LdLA== X-Received: by 2002:a7b:cb43:: with SMTP id v3mr2544710wmj.137.1572193422463; Sun, 27 Oct 2019 09:23:42 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id 1sm8243299wrr.16.2019.10.27.09.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:23:41 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 2/5] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller Date: Sun, 27 Oct 2019 17:23:25 +0100 Message-Id: <20191027162328.1177402-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> References: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the MMCBUS registers. There is no public documentation, but the u-boot GPL sources from the Amlogic BSP show that the DDR clock controller is identical on all three SoCs: #define CFG_DDR_CLK 792 #define CFG_PLL_M (((CFG_DDR_CLK/12)*12)/24) #define CFG_PLL_N 1 #define CFG_PLL_OD 1 // from set_ddr_clock: t_ddr_pll_cntl= (CFG_PLL_OD << 16)|(CFG_PLL_N<<9)|(CFG_PLL_M<<0) writel(timing_reg->t_ddr_pll_cntl|(1<<29),AM_DDR_PLL_CNTL); writel(readl(AM_DDR_PLL_CNTL) & (~(1<<29)),AM_DDR_PLL_CNTL); // from hx_ddr_power_down_enter: shut down DDR PLL writel(readl(AM_DDR_PLL_CNTL)|(1<<30),AM_DDR_PLL_CNTL); do { ... } while((readl(AM_DDR_PLL_CNTL)&(1<<31))==0) This translates to: - AM_DDR_PLL_CNTL[29] is the reset bit - AM_DDR_PLL_CNTL[30] is the enable bit - AM_DDR_PLL_CNTL[31] is the lock bit - AM_DDR_PLL_CNTL[8:0] is the m value (assuming the width is 9 bits based on the start of the n value) - AM_DDR_PLL_CNTL[13:9] is the n value (assuming the width is 5 bits based on the start of the od) - AM_DDR_PLL_CNTL[17:16] is the od (assuming the width is 2 bits based on other PLLs on this SoC) Add a driver for this PLL setup because it's used as one of the inputs of the audio clocks. There may be more clocks inside that clock controller - those can be added in subsequent patches. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/meson8-ddr.c | 152 +++++++++++++++++++++++++++++++++ 2 files changed, 153 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/meson8-ddr.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 3939f218587a..6eca2a406ee3 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -18,4 +18,4 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o -obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o +obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c new file mode 100644 index 000000000000..4aefcc5bdaae --- /dev/null +++ b/drivers/clk/meson/meson8-ddr.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Amlogic Meson8 DDR clock controller + * + * Copyright (C) 2019 Martin Blumenstingl + */ + +#include + +#include +#include +#include + +#include "clk-regmap.h" +#include "clk-pll.h" + +#define AM_DDR_PLL_CNTL 0x00 +#define AM_DDR_PLL_CNTL1 0x04 +#define AM_DDR_PLL_CNTL2 0x08 +#define AM_DDR_PLL_CNTL3 0x0c +#define AM_DDR_PLL_CNTL4 0x10 +#define AM_DDR_PLL_STS 0x14 +#define DDR_CLK_CNTL 0x18 +#define DDR_CLK_STS 0x1c + +static struct clk_regmap meson8_ddr_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 30, + .width = 1, + }, + .m = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .l = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 29, + .width = 1, + }, + }, + .hw.init = &(struct clk_init_data){ + .name = "ddr_pll_dco", + .ops = &meson_clk_pll_ro_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap meson8_ddr_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = AM_DDR_PLL_CNTL, + .shift = 16, + .width = 2, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "ddr_pll", + .ops = &clk_regmap_divider_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &meson8_ddr_pll_dco.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = { + .hws = { + [DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw, + [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw, + }, + .num = 2, +}; + +static struct clk_regmap *const meson8_ddr_clk_regmaps[] = { + &meson8_ddr_pll_dco, + &meson8_ddr_pll, +}; + +static const struct regmap_config meson8_ddr_clkc_regmap_config = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = DDR_CLK_STS, +}; + +static int meson8_ddr_clkc_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + struct resource *res; + void __iomem *base; + struct clk_hw *hw; + int ret, i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, + &meson8_ddr_clkc_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Populate regmap */ + for (i = 0; i < ARRAY_SIZE(meson8_ddr_clk_regmaps); i++) + meson8_ddr_clk_regmaps[i]->map = regmap; + + /* Register all clks */ + for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) { + hw = meson8_ddr_clk_hw_onecell_data.hws[i]; + + ret = devm_clk_hw_register(&pdev->dev, hw); + if (ret) { + dev_err(&pdev->dev, "Clock registration failed\n"); + return ret; + } + } + + return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + &meson8_ddr_clk_hw_onecell_data); +} + +static const struct of_device_id meson8_ddr_clkc_match_table[] = { + { .compatible = "amlogic,meson8-ddr-clkc" }, + { .compatible = "amlogic,meson8b-ddr-clkc" }, + { /* sentinel */ }, +}; + +static struct platform_driver meson8_ddr_clkc_driver = { + .probe = meson8_ddr_clkc_probe, + .driver = { + .name = "meson8-ddr-clkc", + .of_match_table = meson8_ddr_clkc_match_table, + }, +}; + +builtin_platform_driver(meson8_ddr_clkc_driver); From patchwork Sun Oct 27 16:23:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214231 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 785A2913 for ; Sun, 27 Oct 2019 16:23:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 568C6214AF for ; Sun, 27 Oct 2019 16:23:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="AoVinyap" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727764AbfJ0QXs (ORCPT ); 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[2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id 1sm8243299wrr.16.2019.10.27.09.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:23:43 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 3/5] clk: meson: meson8b: use of_clk_hw_register to register the clocks Date: Sun, 27 Oct 2019 17:23:26 +0100 Message-Id: <20191027162328.1177402-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> References: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Switch from clk_hw_register to of_clk_hw_register so we can use clk_parent_data.fw_name. This will be used to get the "xtal", "ddr_pll" and possibly others from the .dtb. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd --- drivers/clk/meson/meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 70ac6755607e..306b809deb49 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3696,7 +3696,7 @@ static void __init meson8b_clkc_init_common(struct device_node *np, if (!clk_hw_onecell_data->hws[i]) continue; - ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]); + ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]); if (ret) return; } From patchwork Sun Oct 27 16:23:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214235 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9A7C112C for ; Sun, 27 Oct 2019 16:24:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B7C18222BD for ; Sun, 27 Oct 2019 16:24:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="DJKRsi+4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727762AbfJ0QXr (ORCPT ); Sun, 27 Oct 2019 12:23:47 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:46882 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727466AbfJ0QXr (ORCPT ); Sun, 27 Oct 2019 12:23:47 -0400 Received: by mail-wr1-f66.google.com with SMTP id n15so7342780wrw.13; Sun, 27 Oct 2019 09:23:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FR91Xkho7A58iCTl5ApNx6Gn9blyxo7jlHkr4Z2ufbE=; b=DJKRsi+4xUNfRqEYSANnCE2BCk4qocBMxIHxvNaFwMv+6reNOJ1yDYZzxawhOVKc+u uTJs8mvzJAJRnXdV3PBCK7J+OLejIm0UExJaXQogyWv2+BgWDBWfXTg3kZpu0Jmdk7lG /TyFplsRJQ2IpcuqsNqJKTxyHc9uJ2l/2CiD1tpl4bJ5csKhETxra1ZBvxjQGJGCtawL yOxoKoQ/Qczup8O23yRK//AG/vdy4hLOGN68aA6tPyya/7qZ+H27V1gYV5prUio4nJDb IQWqqg+8jrprGeXqbfvnrir+EWjX38frqDR51u3xD1yBKGVj/PN1HyM3z5ncT5s0Ameu /Thw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FR91Xkho7A58iCTl5ApNx6Gn9blyxo7jlHkr4Z2ufbE=; b=hbwJ+zhCBWfzHfTFCFqeZCWau3+GTI4AlMdHlQpr4SfofLM170L51LxQsaTS2dODRQ hD/lC7EcESXCJuO01CC5FzgQitUjpRBsmDH8HzUxoTA6sXASJLSs71Z8z6V3xd7ByuXr j/gO2t9rr1lNO1iMyl3DozO1mDyDVqzlhGTwPesA/2PyloEgCX/UrCQHd8lrCBzFzocX Xi/VHuYPijIgR0+HNbtyLf3EbU1ahzAUD7KtNZqwb3UD0Eb4TWm8s64k2Y3qTHrIPWCY fuPlCpZmLP/Gwn6S4pvdUyJ5wetxkBk+ydQXks8V1inGIiMnnxfZ3ts9+jzWYOdZVOGH TW+A== X-Gm-Message-State: APjAAAW4k76Du7kxP0oINBUTcIq/8zypjg1atTSA+4GQiV/9aSZybbKW qhjZh/bZBKcE4nF2zunCAYE= X-Google-Smtp-Source: APXvYqwYcUCsvwTfCVC8G8QhpTTpc/gHzJpzRKp5RQnLVauGHvqBTZj2iIoo9YjsXmaCQ/Mnq8Vf2g== X-Received: by 2002:a5d:640e:: with SMTP id z14mr11475473wru.311.1572193425067; Sun, 27 Oct 2019 09:23:45 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id 1sm8243299wrr.16.2019.10.27.09.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:23:44 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 4/5] ARM: dts: meson8: add the DDR clock controller Date: Sun, 27 Oct 2019 17:23:27 +0100 Message-Id: <20191027162328.1177402-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> References: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main (HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the inputs for the audio clock muxes. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 4f59a4c8f036..257c1364864c 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -3,6 +3,7 @@ * Copyright 2014 Carlo Caione */ +#include #include #include #include @@ -195,6 +196,14 @@ #size-cells = <1>; ranges = <0x0 0xc8000000 0x8000>; + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + dmcbus: bus@6000 { compatible = "simple-bus"; reg = <0x6000 0x400>; @@ -455,8 +464,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; - clocks = <&xtal>; - clock-names = "xtal"; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; #clock-cells = <1>; #reset-cells = <1>; }; From patchwork Sun Oct 27 16:23:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214233 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C27E112C for ; Sun, 27 Oct 2019 16:23:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 798C7222C4 for ; Sun, 27 Oct 2019 16:23:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="jcOMNoQZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727774AbfJ0QXt (ORCPT ); Sun, 27 Oct 2019 12:23:49 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:38276 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727008AbfJ0QXt (ORCPT ); Sun, 27 Oct 2019 12:23:49 -0400 Received: by mail-wr1-f66.google.com with SMTP id v9so7381734wrq.5; Sun, 27 Oct 2019 09:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ryY1C6V/Fnndw45BEkZbgWqU1CO6K4z5Y17d3HMNBz4=; b=jcOMNoQZGE9P0d7ffCbmKdcF2AySd4aXs7mnjS66WOxzthrRtgWPSkR4yREp3Dhjus b2F3R9ITtpURe2IPC5wwadQlQyvuKJrFrk3yBzUZ1+/l6WiYQ2uV76nVGWuFrBkvPtXU ur8ioS5ptyCrLH6LXPMyoI6NmrqHQvEWML9l5VQcjGN/r9vBImUZVVq01cN5dsvE5BeT 2A+wXJje9nr3TzcAhZjfbBwmlClZ7Qe4krqF06Ux+refnB98YpCI95RGgdkm2nog97M7 K881kAGJNyLP9Ataz2iPfbnCepVvnGOEMDtyMNOe3PxBcE+q4iMFVzjSQe4wkxrQ/y7o 0lKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ryY1C6V/Fnndw45BEkZbgWqU1CO6K4z5Y17d3HMNBz4=; b=sqroOMyJxLva5YXyo/bgys3J9RWt1/5HFzZnvX5GrdCFqFOkxVj3ITvOPOe07eUbGu k9ehvSotZGcrJ3/vigzDW2DeM+F9UzwOTGdFOOcDinBQ0sWj+CfowFrgAma8YYAnkG/5 qe4PQ2VmGPRt4T2BUNIsraA/WauG0ubhvR5hcSn7RjkmEuoLK3QObvWtejGjfI8vgf/W GcnLgeKIKEfLdysS71qtmON+GJ0w7J3Kgn3WDb9q7m/LJ5FeIS28EEClqTGuRLJTs0ge wlN91/Yv4+5ZFhbX7tZ/U1q/GzIC3Uu9eui/m33dYgNIUn+hJRnziZAlO7zKkQHjvh/w iMJw== X-Gm-Message-State: APjAAAWiG5XHnWM3NnG+D6ygPf9DkHpoEA3SFMViP0kBvmnYVpd+GZsD 8c6CI/0xvm0OQPT8G5dg/L0= X-Google-Smtp-Source: APXvYqzJzVDuGRmFzkWeOr3NTHwTi62Xi6QJDu+uSXbftVSyV4pNzDeuETaGgy0zSi4H/2tKNFxJFg== X-Received: by 2002:a5d:5609:: with SMTP id l9mr11506053wrv.113.1572193426246; Sun, 27 Oct 2019 09:23:46 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id 1sm8243299wrr.16.2019.10.27.09.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:23:45 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 5/5] ARM: dts: meson8b: add the DDR clock controller Date: Sun, 27 Oct 2019 17:23:28 +0100 Message-Id: <20191027162328.1177402-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> References: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main (HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the inputs for the audio clock muxes. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8b.dtsi | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 1934666ff60f..8ac8bdfaf58f 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -4,6 +4,7 @@ * Author: Carlo Caione */ +#include #include #include #include @@ -172,6 +173,14 @@ #size-cells = <1>; ranges = <0x0 0xc8000000 0x8000>; + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8b-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + dmcbus: bus@6000 { compatible = "simple-bus"; reg = <0x6000 0x400>; @@ -434,8 +443,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; - clocks = <&xtal>; - clock-names = "xtal"; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; #clock-cells = <1>; #reset-cells = <1>; };