From patchwork Sat Nov 2 17:56:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11224193 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE1E41390 for ; Sat, 2 Nov 2019 17:56:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D6F7B21726 for ; Sat, 2 Nov 2019 17:56:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D6F7B21726 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 61A1C6E0C5; Sat, 2 Nov 2019 17:56:45 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by gabe.freedesktop.org (Postfix) with ESMTPS id F3C396E0C5; Sat, 2 Nov 2019 17:56:43 +0000 (UTC) Received: by mail-wr1-x442.google.com with SMTP id o28so12718150wro.7; Sat, 02 Nov 2019 10:56:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i7MoedW7dYIqdxbz/1+3cfjIQ5/QgAvq64b2nX4h9Is=; b=uhmCDcV0ZqKQU9lmIp8jlJx5TXRyK3iYsHnSxThAI91E2zXXrJjMs/tfX5kjSyP872 +bzldq58nTm6hIbI/zOzJwbPMnstgZirqPmeDv0zSgbes+CeThfglo/XTzPFXKcVE8L2 bQb2nYw3xgq3WWKGHZg2NbVSSEu7anCejpYOGQHeKXSuFHa3URtAjjoPpD4aZogmXXT0 KKoRHkU3hsqzIJSTfxa8vNrRW5SofYGJ0wADluaQ5tRlqaIFEfGIP6qRVrRJ90ovbRkh k050yLKTRvBjgeqIK08XilOEs8t0/5uKBDVfsm2Z7ZywKA8msehcsiagElpkAx/5nyez KczQ== X-Gm-Message-State: APjAAAXo2hnT2HIPYDULXGeDzC0rAKn69ZXpGp0KQ3zkUK3m3XRRIpXz iwGbQlDFczWAUkUizTtqjakuvLrG X-Google-Smtp-Source: APXvYqzJtlGVHlwL0v5kEn5rmK2IZ758Txlqib/YVhvasyLC3bmKjUtvK7n7igjNDNR9GVej52q1oA== X-Received: by 2002:adf:f452:: with SMTP id f18mr16970783wrp.264.1572717402606; Sat, 02 Nov 2019 10:56:42 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id d11sm13660495wrf.80.2019.11.02.10.56.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2019 10:56:41 -0700 (PDT) From: Thierry Reding To: Ben Skeggs , Joerg Roedel Subject: [PATCH v2 1/9] iommu: Document iommu_fwspec::flags field Date: Sat, 2 Nov 2019 18:56:29 +0100 Message-Id: <20191102175637.3065-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102175637.3065-1-thierry.reding@gmail.com> References: <20191102175637.3065-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i7MoedW7dYIqdxbz/1+3cfjIQ5/QgAvq64b2nX4h9Is=; b=PBk/3eobuNc6BJ0Ju4MArus3AqqUABkAqnOepK32TX0MsTxcMzsoHqlIVHBVEzvLCI 8SZ8ROh6sJtXTKpxO0B4M/eaLig2OEzfYpX0R9Z4OWKWTYhIHN4asp/qVhGzIl27Aq9h 0XOd0JTV4VwYJf1k8lhb52FNfPoZj1g7oMLRJ6BzK9o3j7z+DvTCDJinEk2P8moOchQq Jedsv5tlbwJynGGYR+ItUTyJEeWgyeoOBlGmQRWD2IkmHqtmiFnZc3xXcEeZgA3ZYqcz b4s9wUskjXOkMSg/XXpG+MY8Xa5auIMl+MSpOg8E8aRhmLEXTMb0wsA/hLx4QKPc2d8z 184Q== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, nouveau@lists.freedesktop.org, Ben Dooks , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding When this field was added in commit 5702ee24182f ("ACPI/IORT: Check ATS capability in root complex nodes"), the kerneldoc comment wasn't updated at the same time. Signed-off-by: Thierry Reding --- include/linux/iommu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index e28e80dea141..7bf038b371b8 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -570,6 +570,7 @@ struct iommu_group *fsl_mc_device_group(struct device *dev); * @ops: ops for this device's IOMMU * @iommu_fwnode: firmware handle for this device's IOMMU * @iommu_priv: IOMMU driver private data for this device + * @flags: IOMMU flags associated with this device * @num_ids: number of associated device IDs * @ids: IDs which this device may present to the IOMMU */ From patchwork Sat Nov 2 17:56:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11224195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 947A8112B for ; Sat, 2 Nov 2019 17:56:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D48021726 for ; Sat, 2 Nov 2019 17:56:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7D48021726 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C8B426E321; Sat, 2 Nov 2019 17:56:47 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by gabe.freedesktop.org (Postfix) with ESMTPS id 59B216E321; Sat, 2 Nov 2019 17:56:46 +0000 (UTC) Received: by mail-wm1-x344.google.com with SMTP id 11so12571220wmk.0; Sat, 02 Nov 2019 10:56:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B2PT8OgwUzPeHw6hJgNkyoN6vsJ1kDG8Ap5UUKvhze0=; b=H+hg+36TN9Jhyw0HFbzG7+ZTfqy6isEH/lBhi4k4OLmaBYCfvcU5a2SSzuNXE3OJ+A trCZ7KNFuxojo8LLWjhCzrza83sooXN+HQ0Zz2So00efroWaVg1yDj0a3d9as4l6xPe5 0bIJLOGL3dMAR3l8VRkQ58hfEIc6LRKSqDdL+qCwszaWcwc00Bjdyu33m3y7eA/zeqSx h4LNrLzA9NNefmT2Yb4Qs8ScUTWzUrekuu7DkVHa4zKqVVyY2NcmQiVNkc2u6TniFgYg tR6/7Olo5aumn2uge2M4sWl+ArvpoCQvDSj9zb1HhzjaStsLYvqQtPKedtn7c8Xg11iT X0Cg== X-Gm-Message-State: APjAAAVfGF2wcW31Ha/AQ1msdngBCZOVpHTdKJGI/HgcaQ23MLdevP0Z TbQzJ8PfezGaHrVsTCt6f5gCjWRz X-Google-Smtp-Source: APXvYqwh0vcSVJl/llQBGAobzeyZMsr7O0KniFZ1e9AEUl48sSDcCxY9VqTZMS3MRW5xlWyEDtHt4A== X-Received: by 2002:a05:600c:2295:: with SMTP id 21mr14933173wmf.85.1572717404745; Sat, 02 Nov 2019 10:56:44 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id t5sm673642wro.76.2019.11.02.10.56.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2019 10:56:43 -0700 (PDT) From: Thierry Reding To: Ben Skeggs , Joerg Roedel Subject: [PATCH v2 2/9] iommu: Add dummy dev_iommu_fwspec_get() helper Date: Sat, 2 Nov 2019 18:56:30 +0100 Message-Id: <20191102175637.3065-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102175637.3065-1-thierry.reding@gmail.com> References: <20191102175637.3065-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B2PT8OgwUzPeHw6hJgNkyoN6vsJ1kDG8Ap5UUKvhze0=; b=UoJ1t+XNs6ajs9GVONSz3qXRw34jZ58PHRGKTpcmzpZuD3Rldp27aTujMwoeMc636j 6eYYSls+GuGPc4z5GkVaQO3S6Uj+JAk1AJNbZM+TWhAk/SsBEScS4O2aTPto/521WH5j 25s3jNzMOxDZqwDquoQmQ7o9fgs8hKKS+unmnXs8R1E+5dACuL4NtIdc/0COAUc7Rjqq LnNZKJ08GAL1/1WZG7VIg5Qn81kVdFOBLfgx6IJp3cX4HP9ICsFdtjrlufZQ8KJZaOSX 6m5/eagAAZeFQEoHvsGgoUTWm289Fztk2pB7yQ0B0FZEYFg3jod1/YAb+ET6nm25SdMk /SzA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, nouveau@lists.freedesktop.org, Ben Dooks , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding This dummy implementation is useful to avoid a dependency on the IOMMU_API Kconfig symbol in drivers that can optionally use the IOMMU API. In order to fully use this, also move the struct iommu_fwspec definition out of the IOMMU_API protected region. Suggested-by: Ben Dooks Signed-off-by: Thierry Reding --- include/linux/iommu.h | 47 ++++++++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 7bf038b371b8..b092e73b2c86 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -190,6 +190,27 @@ struct iommu_sva_ops { iommu_mm_exit_handler_t mm_exit; }; +/** + * struct iommu_fwspec - per-device IOMMU instance data + * @ops: ops for this device's IOMMU + * @iommu_fwnode: firmware handle for this device's IOMMU + * @iommu_priv: IOMMU driver private data for this device + * @flags: IOMMU flags associated with this device + * @num_ids: number of associated device IDs + * @ids: IDs which this device may present to the IOMMU + */ +struct iommu_fwspec { + const struct iommu_ops *ops; + struct fwnode_handle *iommu_fwnode; + void *iommu_priv; + u32 flags; + unsigned int num_ids; + u32 ids[1]; +}; + +/* ATS is supported */ +#define IOMMU_FWSPEC_PCI_RC_ATS (1 << 0) + #ifdef CONFIG_IOMMU_API /** @@ -565,27 +586,6 @@ extern struct iommu_group *generic_device_group(struct device *dev); /* FSL-MC device grouping function */ struct iommu_group *fsl_mc_device_group(struct device *dev); -/** - * struct iommu_fwspec - per-device IOMMU instance data - * @ops: ops for this device's IOMMU - * @iommu_fwnode: firmware handle for this device's IOMMU - * @iommu_priv: IOMMU driver private data for this device - * @flags: IOMMU flags associated with this device - * @num_ids: number of associated device IDs - * @ids: IDs which this device may present to the IOMMU - */ -struct iommu_fwspec { - const struct iommu_ops *ops; - struct fwnode_handle *iommu_fwnode; - void *iommu_priv; - u32 flags; - unsigned int num_ids; - u32 ids[1]; -}; - -/* ATS is supported */ -#define IOMMU_FWSPEC_PCI_RC_ATS (1 << 0) - /** * struct iommu_sva - handle to a device-mm bond */ @@ -980,6 +980,11 @@ const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) return NULL; } +static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev) +{ + return NULL; +} + static inline bool iommu_dev_has_feature(struct device *dev, enum iommu_dev_features feat) { From patchwork Sat Nov 2 17:56:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11224197 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C551112B for ; Sat, 2 Nov 2019 17:56:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6538321726 for ; Sat, 2 Nov 2019 17:56:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6538321726 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 06C746E4DD; Sat, 2 Nov 2019 17:56:50 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by gabe.freedesktop.org (Postfix) with ESMTPS id 84D516E4DD; Sat, 2 Nov 2019 17:56:48 +0000 (UTC) Received: by mail-wm1-x342.google.com with SMTP id z19so7886852wmk.3; Sat, 02 Nov 2019 10:56:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ANfPpmnsT/oeTWNuA93BRI4tRFioqEyA5OCtqkzBRZ8=; b=qeT0qmZk6sbb+JlLu+1+QibZIpOrYMAQiveBO3Gtc9hAH/HCcoZmZPJpHssW1MvFGq dBXM9SxYs1lM4lYmfyW5yeCuCbGtdakDyTvu5ZGutR9R1QwKMDdHld3BRpgy6sHX0HKx UABX/QOT9YbohCzhnMyHx7p2M3H0Tm7cm5VBVzL9mSm/nXGp/dDlpg1za39NBboDYObz AbWD5j4fv0wfVQqpsm9TPgzQObea2b9G8ZmN6ya94kCSj8PxlEsdwxKmF3/1B5k/fLO5 XVf+KFeVZrV/VOTrOj/i8mSU6Mv3xzJLVqxIYpl12Kw+5c0rW7xqp5G4Bj3ftMR8p9NG 4fNg== X-Gm-Message-State: APjAAAUoPJUDoCu2Ir8iBo1oId8IRVA8lDD9wB/q6KwEc8e5UhdHB2kK +JjCLEHYA2J+z3tBocHaY3A= X-Google-Smtp-Source: APXvYqx9tdG3WA1HsVorLUlV0lcZZZ0mAl4cYePM67MnHlKZPh33QVcD9sYlhIq0QqLoi69/NETT4w== X-Received: by 2002:a1c:9a4f:: with SMTP id c76mr16062345wme.103.1572717406828; Sat, 02 Nov 2019 10:56:46 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id v10sm14574594wmg.48.2019.11.02.10.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2019 10:56:45 -0700 (PDT) From: Thierry Reding To: Ben Skeggs , Joerg Roedel Subject: [PATCH v2 3/9] drm/nouveau: fault: Add support for GP10B Date: Sat, 2 Nov 2019 18:56:31 +0100 Message-Id: <20191102175637.3065-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102175637.3065-1-thierry.reding@gmail.com> References: <20191102175637.3065-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ANfPpmnsT/oeTWNuA93BRI4tRFioqEyA5OCtqkzBRZ8=; b=UXbkDudP4dmji/zYAcLUXUjXdfcd7W8lG7HOEPZCRPQ/6upGd6Z4dRI0UqJ/eGYXSZ PLMxF18nEMIkCDF0isYInwxVgqRIYo/72TByzGmzBFSzQZCAdRgwTIryOPQIhNqOhr1h 1g9+Iw7wBTRe5OR191YmEP9h0M7sfvvZJR61fRTAg1D+EoAGZD9n4MlUxzP4yFXTUmQ3 It0P7xe765MhQnJJNkKaKrRYFKa0vwZ0/RF9ZqhC0Fvn8McebUWCECb+JRXOs+kFwX/6 9qjUeDtVJemHafAMcSnJ2n3EUH2Rgx05UHdjXsUd7Fi8GdyrZnIaPU5Sv5E69i5gbe7r Vf0w== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, nouveau@lists.freedesktop.org, Ben Dooks , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding There is no BAR2 on GP10B and there is no need to map through BAR2 because all memory is shared between the GPU and the CPU. Add a custom implementation of the fault sub-device that uses nvkm_memory_addr() instead of nvkm_memory_bar2() to return the address of a pinned fault buffer. Signed-off-by: Thierry Reding --- .../drm/nouveau/include/nvkm/subdev/fault.h | 1 + .../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/fault/Kbuild | 1 + .../gpu/drm/nouveau/nvkm/subdev/fault/base.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/fault/gp100.c | 17 ++++-- .../gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c | 53 +++++++++++++++++++ .../gpu/drm/nouveau/nvkm/subdev/fault/gv100.c | 1 + .../gpu/drm/nouveau/nvkm/subdev/fault/priv.h | 10 ++++ 8 files changed, 80 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h index 97322f95b3ee..a513c16ab105 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h @@ -31,6 +31,7 @@ struct nvkm_fault_data { }; int gp100_fault_new(struct nvkm_device *, int, struct nvkm_fault **); +int gp10b_fault_new(struct nvkm_device *, int, struct nvkm_fault **); int gv100_fault_new(struct nvkm_device *, int, struct nvkm_fault **); int tu102_fault_new(struct nvkm_device *, int, struct nvkm_fault **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index c3c7159f3411..b061df138142 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2375,7 +2375,7 @@ nv13b_chipset = { .name = "GP10B", .bar = gm20b_bar_new, .bus = gf100_bus_new, - .fault = gp100_fault_new, + .fault = gp10b_fault_new, .fb = gp10b_fb_new, .fuse = gm107_fuse_new, .ibus = gp10b_ibus_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild index 53b9d638f2c8..d65ec719f153 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild @@ -2,5 +2,6 @@ nvkm-y += nvkm/subdev/fault/base.o nvkm-y += nvkm/subdev/fault/user.o nvkm-y += nvkm/subdev/fault/gp100.o +nvkm-y += nvkm/subdev/fault/gp10b.o nvkm-y += nvkm/subdev/fault/gv100.o nvkm-y += nvkm/subdev/fault/tu102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c index ca251560d3e0..1c4b852b26c3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.c @@ -108,7 +108,7 @@ nvkm_fault_oneinit_buffer(struct nvkm_fault *fault, int id) return ret; /* Pin fault buffer in BAR2. */ - buffer->addr = nvkm_memory_bar2(buffer->mem); + buffer->addr = fault->func->buffer.pin(buffer); if (buffer->addr == ~0ULL) return -EFAULT; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c index 4f3c4e091117..f6b189cc4330 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.c @@ -21,25 +21,26 @@ */ #include "priv.h" +#include #include #include -static void +void gp100_fault_buffer_intr(struct nvkm_fault_buffer *buffer, bool enable) { struct nvkm_device *device = buffer->fault->subdev.device; nvkm_mc_intr_mask(device, NVKM_SUBDEV_FAULT, enable); } -static void +void gp100_fault_buffer_fini(struct nvkm_fault_buffer *buffer) { struct nvkm_device *device = buffer->fault->subdev.device; nvkm_mask(device, 0x002a70, 0x00000001, 0x00000000); } -static void +void gp100_fault_buffer_init(struct nvkm_fault_buffer *buffer) { struct nvkm_device *device = buffer->fault->subdev.device; @@ -48,7 +49,12 @@ gp100_fault_buffer_init(struct nvkm_fault_buffer *buffer) nvkm_mask(device, 0x002a70, 0x00000001, 0x00000001); } -static void +u64 gp100_fault_buffer_pin(struct nvkm_fault_buffer *buffer) +{ + return nvkm_memory_bar2(buffer->mem); +} + +void gp100_fault_buffer_info(struct nvkm_fault_buffer *buffer) { buffer->entries = nvkm_rd32(buffer->fault->subdev.device, 0x002a78); @@ -56,7 +62,7 @@ gp100_fault_buffer_info(struct nvkm_fault_buffer *buffer) buffer->put = 0x002a80; } -static void +void gp100_fault_intr(struct nvkm_fault *fault) { nvkm_event_send(&fault->event, 1, 0, NULL, 0); @@ -68,6 +74,7 @@ gp100_fault = { .buffer.nr = 1, .buffer.entry_size = 32, .buffer.info = gp100_fault_buffer_info, + .buffer.pin = gp100_fault_buffer_pin, .buffer.init = gp100_fault_buffer_init, .buffer.fini = gp100_fault_buffer_fini, .buffer.intr = gp100_fault_buffer_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c new file mode 100644 index 000000000000..9e66d1f7654d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2019 NVIDIA Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "priv.h" + +#include + +#include + +u64 +gp10b_fault_buffer_pin(struct nvkm_fault_buffer *buffer) +{ + return nvkm_memory_addr(buffer->mem); +} + +static const struct nvkm_fault_func +gp10b_fault = { + .intr = gp100_fault_intr, + .buffer.nr = 1, + .buffer.entry_size = 32, + .buffer.info = gp100_fault_buffer_info, + .buffer.pin = gp10b_fault_buffer_pin, + .buffer.init = gp100_fault_buffer_init, + .buffer.fini = gp100_fault_buffer_fini, + .buffer.intr = gp100_fault_buffer_intr, + .user = { { 0, 0, MAXWELL_FAULT_BUFFER_A }, 0 }, +}; + +int +gp10b_fault_new(struct nvkm_device *device, int index, + struct nvkm_fault **pfault) +{ + return nvkm_fault_new_(&gp10b_fault, device, index, pfault); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c index 6747f09c2dc3..2707be4ffabc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c @@ -214,6 +214,7 @@ gv100_fault = { .buffer.nr = 2, .buffer.entry_size = 32, .buffer.info = gv100_fault_buffer_info, + .buffer.pin = gp100_fault_buffer_pin, .buffer.init = gv100_fault_buffer_init, .buffer.fini = gv100_fault_buffer_fini, .buffer.intr = gv100_fault_buffer_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h index 975e66ac6344..f6f1dd7eee1f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/priv.h @@ -30,6 +30,7 @@ struct nvkm_fault_func { int nr; u32 entry_size; void (*info)(struct nvkm_fault_buffer *); + u64 (*pin)(struct nvkm_fault_buffer *); void (*init)(struct nvkm_fault_buffer *); void (*fini)(struct nvkm_fault_buffer *); void (*intr)(struct nvkm_fault_buffer *, bool enable); @@ -40,6 +41,15 @@ struct nvkm_fault_func { } user; }; +void gp100_fault_buffer_intr(struct nvkm_fault_buffer *, bool enable); +void gp100_fault_buffer_fini(struct nvkm_fault_buffer *); +void gp100_fault_buffer_init(struct nvkm_fault_buffer *); +u64 gp100_fault_buffer_pin(struct nvkm_fault_buffer *); +void gp100_fault_buffer_info(struct nvkm_fault_buffer *); +void gp100_fault_intr(struct nvkm_fault *); + +u64 gp10b_fault_buffer_pin(struct nvkm_fault_buffer *); + int gv100_fault_oneinit(struct nvkm_fault *); int nvkm_ufault_new(struct nvkm_device *, const struct nvkm_oclass *, From patchwork Sat Nov 2 17:56:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11224199 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96F211390 for ; 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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id t29sm23428383wrb.53.2019.11.02.10.56.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2019 10:56:47 -0700 (PDT) From: Thierry Reding To: Ben Skeggs , Joerg Roedel Subject: [PATCH v2 4/9] drm/nouveau: tegra: Do not try to disable PCI device Date: Sat, 2 Nov 2019 18:56:32 +0100 Message-Id: <20191102175637.3065-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102175637.3065-1-thierry.reding@gmail.com> References: <20191102175637.3065-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nFY1vqzSONgdwE5+azceCzycYUt1l/wUOCKvdJLbIwE=; b=tw+Jpba8055Bl8J2Hlie89ay0WxADSFMhaavglIxVwMeYCKa98EiG+IJGKD99CGMf8 MmdBt7wzXf7CCufbUnVkS7Cbp0BDpGuyca+to8s4g0lEZtpDUlOlYdKCC7JbKIB5KE1X LS7xWBahzkzEeP9ofB1SwNH0vI0e6trPz2AVeq/1zDoJZF1goHsbSdVjW1XS8f2sxLev zEE5jpuvrMBgqmoEBQC/y1HpGo4hlV1njKU6fNkTgH+K7MceB8WxjyzYHRCsP1QMRtdN tGhQ+oZciB0MKcL/zYQMsgn0xwUKwpZr5V2A4lcthRicFvIKR+wOTsixgsiq5F4lIt9r Z85A== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, nouveau@lists.freedesktop.org, Ben Dooks , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding When Nouveau is instantiated on top of a platform device, the dev->pdev field will be NULL and calling pci_disable_device() will crash. Move the PCI disabling code to the PCI specific driver removal code. Reviewed-by: Lyude Paul Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nouveau_drm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 2cd83849600f..b65ae817eabf 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -715,7 +715,6 @@ static int nouveau_drm_probe(struct pci_dev *pdev, void nouveau_drm_device_remove(struct drm_device *dev) { - struct pci_dev *pdev = dev->pdev; struct nouveau_drm *drm = nouveau_drm(dev); struct nvkm_client *client; struct nvkm_device *device; @@ -727,7 +726,6 @@ nouveau_drm_device_remove(struct drm_device *dev) device = nvkm_device_find(client->device); nouveau_drm_device_fini(dev); - pci_disable_device(pdev); drm_dev_put(dev); nvkm_device_del(&device); } @@ -738,6 +736,7 @@ nouveau_drm_remove(struct pci_dev *pdev) struct drm_device *dev = pci_get_drvdata(pdev); nouveau_drm_device_remove(dev); + pci_disable_device(pdev); } static int From patchwork Sat Nov 2 17:56:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11224201 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4370F1390 for ; Sat, 2 Nov 2019 17:57:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2BFFC218AC for ; Sat, 2 Nov 2019 17:57:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2BFFC218AC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 649E86E4EC; Sat, 2 Nov 2019 17:56:55 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1C6376E4EC; Sat, 2 Nov 2019 17:56:53 +0000 (UTC) Received: by mail-wm1-x343.google.com with SMTP id m17so3275037wmi.5; Sat, 02 Nov 2019 10:56:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iPyrNYuh+D9sdc90p8MGbT53BzBTuJgc562Xscp47+M=; b=HRsHfYkIIJl1W2fu+VZ9twOupEGQt0Yo+EdUYvFlo0ExpPvX2cniR4FHCWD05h1p5l YNDZXkevmixIXTYWd/6jr0EoDuWSdDHo23wMCqgW0zEfMMC8zEDjjG1hkDdkTNN15yIN +BDYFpCv38Nhlmx4Q/VMvr2swCFRm1K2vT0cWbgCAsxUMZMvXEm/XHq9mGAC1yI0Wtmy wbqESGxJ9YAQMCrG2lKcY7nO8ZUW3htxWh1du51jb3LsVM1/Mx2dIw9q/XEpcfTaokxl lkvBcszChijp4jMSDSbSqjhyEq99pAR4Wv+NLsBOEcX4N/NiXjPzQDCBuqeQslcP09TO Ue+Q== X-Gm-Message-State: APjAAAURzLFrBzsfeVJ3i4jUt5NGqgAYg+K3sZRQ82YFfI+mn+baRsGA OE9bhnDBGmzRK0uFmdTkSuI= X-Google-Smtp-Source: APXvYqyS7+gBjnA3J0Ipl+n3F4+f2+CSBvOI/VkWKB6mZCfhDy76c/tr0ezPCPCD4eQtO1Cds5+7Rw== X-Received: by 2002:a1c:7f54:: with SMTP id a81mr16105671wmd.48.1572717411603; Sat, 02 Nov 2019 10:56:51 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id u1sm8614139wrp.56.2019.11.02.10.56.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2019 10:56:50 -0700 (PDT) From: Thierry Reding To: Ben Skeggs , Joerg Roedel Subject: [PATCH v2 5/9] drm/nouveau: tegra: Avoid pulsing reset twice Date: Sat, 2 Nov 2019 18:56:33 +0100 Message-Id: <20191102175637.3065-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102175637.3065-1-thierry.reding@gmail.com> References: <20191102175637.3065-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iPyrNYuh+D9sdc90p8MGbT53BzBTuJgc562Xscp47+M=; b=nP2SGINI4Ur/eHW/lspNtR35xdwGU7jvbgoMCmGYHbG8Pf1PrfIk9Y0NDM6F85H7Fv sZZZ0s/ojJj4ZbV79PnHQHspwJMQ5Ee7/HWruEjifAUdh3OxVaoedI4loPy+m8uYUlBz 49Sv69d5FDwE2LGgjDSqAW+UoahBppg/LHNrovn3wVJiNIhtvSnFF4RVqoM2apOP/l6y WYRJMLzsx8B52UTxPys49YFNpglgtIW6Du0D+zAD4akodfQ7iy6W9r8v+zfyMyMcHBWL Co++vpyUFGjVUAwiSzCRM6ETL1ub638Wz//133ii8rWFxsJp3nZnYqlqwhAzqJrbwONB vpHw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, nouveau@lists.freedesktop.org, Ben Dooks , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding When the GPU powergate is controlled by a generic power domain provider, the reset will automatically be asserted and deasserted as part of the power-ungating procedure. On some Jetson TX2 boards, doing an additional assert and deassert of the GPU outside of the power-ungate procedure can cause the GPU to go into a bad state where the memory interface can no longer access system memory. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index 0e372a190d3f..747a775121cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c @@ -52,18 +52,18 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev) clk_set_rate(tdev->clk_pwr, 204000000); udelay(10); - reset_control_assert(tdev->rst); - udelay(10); - if (!tdev->pdev->dev.pm_domain) { + reset_control_assert(tdev->rst); + udelay(10); + ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); if (ret) goto err_clamp; udelay(10); - } - reset_control_deassert(tdev->rst); - udelay(10); + reset_control_deassert(tdev->rst); + udelay(10); + } return 0; From patchwork Sat Nov 2 17:56:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11224203 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 25E46112B for ; Sat, 2 Nov 2019 17:57:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0ED8B21726 for ; Sat, 2 Nov 2019 17:57:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0ED8B21726 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC73E6E50C; Sat, 2 Nov 2019 17:56:58 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7ECE66E4F4; Sat, 2 Nov 2019 17:56:55 +0000 (UTC) Received: by mail-wr1-x441.google.com with SMTP id o28so12718461wro.7; Sat, 02 Nov 2019 10:56:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n1tTzvYM5w9+u5hVDlIZGuSZUZEgZbCTm+ltdJcT/B4=; b=HCZqsNT4y4kwYnUGR1VhbSiWM/i1SCs0sqsKv2+6CpUIBn6PHJIBk8SVroBVmo2E62 hRzAmsTOmlYzq8UCgPuaANd5m81txcqgAoebxfX9Q7YrR+1PPQY8z0CAjU1CFiMiga/9 wJpnvOp0f/XqWx8UfoAgb3fykaO/s9EKWWfBTxzMhDWKJ6e2fKvB1fvb92NJdHDRUy5r 6YVgywzmiBrxrOF6XHZhrchGAwluIYrzPhJvr4q5IE1eAdF6KgO2Hgto1Wjz8SVSX6LJ ukbI3Ef9FP0Wdu7k7ggE4GWR5INjaJjUu3a4tpZbRILno3ALFBM50ACf+l2qmQHeHrLs VsNg== X-Gm-Message-State: APjAAAXpoSaPJG5PsvUyq0kODyYV0YlXhahfbFXmwipGFX777uAJECjN TpyWy5lrNjUmRfCeSIaRRqkXHkVe X-Google-Smtp-Source: APXvYqwbnnYZXrTkrBOfrjQ8/OumIiqq2aGuleKDeqHVq/H+Li2Ivc5XBEpeNlbKG3RfHNpeD83iPA== X-Received: by 2002:a5d:4612:: with SMTP id t18mr15317254wrq.255.1572717414013; Sat, 02 Nov 2019 10:56:54 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id f13sm10800339wrq.96.2019.11.02.10.56.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2019 10:56:52 -0700 (PDT) From: Thierry Reding To: Ben Skeggs , Joerg Roedel Subject: [PATCH v2 6/9] drm/nouveau: tegra: Set clock rate if not set Date: Sat, 2 Nov 2019 18:56:34 +0100 Message-Id: <20191102175637.3065-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102175637.3065-1-thierry.reding@gmail.com> References: <20191102175637.3065-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n1tTzvYM5w9+u5hVDlIZGuSZUZEgZbCTm+ltdJcT/B4=; b=Ez9eNqz/Ef4W+g9pbhwhmvBdXpT7gFPFmbgzwdZhMJ7WrkBziKZDOmzPtdKCI9Rewx j9zCBqE17D73D3xYZtyK9viD4VvW06H6nyqCEvDOM02OdtjuADd8Hr8Vn2mdamZwUkVK XmMej0sSChRRHMjAlTIjGXhHyuK3WiCvOyIbjrJB8j93m6r0ikiISpd1MrWAgytgaBMQ BmRt0oDiRbXYhi08tyPE+glhQRK+TyoRSCqyCpm8WC5utejvQYk+OTtla69byetV3Vkb KSkQ7jZRGNWPTFdH6cyCs/CAQV38NLV0E0lYd7CIAyAF0q9ZPUVNlkFRjSsGJz6apEfl lCzA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, nouveau@lists.freedesktop.org, Ben Dooks , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding If the GPU clock has not had a rate set, initialize it to the maximum clock rate to make sure it does run. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index 747a775121cf..d0d52c1d4aee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c @@ -279,6 +279,7 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func, struct nvkm_device **pdevice) { struct nvkm_device_tegra *tdev; + unsigned long rate; int ret; if (!(tdev = kzalloc(sizeof(*tdev), GFP_KERNEL))) @@ -307,6 +308,17 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func, goto free; } + rate = clk_get_rate(tdev->clk); + if (rate == 0) { + ret = clk_set_rate(tdev->clk, ULONG_MAX); + if (ret < 0) + goto free; + + rate = clk_get_rate(tdev->clk); + + dev_dbg(&pdev->dev, "GPU clock set to %lu\n", rate); + } + if (func->require_ref_clk) tdev->clk_ref = devm_clk_get(&pdev->dev, "ref"); if (IS_ERR(tdev->clk_ref)) { From patchwork Sat Nov 2 17:56:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11224205 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C01571390 for ; Sat, 2 Nov 2019 17:57:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A867C21726 for ; Sat, 2 Nov 2019 17:57:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A867C21726 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A777C6E50D; Sat, 2 Nov 2019 17:57:00 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by gabe.freedesktop.org (Postfix) with ESMTPS id B97A86E4F9; Sat, 2 Nov 2019 17:56:57 +0000 (UTC) Received: by mail-wr1-x441.google.com with SMTP id v9so12747803wrq.5; Sat, 02 Nov 2019 10:56:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TBGvky0NnQZeg63n6Ic4zjBFtsUUkKVRowQY0EPm9HY=; b=OLvPSXjcms12XnA9niFWekrRrcbvaPTy2x6PRQw08mvnAMe/d0sz7ykySNI0N77nxx m8Ts7xpTFJMha2IdPa2v98Uh++CABsBMeaWVoMh4KYxKnOUFepEYb2mjtv9bXAnI2k/6 3lv8iUPnpq3c6pZOvgHbUgLrtvwrBKCisNM1kSwwgJ35QI5/LJLuTaAc653RNYzj1z0n KzzXSy29clYdpBZI2zDvKr7wRJeXXYxD48MweCvDrcuDGw0IhXG/R+kqfgtSPoSW1QIa uC3zytCYW1QMwTPHYWx3iryTP+mg1uf3+Z5+0MH1AhZIAnNSXQNsf8JkJjOIRkEO7NNi ibYg== X-Gm-Message-State: APjAAAV5M/H4C+PipTUz3jBKTTfvrASvdSSa9gUBHoDJjL6ARulTLKRK 5ggERX79T7B6H+9uFvytTGE= X-Google-Smtp-Source: APXvYqxOLNjP/3DBg4V3uwz9iz5CjZ1RkuM8IW/bvjgcCigsK2Vn74oR4RwbTRV5gqlOC9StRj92iw== X-Received: by 2002:adf:db0e:: with SMTP id s14mr16844240wri.341.1572717416157; Sat, 02 Nov 2019 10:56:56 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id h205sm12007213wmf.35.2019.11.02.10.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2019 10:56:55 -0700 (PDT) From: Thierry Reding To: Ben Skeggs , Joerg Roedel Subject: [PATCH v2 7/9] drm/nouveau: secboot: Read WPR configuration from GPU registers Date: Sat, 2 Nov 2019 18:56:35 +0100 Message-Id: <20191102175637.3065-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102175637.3065-1-thierry.reding@gmail.com> References: <20191102175637.3065-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TBGvky0NnQZeg63n6Ic4zjBFtsUUkKVRowQY0EPm9HY=; b=mQwCxE+ACwCNAtNNotlKs7E39ChGSwDghVPnTpzol2wQB3+C+YI2dsshyZcPxsJDSW H1pwDNSRmafPvupZjjltT/3xJ9EBJrHo+vIRkgHCBc0tOWJkzl026DS0cwtRyR24Pq8k 89IWShU/C7HWr+5rlTLVNSbqIkGbuJXOcojV47VPZs8iXQwWCd7FGsLPz9eiUjCLtVKc pUzIw8lJ9bsYj3W9ZLSe+sm3YX9IWzrBl4ghFLwN/+zhIqOKrnVjRkW+jwdkhw3LSdLy s0alr8g0PylVT0gmLDPryDhEaKnP9QLi0qNDxCGc26pp3aU+MAq6R4tG5KHpEFTrt1FS 70vw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, nouveau@lists.freedesktop.org, Ben Dooks , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding The GPUs found on Tegra SoCs have registers that can be used to read the WPR configuration. Use these registers instead of reaching into the memory controller's register space to read the same information. Signed-off-by: Thierry Reding --- .../drm/nouveau/nvkm/subdev/secboot/gm200.h | 2 +- .../drm/nouveau/nvkm/subdev/secboot/gm20b.c | 81 ++++++++++++------- .../drm/nouveau/nvkm/subdev/secboot/gp10b.c | 4 +- 3 files changed, 53 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h index 62c5e162099a..280b1448df88 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h @@ -41,6 +41,6 @@ int gm200_secboot_run_blob(struct nvkm_secboot *, struct nvkm_gpuobj *, struct nvkm_falcon *); /* Tegra-only */ -int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *, u32); +int gm20b_secboot_tegra_read_wpr(struct gm200_secboot *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c index df8b919dcf09..f8a543122219 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -23,39 +23,65 @@ #include "acr.h" #include "gm200.h" -#define TEGRA210_MC_BASE 0x70019000 - #ifdef CONFIG_ARCH_TEGRA -#define MC_SECURITY_CARVEOUT2_CFG0 0xc58 -#define MC_SECURITY_CARVEOUT2_BOM_0 0xc5c -#define MC_SECURITY_CARVEOUT2_BOM_HI_0 0xc60 -#define MC_SECURITY_CARVEOUT2_SIZE_128K 0xc64 -#define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED (1 << 1) /** * gm20b_secboot_tegra_read_wpr() - read the WPR registers on Tegra * - * On dGPU, we can manage the WPR region ourselves, but on Tegra the WPR region - * is reserved from system memory by the bootloader and irreversibly locked. - * This function reads the address and size of the pre-configured WPR region. + * On dGPU, we can manage the WPR region ourselves, but on Tegra this region + * is allocated from system memory by the secure firmware. The region is then + * marked as a "secure carveout" and irreversibly locked. Furthermore, the WPR + * secure carveout is also configured to be sent to the GPU via a dedicated + * serial bus between the memory controller and the GPU. The GPU requests this + * information upon leaving reset and exposes it through a FIFO register at + * offset 0x100cd4. + * + * The FIFO register's lower 4 bits can be used to set the read index into the + * FIFO. After each read of the FIFO register, the read index is incremented. + * + * Indices 2 and 3 contain the lower and upper addresses of the WPR. These are + * stored in units of 256 B. The WPR is inclusive of both addresses. + * + * Unfortunately, for some reason the WPR info register doesn't contain the + * correct values for the secure carveout. It seems like the upper address is + * always too small by 128 KiB - 1. Given that the secure carvout size in the + * memory controller configuration is specified in units of 128 KiB, it's + * possible that the computation of the upper address of the WPR is wrong and + * causes this difference. */ int -gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base) +gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb) { + struct nvkm_device *device = gsb->base.subdev.device; struct nvkm_secboot *sb = &gsb->base; - void __iomem *mc; - u32 cfg; + u64 base, limit; + u32 value; - mc = ioremap(mc_base, 0xd00); - if (!mc) { - nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n"); - return -ENOMEM; - } - sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | - ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32); - sb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K) - << 17; - cfg = ioread32_native(mc + MC_SECURITY_CARVEOUT2_CFG0); - iounmap(mc); + /* set WPR info register to point at WPR base address register */ + value = nvkm_rd32(device, 0x100cd4); + value &= ~0xf; + value |= 0x2; + nvkm_wr32(device, 0x100cd4, value); + + /* read base address */ + value = nvkm_rd32(device, 0x100cd4); + base = (u64)(value >> 4) << 12; + + /* read limit */ + value = nvkm_rd32(device, 0x100cd4); + limit = (u64)(value >> 4) << 12; + + /* + * The upper address of the WPR seems to be computed wrongly and is + * actually SZ_128K - 1 bytes lower than it should be. Adjust the + * value accordingly. + */ + limit += SZ_128K - 1; + + sb->wpr_size = limit - base + 1; + sb->wpr_addr = base; + + nvkm_info(&sb->subdev, "WPR: %016llx-%016llx\n", sb->wpr_addr, + sb->wpr_addr + sb->wpr_size - 1); /* Check that WPR settings are valid */ if (sb->wpr_size == 0) { @@ -63,11 +89,6 @@ gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base) return -EINVAL; } - if (!(cfg & TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED)) { - nvkm_error(&sb->subdev, "WPR region not locked\n"); - return -EINVAL; - } - return 0; } #else @@ -85,7 +106,7 @@ gm20b_secboot_oneinit(struct nvkm_secboot *sb) struct gm200_secboot *gsb = gm200_secboot(sb); int ret; - ret = gm20b_secboot_tegra_read_wpr(gsb, TEGRA210_MC_BASE); + ret = gm20b_secboot_tegra_read_wpr(gsb); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c index 28ca29d0eeee..d84e85825995 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c @@ -23,15 +23,13 @@ #include "acr.h" #include "gm200.h" -#define TEGRA186_MC_BASE 0x02c10000 - static int gp10b_secboot_oneinit(struct nvkm_secboot *sb) { struct gm200_secboot *gsb = gm200_secboot(sb); int ret; - ret = gm20b_secboot_tegra_read_wpr(gsb, TEGRA186_MC_BASE); + ret = gm20b_secboot_tegra_read_wpr(gsb); if (ret) return ret; From patchwork Sat Nov 2 17:56:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11224207 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45E801390 for ; Sat, 2 Nov 2019 17:57:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2EC8621726 for ; Sat, 2 Nov 2019 17:57:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2EC8621726 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CBC0F6E4F4; Sat, 2 Nov 2019 17:57:02 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9EF9A6E4F4; Sat, 2 Nov 2019 17:56:59 +0000 (UTC) Received: by mail-wm1-x344.google.com with SMTP id t26so7970879wmi.4; Sat, 02 Nov 2019 10:56:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KgCN3eDLCLLxgvLwcLPRUvAfY7m1hNtkJ6cy/5CLIlQ=; b=X9f9Cn80JksT0/+OM6tXEoICwDPL6KCXzPNfPVM+DGpK4c9xkvOUr3pZ/tYju9viKu 383LQdh1Wz3QpE3dfpmTKDLHpj4T5xVe1nqYZP+Nor7vX74WBRymlBWxxWTiHHGqPlMn bt0tXmkH25tL44TvBKIeNtLZktFOH9Gv4zcnU9i6EdbJGmAP9rimEuixXda4S3NHl5ZI oAJx3Ej7xAK4bIZN62c6nGxikENrZclwzuv5fl73ICMqrWaeahYN9F6AgkxlhyhrVLAj Uye2i6p3/leEiqGJhBbmk3bOzDAI8qJ4cIAcSz8kn54Y2bBTPCz0PI2gr4ej0njXJo94 JKNg== X-Gm-Message-State: APjAAAXK9k5qZR7/T0cSqf4smDozZUqJJmJman4+uM0gbAidIou8Uko2 GyExEfCzt/N9+/Q8PlTq1jY= X-Google-Smtp-Source: APXvYqyLc1/offISysokD0OdxAmQjH1j//oM182q1XhuSlplZ67uIsjWLYLulL9JkZb2tJrQTDA8eg== X-Received: by 2002:a05:600c:22cb:: with SMTP id 11mr2199541wmg.117.1572717418126; Sat, 02 Nov 2019 10:56:58 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id i71sm14737287wri.68.2019.11.02.10.56.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2019 10:56:57 -0700 (PDT) From: Thierry Reding To: Ben Skeggs , Joerg Roedel Subject: [PATCH v2 8/9] drm/nouveau: gp10b: Add custom L2 cache implementation Date: Sat, 2 Nov 2019 18:56:36 +0100 Message-Id: <20191102175637.3065-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102175637.3065-1-thierry.reding@gmail.com> References: <20191102175637.3065-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KgCN3eDLCLLxgvLwcLPRUvAfY7m1hNtkJ6cy/5CLIlQ=; b=nWU0EQiDtPwW5QxBiIORTTGRkgsglc8fjDLPIwQuBoO+/gLIIG17Gx1U+B8QhZIY8W OnOFqylKcpVej5MtufBcHUDmGw4ajMffNyjD/fG91Q9mQwKicn14JyrxdzuwGVpf82zf 4CCEACwSecba1VFahwpsemlBE+NO4OJxG16ZcohkafhSwo5FzQFTtAaLGqVfQT2jNBTK tTkCAdTSL2D3jL+O5/vlt7790YxiZvH8k0R4ikUQWARdnhYzT6dis4bMDBg4ZzXRFz5r 6YliQip1Ur19euAXVw7nOHpBpfAsnlSvlm8kg5T2hJvmd6pkWJtbMxLdppDrZH5YZqFc pDsw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, nouveau@lists.freedesktop.org, Ben Dooks , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding --- Changes in v2: - remove IOMMU_API protection to increase compile coverage - relies on dummy dev_iommu_fwspec_get() helper .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 + .../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild | 1 + .../gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c | 65 +++++++++++++++++++ .../gpu/drm/nouveau/nvkm/subdev/ltc/priv.h | 2 + 5 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h index 644d527c3b96..d76f60d7d29a 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h @@ -40,4 +40,5 @@ int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gm200_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gp100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gp102_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); +int gp10b_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index b061df138142..231ec0073af3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2380,7 +2380,7 @@ nv13b_chipset = { .fuse = gm107_fuse_new, .ibus = gp10b_ibus_new, .imem = gk20a_instmem_new, - .ltc = gp102_ltc_new, + .ltc = gp10b_ltc_new, .mc = gp10b_mc_new, .mmu = gp10b_mmu_new, .secboot = gp10b_secboot_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild index 2b6d36ea7067..728d75010847 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild @@ -6,3 +6,4 @@ nvkm-y += nvkm/subdev/ltc/gm107.o nvkm-y += nvkm/subdev/ltc/gm200.o nvkm-y += nvkm/subdev/ltc/gp100.o nvkm-y += nvkm/subdev/ltc/gp102.o +nvkm-y += nvkm/subdev/ltc/gp10b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c new file mode 100644 index 000000000000..c0063c7caa50 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2019 NVIDIA Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Thierry Reding + */ + +#include "priv.h" + +static void +gp10b_ltc_init(struct nvkm_ltc *ltc) +{ + struct nvkm_device *device = ltc->subdev.device; + struct iommu_fwspec *spec; + + nvkm_wr32(device, 0x17e27c, ltc->ltc_nr); + nvkm_wr32(device, 0x17e000, ltc->ltc_nr); + nvkm_wr32(device, 0x100800, ltc->ltc_nr); + + spec = dev_iommu_fwspec_get(device->dev); + if (spec) { + u32 sid = spec->ids[0] & 0xffff; + + /* stream ID */ + nvkm_wr32(device, 0x160000, sid << 2); + } +} + +static const struct nvkm_ltc_func +gp10b_ltc = { + .oneinit = gp100_ltc_oneinit, + .init = gp10b_ltc_init, + .intr = gp100_ltc_intr, + .cbc_clear = gm107_ltc_cbc_clear, + .cbc_wait = gm107_ltc_cbc_wait, + .zbc = 16, + .zbc_clear_color = gm107_ltc_zbc_clear_color, + .zbc_clear_depth = gm107_ltc_zbc_clear_depth, + .zbc_clear_stencil = gp102_ltc_zbc_clear_stencil, + .invalidate = gf100_ltc_invalidate, + .flush = gf100_ltc_flush, +}; + +int +gp10b_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +{ + return nvkm_ltc_new_(&gp10b_ltc, device, index, pltc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h index 2fcf18e46ce3..eca5a711b1b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h @@ -46,4 +46,6 @@ void gm107_ltc_zbc_clear_depth(struct nvkm_ltc *, int, const u32); int gp100_ltc_oneinit(struct nvkm_ltc *); void gp100_ltc_init(struct nvkm_ltc *); void gp100_ltc_intr(struct nvkm_ltc *); + +void gp102_ltc_zbc_clear_stencil(struct nvkm_ltc *, int, const u32); #endif From patchwork Sat Nov 2 17:56:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11224209 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEBF8112B for ; Sat, 2 Nov 2019 17:57:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 979A821726 for ; Sat, 2 Nov 2019 17:57:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 979A821726 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 059936E516; Sat, 2 Nov 2019 17:57:06 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1ACE56E500; Sat, 2 Nov 2019 17:57:02 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id q130so12044037wme.2; Sat, 02 Nov 2019 10:57:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hRybqVavQHo4kc2uAW1DufA56ffoS4VWZ8W5YOU7UtQ=; b=DGCLmKbr29oaN5qiB0pqVP6rrJakaJxG6neTC/o+CSuWyHtaF092uxFZr7ds/y5RpA GIIJP+IcbhR12MglyKMjjnI+tqBqfP5JRhHXCs4jsCxEA1CWBxgvh1HetEtIeB3eHk7x mwzz1Qns6BS+uzbxWAbWAtDY164UUBJrmECuzwh1OnGyhRWqCIJGv4Uke9uV4rRhzO/H L1N7Q9fdkMPAY0H/ZK4lVzCwrG5VVg8q4RuNsM6z4HjdCIL1375zhaZO///2OHxBVjcc HxVW2/q3tUAKGpyMUVTyZQCRxrgiW0Dj5twQ8to6LOe5usv5OrqoD8ThMgTEkkcThPZ4 3rLQ== X-Gm-Message-State: APjAAAXz046opAxiZIZOifydkomjoXrHqYOJP9b76R3h5H3JuMjTroy/ uDSrkBLGHCvRvuxGDGtYWtJberMN X-Google-Smtp-Source: APXvYqylSa5xQza6BCuat0c+VFhWosAfc/mcoFK3Z3DTN66n2gfL4tq3KX7mnuNq/rdbV9NYuPbAcw== X-Received: by 2002:a1c:7ec2:: with SMTP id z185mr15811883wmc.79.1572717420566; Sat, 02 Nov 2019 10:57:00 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id b3sm6918849wmh.17.2019.11.02.10.56.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2019 10:56:59 -0700 (PDT) From: Thierry Reding To: Ben Skeggs , Joerg Roedel Subject: [PATCH v2 9/9] drm/nouveau: gp10b: Use correct copy engine Date: Sat, 2 Nov 2019 18:56:37 +0100 Message-Id: <20191102175637.3065-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191102175637.3065-1-thierry.reding@gmail.com> References: <20191102175637.3065-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hRybqVavQHo4kc2uAW1DufA56ffoS4VWZ8W5YOU7UtQ=; b=kGdAlsC0kEb4EWVcirGKrl+8N8G7z11eyL+N++FGbwwSzSoE6ZcKMLbYcO8O5MdHOg /IO8dqfY6v0T5HTtAWyebqsKBaTGXbhc9QsdM8p72pWjQu+b7J+v8R1PZIHMiVh0nFjI uM1nErfIpv1RyrpdMMbnwoT1L7pfUI3/Gv0yONmxOc32v6QGgAj+wsOU3sPZggGQdUtv 0gBO1OXVkMZiZPD4RnAsf8+xvDExix3v/FbSNTLdzkj6GsKNigJ/txIoV4KYIw/N11wB GFd5SNI+R06IQtGoyrul/YY6ihqwEkhOwNXA1P/S8jcoculMy2EX307WJrYSmpcc0FW/ PKeA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, nouveau@lists.freedesktop.org, Ben Dooks , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding gp10b uses the new engine enumeration mechanism introduced in the Pascal architecture. As a result, the copy engine, which used to be at index 2 for prior Tegra GPU instantiations, has now moved to index 0. Fix up the index and also use the gp100 variant of the copy engine class because on gp10b the PASCAL_DMA_COPY_B class is not supported. Signed-off-by: Thierry Reding --- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 231ec0073af3..eba450e689b2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2387,7 +2387,7 @@ nv13b_chipset = { .pmu = gm20b_pmu_new, .timer = gk20a_timer_new, .top = gk104_top_new, - .ce[2] = gp102_ce_new, + .ce[0] = gp100_ce_new, .dma = gf119_dma_new, .fifo = gp10b_fifo_new, .gr = gp10b_gr_new,