From patchwork Tue Nov 5 23:40:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 11228947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A10241599 for ; Tue, 5 Nov 2019 23:43:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D19E2087E for ; Tue, 5 Nov 2019 23:43:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AuSe0hVB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5D19E2087E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iS8Tk-00070U-FF for patchwork-qemu-devel@patchwork.kernel.org; Tue, 05 Nov 2019 18:43:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37970) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iS8SA-0005UU-QE for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iS8S9-0004d2-Oj for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:38 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:37421) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iS8S9-0004bm-HA for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:37 -0500 Received: by mail-wr1-x443.google.com with SMTP id t1so17626746wrv.4 for ; Tue, 05 Nov 2019 15:41:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RzXz801WN8Wx2siaVGOD6DywcY9lAErvVsKc+KJI/kM=; b=AuSe0hVBeklV+RVM2hnDJCbwpAIF4Z34BL4zM7yMYZKcHOZxyxaNgfQrW8ZV8e2e++ mU6fdzUZqxpe6oeiDXzA9uCIoSJgVAhr7b/1QtNaRVNHvUBIUY6Bxm7G53FA5K4NPGBP GJ9CZ3oqTM9W9cQI1PIcE25klx96XF5SI8Gl7A9qc0jz4/DEbFLlCrTcO9BvbruNLsSK tmOKG1nUQiVkFT2dRCSVlZfCqlryUNsXrx6ZJlbnHlgsnfZP6qlzw28VHIwg5NpK3UBz rRNpgLBG/ZYSofRzRYBaA+B/CL5/wezGWuTonyTcxRinVMLyG161MlWQ/nUg3xsn/S5X s/Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RzXz801WN8Wx2siaVGOD6DywcY9lAErvVsKc+KJI/kM=; b=otWejV2qNYlX0mUM+nsDf8OrZfK6gkJAr8get2rQaQoOf8oL+XvhHJqaNBMYIuC5SE NTSGuov/tG/ip8WY1o8JHzow0UnZaVh9mqH4r0idk0PITxf0FOw3/8Q8FVKSFncRP4/k dvDyGrAEHyhNNNMhcallHhDZeZTnaC0kCKWilosyvRyHh4ldHxvAUwCQpGUiWQrEMEa4 1YT9jbJcdiMlM4U5CLY/ktQorjOi47pnsBqgzhbcEXWKsVTgadWuL3qgxQv7ezc+jXqr AFQ87vc/2PvHos3NgMViVUGoUgi/OPVn18SpyUX05JCB4/zocpiU+ZuFKeeXj1Fh/PXd CdUQ== X-Gm-Message-State: APjAAAWkRkr3QFpSbFjQzYGLPLsZSszH4bIBNCvxWzpK7D7CMkUPMuyu Vn1jh8edVnOtLKqvcUHFXDTvkBdynL9urQ== X-Google-Smtp-Source: APXvYqyJwJv+kQe8FbjKTbzUGqNNcZWRvqFVq0poixXXwRZvPFUTVnAURAYcejKoEutFVdFYJQErCw== X-Received: by 2002:adf:d850:: with SMTP id k16mr25717671wrl.204.1572997296466; Tue, 05 Nov 2019 15:41:36 -0800 (PST) Received: from moi-limbo-9350.home (host86-144-13-94.range86-144.btcentralplus.com. [86.144.13.94]) by smtp.gmail.com with ESMTPSA id q25sm27295010wra.3.2019.11.05.15.41.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 15:41:36 -0800 (PST) From: Beata Michalska To: qemu-devel@nongnu.org Subject: [PATCH v2 1/4] tcg: cputlb: Add probe_read Date: Tue, 5 Nov 2019 23:40:57 +0000 Message-Id: <20191105234100.22052-2-beata.michalska@linaro.org> In-Reply-To: <20191105234100.22052-1-beata.michalska@linaro.org> References: <20191105234100.22052-1-beata.michalska@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, quintela@redhat.com, richard.henderson@linaro.org, dgilbert@redhat.com, shameerali.kolothum.thodi@huawei.com, eric.auger@redhat.com, qemu-arm@nongnu.org, pbonzini@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add probe_read alongside the write probing equivalent. Signed-off-by: Beata Michalska Reviewed-by: Alex Bennée --- include/exec/exec-all.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d85e610..350c4b4 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -339,6 +339,12 @@ static inline void *probe_write(CPUArchState *env, target_ulong addr, int size, return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); } +static inline void *probe_read(CPUArchState *env, target_ulong addr, int size, + int mmu_idx, uintptr_t retaddr) +{ + return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); +} + #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ /* Estimated block size for TB allocation. */ From patchwork Tue Nov 5 23:40:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 11228949 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 896C21599 for ; Tue, 5 Nov 2019 23:44:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4403121A49 for ; Tue, 5 Nov 2019 23:44:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="uUPeAAFW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4403121A49 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51776 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iS8VL-0000S5-MJ for patchwork-qemu-devel@patchwork.kernel.org; Tue, 05 Nov 2019 18:44:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38024) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iS8SI-0005gy-6b for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iS8SG-0004i8-KI for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:46 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:40844) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iS8SG-0004hU-CB for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:44 -0500 Received: by mail-wm1-x342.google.com with SMTP id f3so1287677wmc.5 for ; Tue, 05 Nov 2019 15:41:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Sy5cjMuouBWQH2G8fTg0cVy6rCUVCOD5IYH6fYB1xWE=; b=uUPeAAFWpsQVgDgX9zK629s/MRIZYqBMA0FkLiJ+dStO1CsqkRMZDjT5RjUrxtr7UM wEu1502lhzwyB0p0X39wmN1PL4v58XvjhzGF/n1yD4edCwvXmuQuxVzN/uabeWa8hVMA H02fxKdt5547GpIbXOdfQF1u+SPzdTIENnkrFdIpXVBKtKXCCbdwtCkaocUiLsNqeWdW XZ6enM+vKC11nJta6W4iZsL1KS0IfjH/M6rfP8JVImloT+0oPCxmQ+Duz59oeuaAvbZ9 7pBzvWbx0rnPRFJm9er3B/ArQxP1yujQxvYDOl8FLaUL4+qbSfzH+wkD+Dba0cJlSr/K GbOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Sy5cjMuouBWQH2G8fTg0cVy6rCUVCOD5IYH6fYB1xWE=; b=IwvzzKVDxVY8jji2WGkRXSeu00amH1oe19dhOFK7r7cx2m2Hx82z3fjUAdAbTtf160 +ZW/Eg/ttrOoDXfrvi26B4we5WfsrJA7mqfAiRaOAibGp8MF8eqNmdCtiRtS1i1xAfoP Zt8xL8KMSmN3NcKSxcrdHZT2+d90iIU6gtm2nU+Z62QeQ08iza8CJG1K+fVyBJ5cFdGI +2WoOwVe48VYPHT1gpIEreuiE7Tw9o+XV021DOXAccIEIGlZ74Zb7jot1zmPf/VfxSpR CxTO09Q1PwiJaU7UekTW7WWC7BXIa41fFzz6PzE/SHe2/YNQqSSk4qDcmKbTHpOssvE8 MmSw== X-Gm-Message-State: APjAAAUfFcPTxZdxazA2ZkUvFCsinZgTvnpr/vcDBTmGnD57NqHx2DC9 eLTNPyXaPYKfe29U9C2xWextpftpdJZFkQ== X-Google-Smtp-Source: APXvYqy4a1ZnKMeH/iJh6Aqh/1SQt4byy5bsJhpPafnwYqoagdkX6GmiD+8k/u0Psncw1+fwkQWDcw== X-Received: by 2002:a1c:558a:: with SMTP id j132mr1251077wmb.21.1572997302646; Tue, 05 Nov 2019 15:41:42 -0800 (PST) Received: from moi-limbo-9350.home (host86-144-13-94.range86-144.btcentralplus.com. [86.144.13.94]) by smtp.gmail.com with ESMTPSA id q25sm27295010wra.3.2019.11.05.15.41.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 15:41:42 -0800 (PST) From: Beata Michalska To: qemu-devel@nongnu.org Subject: [PATCH v2 2/4] Memory: Enable writeback for given memory region Date: Tue, 5 Nov 2019 23:40:58 +0000 Message-Id: <20191105234100.22052-3-beata.michalska@linaro.org> In-Reply-To: <20191105234100.22052-1-beata.michalska@linaro.org> References: <20191105234100.22052-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, quintela@redhat.com, richard.henderson@linaro.org, dgilbert@redhat.com, shameerali.kolothum.thodi@huawei.com, eric.auger@redhat.com, qemu-arm@nongnu.org, pbonzini@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add an option to trigger memory writeback to sync given memory region with the corresponding backing store, case one is available. This extends the support for persistent memory, allowing syncing on-demand. Signed-off-by: Beata Michalska --- exec.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/exec/memory.h | 6 ++++++ include/exec/ram_addr.h | 8 ++++++++ include/qemu/cutils.h | 1 + memory.c | 12 ++++++++++++ util/cutils.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 117 insertions(+) diff --git a/exec.c b/exec.c index ffdb518..e1f06de 100644 --- a/exec.c +++ b/exec.c @@ -65,6 +65,8 @@ #include "exec/ram_addr.h" #include "exec/log.h" +#include "qemu/pmem.h" + #include "migration/vmstate.h" #include "qemu/range.h" @@ -2156,6 +2158,47 @@ int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) return 0; } +/* + * Trigger sync on the given ram block for range [start, start + length] + * with the backing store if one is available. + * Otherwise no-op. + * @Note: this is supposed to be a synchronous op. + */ +void qemu_ram_writeback(RAMBlock *block, ram_addr_t start, ram_addr_t length) +{ + void *addr = ramblock_ptr(block, start); + + /* + * The requested range might spread up to the very end of the block + */ + if ((start + length) > block->used_length) { + qemu_log("%s: sync range outside the block boundaries: " + "start: " RAM_ADDR_FMT " length: " RAM_ADDR_FMT + " block length: " RAM_ADDR_FMT " Narrowing down ..." , + __func__, start, length, block->used_length); + length = block->used_length - start; + } + +#ifdef CONFIG_LIBPMEM + /* The lack of support for pmem should not block the sync */ + if (ramblock_is_pmem(block)) { + pmem_persist(addr, length); + } else +#endif + if (block->fd >= 0) { + /** + * Case there is no support for PMEM or the memory has not been + * specified as persistent (or is not one) - use the msync. + * Less optimal but still achieves the same goal + */ + if (qemu_msync(addr, length, qemu_host_page_size, block->fd)) { + warn_report("%s: failed to sync memory range: start: " + RAM_ADDR_FMT " length: " RAM_ADDR_FMT, + __func__, start, length); + } + } +} + /* Called with ram_list.mutex held */ static void dirty_memory_extend(ram_addr_t old_ram_size, ram_addr_t new_ram_size) diff --git a/include/exec/memory.h b/include/exec/memory.h index e499dc2..27a84e0 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1265,6 +1265,12 @@ void *memory_region_get_ram_ptr(MemoryRegion *mr); */ void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp); +/** + * memory_region_do_writeback: Trigger writeback for selected address range + * [addr, addr + size] + * + */ +void memory_region_do_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size); /** * memory_region_set_log: Turn dirty logging on or off for a region. diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index bed0554..5adebb0 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -174,6 +174,14 @@ void qemu_ram_free(RAMBlock *block); int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp); +void qemu_ram_writeback(RAMBlock *block, ram_addr_t start, ram_addr_t length); + +/* Clear whole block of mem */ +static inline void qemu_ram_block_writeback(RAMBlock *block) +{ + qemu_ram_writeback(block, 0, block->used_length); +} + #define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1) #define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_CODE)) diff --git a/include/qemu/cutils.h b/include/qemu/cutils.h index b54c847..41c5fa9 100644 --- a/include/qemu/cutils.h +++ b/include/qemu/cutils.h @@ -130,6 +130,7 @@ const char *qemu_strchrnul(const char *s, int c); #endif time_t mktimegm(struct tm *tm); int qemu_fdatasync(int fd); +int qemu_msync(void *addr, size_t length, size_t alignment, int fd); int fcntl_setfl(int fd, int flag); int qemu_parse_fd(const char *param); int qemu_strtoi(const char *nptr, const char **endptr, int base, diff --git a/memory.c b/memory.c index c952eab..15734a0 100644 --- a/memory.c +++ b/memory.c @@ -2214,6 +2214,18 @@ void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp qemu_ram_resize(mr->ram_block, newsize, errp); } + +void memory_region_do_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size) +{ + /* + * Might be extended case needed to cover + * different types of memory regions + */ + if (mr->ram_block && mr->dirty_log_mask) { + qemu_ram_writeback(mr->ram_block, addr, size); + } +} + /* * Call proper memory listeners about the change on the newly * added/removed CoalescedMemoryRange. diff --git a/util/cutils.c b/util/cutils.c index fd591ca..7a50dbc 100644 --- a/util/cutils.c +++ b/util/cutils.c @@ -164,6 +164,53 @@ int qemu_fdatasync(int fd) #endif } +/** + * Sync changes made to the memory mapped file back to the backing + * storage. For POSIX compliant systems this will simply fallback + * to regular msync call (thus the required alignment). Otherwise + * it will trigger whole file sync (including the metadata case + * there is no support to skip that otherwise) + * + * @addr - start of the memory area to be synced + * @length - length of the are to be synced + * @align - alignment (expected to be PAGE_SIZE) + * @fd - file descriptor for the file to be synced + * (mandatory only for POSIX non-compliant systems) + */ +int qemu_msync(void *addr, size_t length, size_t align, int fd) +{ +#ifdef CONFIG_POSIX + size_t align_mask; + + /* Bare minimum of sanity checks on the alignment */ + /* The start address needs to be a multiple of PAGE_SIZE */ + align = MAX(align, qemu_real_host_page_size); + align_mask = ~(qemu_real_host_page_size - 1); + align = (align + ~align_mask) & align_mask; + + align_mask = ~(align - 1); + /** + * There are no strict reqs as per the length of mapping + * to be synced. Still the length needs to follow the address + * alignment changes. Additionally - round the size to the multiple + * of requested alignment (expected as PAGE_SIZE) + */ + length += ((uintptr_t)addr & (align - 1)); + length = (length + ~align_mask) & align_mask; + + addr = (void *)((uintptr_t)addr & align_mask); + + return msync(addr, length, MS_SYNC); +#else /* CONFIG_POSIX */ + /** + * Perform the sync based on the file descriptor + * The sync range will most probably be wider than the one + * requested - but it will still get the job done + */ + return qemu_fdatasync(fd); +#endif /* CONFIG_POSIX */ +} + #ifndef _WIN32 /* Sets a specific flag */ int fcntl_setfl(int fd, int flag) From patchwork Tue Nov 5 23:40:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 11228951 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9FC41599 for ; Tue, 5 Nov 2019 23:47:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 963CF214B2 for ; Tue, 5 Nov 2019 23:47:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fF775Z+5" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 963CF214B2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iS8Xf-0002MT-U4 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 05 Nov 2019 18:47:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38055) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iS8SL-0005lf-4J for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iS8SK-0004jv-34 for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:48 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:34227) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iS8SJ-0004jX-Tj for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:48 -0500 Received: by mail-wm1-x341.google.com with SMTP id v3so1020145wmh.1 for ; Tue, 05 Nov 2019 15:41:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WySS2tj+mpRubnHgzdskn314seKpdU+7MYMHfRQ/Nvs=; b=fF775Z+5dIMsRGdWH+I2PtFx9WyG3X0MMIUcG3qgO1Q0xghnVUcLQ3a1gFaErboFW3 e/ON+bySNI0QJXVDif7PZy3RFU8Lq2KxH9DuNKJbfajsMyo/SrRs+RjJCaADd9YarBl3 /4WymLEBvZwVyUk2JU3KlH1x8imALHQp7HFVV0MckiJd5A71EEJxujJYu9riFJSUCWwi edGzcFkmpO30uUO2Eje/Ofr14pd3dV2c39c8xi0zcZk6YjywUFMPA+MSOMidL36sHGvr 5IVOqtn/baRYdl/s7pRUYNOy+fEfWvIWlaa09Ivh8X/6MXClwiMAOJa+r9txPwQ0npHD zf4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WySS2tj+mpRubnHgzdskn314seKpdU+7MYMHfRQ/Nvs=; b=sHst/9RmE5tMij9Nyb590o8O7P0p5KYnqKGHf0FfYY97WKgNHol3wmDo86l1EkiXYU MJhHhKXuSSk4vPysY1YGmsYQRGUf8HwHbPKCGw/ZJF9GWC2HuxYtDWBbx9ouEnT2T0bd jKtk77MfmIQTNn0bSLfb6od+clhAhh6UrBMKzKP3G6CPbnz64PeL/8Er/xE/OYe9YJ79 1ThOHi/se/jyHMtLL8LOdJHm1vhpio1xQ1D0x0cfrKniRK9a9gX2hB5hG5ec6T7gXTsi srsGH/h8nax1laay0m/e3LdSzQlSva/DB0PbgILSm38BemvHRB0PdibgdBu/veROlpjd bA4Q== X-Gm-Message-State: APjAAAW1fuBcgyNztxhwHY6c+c49N7GN8PY6m8AKGQVwPg9Cu45NFD5d uRu3gDr7DVfjtKeHtAqfkHCnGJ/NNe/bSw== X-Google-Smtp-Source: APXvYqxl7N4pKSLFxno3Rdg0GkCD+jJMq+vBS7SlRpf7SeN2uE39lGmusweoOD6EHar026xvARW1hg== X-Received: by 2002:a7b:c38c:: with SMTP id s12mr1341166wmj.84.1572997306754; Tue, 05 Nov 2019 15:41:46 -0800 (PST) Received: from moi-limbo-9350.home (host86-144-13-94.range86-144.btcentralplus.com. [86.144.13.94]) by smtp.gmail.com with ESMTPSA id q25sm27295010wra.3.2019.11.05.15.41.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 15:41:46 -0800 (PST) From: Beata Michalska To: qemu-devel@nongnu.org Subject: [PATCH v2 3/4] migration: ram: Switch to ram block writeback Date: Tue, 5 Nov 2019 23:40:59 +0000 Message-Id: <20191105234100.22052-4-beata.michalska@linaro.org> In-Reply-To: <20191105234100.22052-1-beata.michalska@linaro.org> References: <20191105234100.22052-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, quintela@redhat.com, richard.henderson@linaro.org, dgilbert@redhat.com, shameerali.kolothum.thodi@huawei.com, eric.auger@redhat.com, qemu-arm@nongnu.org, pbonzini@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Switch to ram block writeback for pmem migration. Signed-off-by: Beata Michalska Reviewed-by: Richard Henderson Acked-by: Dr. David Alan Gilbert Reviewed-by: Alex Bennée --- migration/ram.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/migration/ram.c b/migration/ram.c index 5078f94..38070f1 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -33,7 +33,6 @@ #include "qemu/bitops.h" #include "qemu/bitmap.h" #include "qemu/main-loop.h" -#include "qemu/pmem.h" #include "xbzrle.h" #include "ram.h" #include "migration.h" @@ -3981,9 +3980,7 @@ static int ram_load_cleanup(void *opaque) RAMBlock *rb; RAMBLOCK_FOREACH_NOT_IGNORED(rb) { - if (ramblock_is_pmem(rb)) { - pmem_persist(rb->host, rb->used_length); - } + qemu_ram_block_writeback(rb); } xbzrle_load_cleanup(); From patchwork Tue Nov 5 23:41:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 11228953 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EBBE51599 for ; Tue, 5 Nov 2019 23:49:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A8A82214B2 for ; Tue, 5 Nov 2019 23:49:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="qAYHjiPa" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A8A82214B2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iS8Zo-0003oW-3W for patchwork-qemu-devel@patchwork.kernel.org; Tue, 05 Nov 2019 18:49:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38093) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iS8SP-0005tR-LN for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iS8SO-0004lp-6r for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:53 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:45837) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iS8SO-0004lW-13 for qemu-devel@nongnu.org; Tue, 05 Nov 2019 18:41:52 -0500 Received: by mail-wr1-x443.google.com with SMTP id q13so23570831wrs.12 for ; Tue, 05 Nov 2019 15:41:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8lNKiTvXzplhNbh/GcJVZyL/fynA0fCPHUNuHIruE/g=; b=qAYHjiPaen2PldMQMuyzz31BaZEpScWhl3dgB5BGybuKI7BOpksA4pcEHY1ywJyg6L NqCVBxb3H9Q1Dkxjfjx6pZa3xOK6oCyiA8e00qdtiA7Uy1knGa0PbVsdfS+g7CdAvjW7 b/g61P+spe/jiqJRAZhLC4cscWJGn2z5TUFjDeywoLzNyqIAG8MWDVGcElV4u9m6dFGo Ul85U6nRz+/OEbJOQ4A+8b3kBg+9/NXSHZUc5ck92vLbSp4UgUok0ve7mEGQlV1FTV/a w3pxRhRCdhYLDsguJEpR8csZlFEDWspMCLYokUVHE0nhobMvgAJLk3atnZSuyzsgkni+ 9Dyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8lNKiTvXzplhNbh/GcJVZyL/fynA0fCPHUNuHIruE/g=; b=rguESLH+PLDxQuEncsxkjtKgPq3d+3PHEXp2gAtMTK0ttinrwQuH6uLwlcOb6W16+X gC0cNoz8W7PYu4NRoJwOBipkc7pU0mLrRLq1iG8b9Z2lDGAL7C4PMQGrLDeR1HyZT/yT rT1+fD5A7eCvLzEL2ou3E8eIkZbvQ6jv1edbFC7Wq+GKIxaWq8AAqOevQoc+J1bOoX2w zaFRusaLNEYnh6xNprWpYu6f1c2aypxuYsMgOEAqJjjRbEpuHM7YL7eeq036E0eJZ8pi +700CliHJXwMgmsd9GLOWNWj/8D5BBiVvzoWNR0x1ap646y5eastDrW0PCDZzFmxf4N7 Utnw== X-Gm-Message-State: APjAAAWMEMjQnusUb1n0nAkZzwUFefUMg9R+QAsiejKXnSVouQaaVcWq iW/pzfnwogk0ULANWWMSPjahN6dY6TTrzQ== X-Google-Smtp-Source: APXvYqwt9r6dQ0PzrUZBPgiZSJtTuB7gsK8Ja4/pTzruE816FfKjnKiaAL2FHWDCKJeUmE6481yUwg== X-Received: by 2002:adf:9044:: with SMTP id h62mr31518193wrh.91.1572997310898; Tue, 05 Nov 2019 15:41:50 -0800 (PST) Received: from moi-limbo-9350.home (host86-144-13-94.range86-144.btcentralplus.com. [86.144.13.94]) by smtp.gmail.com with ESMTPSA id q25sm27295010wra.3.2019.11.05.15.41.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2019 15:41:50 -0800 (PST) From: Beata Michalska To: qemu-devel@nongnu.org Subject: [PATCH v2 4/4] target/arm: Add support for DC CVAP & DC CVADP ins Date: Tue, 5 Nov 2019 23:41:00 +0000 Message-Id: <20191105234100.22052-5-beata.michalska@linaro.org> In-Reply-To: <20191105234100.22052-1-beata.michalska@linaro.org> References: <20191105234100.22052-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, quintela@redhat.com, richard.henderson@linaro.org, dgilbert@redhat.com, shameerali.kolothum.thodi@huawei.com, eric.auger@redhat.com, qemu-arm@nongnu.org, pbonzini@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" ARMv8.2 introduced support for Data Cache Clean instructions to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence) - DV CVADP. Both specify conceptual points in a memory system where all writes that are to reach them are considered persistent. The support provided considers both to be actually the same so there is no distinction between the two. If none is available (there is no backing store for given memory) both will result in Data Cache Clean up to the point of coherency. Otherwise sync for the specified range shall be performed. Signed-off-by: Beata Michalska Reviewed-by: Richard Henderson --- linux-user/elfload.c | 2 ++ target/arm/cpu.h | 10 ++++++++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f6693e5..07b16cc 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -656,6 +656,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); + GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); return hwcaps; } @@ -665,6 +666,7 @@ static uint32_t get_elf_hwcap2(void) ARMCPU *cpu = ARM_CPU(thread_cpu); uint32_t hwcaps = 0; + GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e1a66a2..0dc22c6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3617,6 +3617,16 @@ static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; } +static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; +} + +static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 68baf04..e6a033e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -661,6 +661,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64isar0 = t; t = cpu->isar.id_aa64isar1; + t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ diff --git a/target/arm/helper.c b/target/arm/helper.c index be67e2c..00c72e4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5924,6 +5924,52 @@ static const ARMCPRegInfo rndr_reginfo[] = { .access = PL0_R, .readfn = rndr_readfn }, REGINFO_SENTINEL }; + +#ifndef CONFIG_USER_ONLY +static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, + uint64_t value) +{ + ARMCPU *cpu = env_archcpu(env); + /* CTR_EL0 System register -> DminLine, bits [19:16] */ + uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); + uint64_t vaddr_in = (uint64_t) value; + uint64_t vaddr = vaddr_in & ~(dline_size - 1); + void *haddr; + int mem_idx = cpu_mmu_index(env, false); + + /* This won't be crossing page boundaries */ + haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); + if (haddr) { + + ram_addr_t offset; + MemoryRegion *mr; + + /* RCU lock is already being held */ + mr = memory_region_from_host(haddr, &offset); + + if (mr) { + memory_region_do_writeback(mr, offset, dline_size); + } + } +} + +static const ARMCPRegInfo dcpop_reg[] = { + { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, + .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .accessfn = aa64_cacheop_access, .writefn = dccvap_writefn }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo dcpodp_reg[] = { + { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, + .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .accessfn = aa64_cacheop_access, .writefn = dccvap_writefn }, + REGINFO_SENTINEL +}; +#endif /*CONFIG_USER_ONLY*/ + #endif static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, @@ -6884,6 +6930,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } +#ifndef CONFIG_USER_ONLY + /* Data Cache clean instructions up to PoP */ + if (cpu_isar_feature(aa64_dcpop, cpu)) { + define_one_arm_cp_reg(cpu, dcpop_reg); + + if (cpu_isar_feature(aa64_dcpodp, cpu)) { + define_one_arm_cp_reg(cpu, dcpodp_reg); + } + } +#endif /*CONFIG_USER_ONLY*/ #endif /*