From patchwork Wed Nov 6 09:42:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 11229817 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE1211747 for ; Wed, 6 Nov 2019 09:42:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BB7F52166E for ; Wed, 6 Nov 2019 09:42:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ZHPpdCQO"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="1jsG+JG/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BB7F52166E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=HziKVi/gDqWGStL3VspsbR5dHAKGtiw0ASVe5HE2Ysc=; b=ZHPpdCQOrFeUxo+ae1YoX7l3UI j+CZ+qNZB8Z1yvKKH57CcuIydgd0jQqII74T46QuZLPvnzMUDng8l1h/MIRJlfjfVwIidujeIU4M+ 2fG75sbYs5DxhII1pRrxN49Xso20Pn99bsjsXAlfDzzmWeAFkEpZ9KXsTXhXt0UmCQyNtF95SNSvY iC18IcY/VQU1OyWLevn3zoGo8IQWYXk7agSS+SQZTqrQBAh2A4PJgnPGL+sG+Yw1SfrdTisbdTOmS gZun43yVDxSmArCwzJYMg1yumfwHsdiws0PTc7MLbsqZGYHgiBJ8gyrtWpjzCszMVGNXP9k5CFRdt hHixbohQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iSHps-00057y-Qi; Wed, 06 Nov 2019 09:42:44 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iSHpi-0004vJ-5g for linux-arm-kernel@lists.infradead.org; Wed, 06 Nov 2019 09:42:35 +0000 Received: from e123331-lin.home (lfbn-mar-1-643-104.w90-118.abo.wanadoo.fr [90.118.215.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2B0D821848; Wed, 6 Nov 2019 09:42:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573033353; bh=2Ud6E61gmFSpjdcQqLY79p0ZM6SvCo8yhcRT5z4+27I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=1jsG+JG/MsJdY/4pl3GRUqXigrT/VAabr0SxCmEYQiR2125P+1KJ7iUn7x7F1ATqh BZmXCECgIrC/smEefJwaGgGdAEPsxsEYUAf7BC5CADa9FhLeHD6vQ2DkLgUdyv7JAL bNGnBVFc3VBnE9St6zPdBkbeQKwEE5VoWmkKlXt8= From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] ARM/decompressor: avoid CP15 barrier instructions in v7 cache setup code Date: Wed, 6 Nov 2019 10:42:18 +0100 Message-Id: <20191106094219.24365-2-ardb@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191106094219.24365-1-ardb@kernel.org> References: <20191106094219.24365-1-ardb@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191106_014234_248520_C3B0B00C X-CRM114-Status: GOOD ( 12.65 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Commit e17b1af96b2afc38e684aa2f1033387e2ed10029 "ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cache" added some explicit handling of the CP15BEN bit in the SCTLR system register, to ensure that CP15 barrier instructions are enabled, even if we enter the decompressor via the EFI stub. However, as it turns out, there are other ways in which we may end up using CP15 barrier instructions without them being enabled. I.e., if the decompressor startup code skips the cache_on() call initially, we end up calling cache_clean_flush() with the caches and MMU off, in which case the CP15BEN bit in SCTLR may not be programmed either. And in fact, cache_on() itself issues CP15 barrier instructions before actually enabling them by programming the new SCTLR value (and issuing an ISB) Since all these routines are specific to v7, let's clean this up by using the ordinary v7 barrier instructions in the v7 specific cache handling routines, so that we never rely on the CP15 ones. This also avoids the issue where a barrier is required between programming SCTLR and using the CP15 barrier instructions, which would result in two different kinds of barriers being used in the same function. Cc: # v4.4+ Signed-off-by: Ard Biesheuvel --- arch/arm/boot/compressed/head.S | 35 ++++++++++++++------ 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 93dffed0ac6e..ec14687aea3c 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -656,6 +656,21 @@ params: ldr r0, =0x10000100 @ params_phys for RPC .align #endif + .macro v7dsb + ARM( .inst 0xf57ff04f @ v7+ dsb ) + THUMB( dsb ) + .endm + + .macro v7dmb + ARM( .inst 0xf57ff05f @ v7+ dmb ) + THUMB( dmb ) + .endm + + .macro v7isb + ARM( .inst 0xf57ff06f @ v7+ isb ) + THUMB( isb ) + .endm + /* * Turn on the cache. We need to setup some page tables so that we * can have both the I and D caches on. @@ -827,7 +842,7 @@ __armv7_mmu_cache_on: movne r6, #CB_BITS | 0x02 @ !XN blne __setup_mmu mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + v7dsb @ drain write buffer tst r11, #0xf @ VMSA mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs #endif @@ -849,11 +864,11 @@ __armv7_mmu_cache_on: mcrne p15, 0, r1, c3, c0, 0 @ load domain access control mcrne p15, 0, r6, c2, c0, 2 @ load ttb control #endif - mcr p15, 0, r0, c7, c5, 4 @ ISB + v7isb mcr p15, 0, r0, c1, c0, 0 @ load control register mrc p15, 0, r0, c1, c0, 0 @ and read it back mov r0, #0 - mcr p15, 0, r0, c7, c5, 4 @ ISB + v7isb mov pc, r12 __fa526_cache_on: @@ -1154,8 +1169,8 @@ __armv7_mmu_cache_off: mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB #endif mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c5, 4 @ ISB + v7dsb + v7isb mov pc, r12 /* @@ -1218,7 +1233,7 @@ __armv7_mmu_cache_flush: mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D b iflush hierarchical: - mcr p15, 0, r10, c7, c10, 5 @ DMB + v7dmb stmfd sp!, {r0-r7, r9-r11} mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr @@ -1232,7 +1247,7 @@ loop1: cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr + v7isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr and r2, r1, #7 @ extract the length of the cache lines add r2, r2, #4 @ add 4 (line length offset) @@ -1264,10 +1279,10 @@ finished: mov r10, #0 @ switch back to cache level 0 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr iflush: - mcr p15, 0, r10, c7, c10, 4 @ DSB + v7dsb mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB - mcr p15, 0, r10, c7, c10, 4 @ DSB - mcr p15, 0, r10, c7, c5, 4 @ ISB + v7dsb + v7isb mov pc, lr __armv5tej_mmu_cache_flush: From patchwork Wed Nov 6 09:42:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 11229819 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CC38C1747 for ; Wed, 6 Nov 2019 09:42:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AA89B2166E for ; Wed, 6 Nov 2019 09:42:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="USpM2K6l"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="QxrXnOkq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AA89B2166E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=b8Ddd51tnS+ErN22F6IlsRuXt0Ij1HeeoEpDtWbmQ74=; b=USpM2K6lhs7rrlqAZpUAg9bXHk 39+mFw8cWZFSdDTlpsYgzpcRDyUTvlVmqEADO35IJRu44dtt8g+mLbfwUz03VyPG0IvKj8JrWwhje U+J4OiGfsmuFonB5pG6pVYJAV4Vh1L+YdsSU7WnAEprDljYU4m9Sabr+Hnu0fusjD2BKKtea2jLEW e3GwZrCEog54NLecpxVZMTexSjqPQCF+uPX5sDOKlXPJngdJDkZ+PJO6SHGnj4n/K+qBqn9/fwYLM JoDScgeV0hH3hJ0nRVQViJEpzxaUEbZxTo8Ue+t59P1FVNdxN+Hbgye579WKjl0zI1qt1zBf/JDnU ooDa4yTQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iSHq4-0005LK-KK; Wed, 06 Nov 2019 09:42:56 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iSHpj-0004w5-Et for linux-arm-kernel@lists.infradead.org; Wed, 06 Nov 2019 09:42:36 +0000 Received: from e123331-lin.home (lfbn-mar-1-643-104.w90-118.abo.wanadoo.fr [90.118.215.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 53D2E2166E; Wed, 6 Nov 2019 09:42:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573033355; bh=Xpce4/ws0tivXiJphl965VRfX0ymYGfscPagSV/Lc+A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QxrXnOkqfSMB/uEQXUrwbnj2y+B6OqkECeKJMSqFor5flsu07VDZWtHa+ActjEKTY qB4azmQFNq2Du7+wp1or2VzlyvAHKVZzF7A1U+pKkz8moXqfvF8z4lQ4fq5Ho9uhRe nCMd90qWmhlp/YLJnxbHTptUMFR2HJbl6IJ21hmA= From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] Revert "ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cache" Date: Wed, 6 Nov 2019 10:42:19 +0100 Message-Id: <20191106094219.24365-3-ardb@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191106094219.24365-1-ardb@kernel.org> References: <20191106094219.24365-1-ardb@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191106_014235_538605_6B14A0DC X-CRM114-Status: GOOD ( 11.27 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This reverts commit e17b1af96b2afc38e684aa2f1033387e2ed10029, which is no longer necessary now that the v7 specific routines take care not to issue CP15 barrier instructions before they are enabled in SCTLR. Signed-off-by: Ard Biesheuvel --- arch/arm/boot/compressed/head.S | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index ec14687aea3c..4369f491b23d 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -1462,21 +1462,7 @@ ENTRY(efi_stub_entry) @ Preserve return value of efi_entry() in r4 mov r4, r0 - - @ our cache maintenance code relies on CP15 barrier instructions - @ but since we arrived here with the MMU and caches configured - @ by UEFI, we must check that the CP15BEN bit is set in SCTLR. - @ Note that this bit is RAO/WI on v6 and earlier, so the ISB in - @ the enable path will be executed on v7+ only. - mrc p15, 0, r1, c1, c0, 0 @ read SCTLR - tst r1, #(1 << 5) @ CP15BEN bit set? - bne 0f - orr r1, r1, #(1 << 5) @ CP15 barrier instructions - mcr p15, 0, r1, c1, c0, 0 @ write SCTLR - ARM( .inst 0xf57ff06f @ v7+ isb ) - THUMB( isb ) - -0: bl cache_clean_flush + bl cache_clean_flush bl cache_off @ Set parameters for booting zImage according to boot protocol