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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FaS33hhBgVArn91yix8dEhBmceHqNahuyU9paSIkKLY=; b=KmTX71GzeFFwhMjOSFRNctkN1StAZRFtOVTEEHy39KUxMyqxONtHczU2u4jXOeKv1zhlHUrWyUKfRnjxfepqxhu3Ny8NVYnPDAchpGrFrVWIadTA36C2QHd6cqGNRqjRmkabDS6k4Rp9L9DoSIPSev1YgmjPt1leAaKf1GGBREQ= X-Mailman-Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Flora.Cui@amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Flora Cui Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" add compute/gfx dispatch hang test for gfx9 Signed-off-by: Flora Cui --- tests/amdgpu/amdgpu_test.c | 12 +++++++ tests/amdgpu/amdgpu_test.h | 1 + tests/amdgpu/basic_tests.c | 67 ++++++++++++++++++++++++++++------- tests/amdgpu/deadlock_tests.c | 14 ++++++++ 4 files changed, 81 insertions(+), 13 deletions(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 94bc3056..3ac9d8d2 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -460,6 +460,18 @@ static void amdgpu_disable_suites() "illegal mem access test (set amdgpu.vm_fault_stop=2)", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + /* This test was ran on GFX9 only */ + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "gfx ring bad dispatch test (set amdgpu.lockup_timeout=50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + /* This test was ran on GFX9 only */ + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "compute ring bad dispatch test (set amdgpu.lockup_timeout=50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index 0cb6ee98..2b01bf41 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -241,6 +241,7 @@ CU_BOOL suite_syncobj_timeline_tests_enable(void); */ extern CU_TestInfo syncobj_timeline_tests[]; +void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip_type); /** * Helper functions diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index a57dcbb4..71c9220d 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -311,7 +311,8 @@ static uint32_t shader_bin[] = { enum cs_type { CS_BUFFERCLEAR, - CS_BUFFERCOPY + CS_BUFFERCOPY, + CS_HANG }; static const uint32_t bufferclear_cs_shader_gfx9[] = { @@ -473,6 +474,14 @@ static const uint32_t cached_cmd_gfx9[] = { 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0 }; +unsigned int memcpy_ps_hang[] = { + 0xFFFFFFFF, 0xBEFE0A7E, 0xBEFC0304, 0xC0C20100, + 0xC0800300, 0xC8080000, 0xC80C0100, 0xC8090001, + 0xC80D0101, 0xBF8C007F, 0xF0800F00, 0x00010002, + 0xBEFE040C, 0xBF8C0F70, 0xBF800000, 0xBF800000, + 0xF800180F, 0x03020100, 0xBF810000 +}; + int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size, unsigned alignment, unsigned heap, uint64_t alloc_flags, uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu, @@ -2189,6 +2198,10 @@ static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr, shader = buffercopy_cs_shader_gfx9; shader_size = sizeof(buffercopy_cs_shader_gfx9); break; + case CS_HANG: + shader = memcpy_ps_hang; + shader_size = sizeof(memcpy_ps_hang); + break; default: return -1; break; @@ -2409,7 +2422,8 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle, static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle, uint32_t ip_type, - uint32_t ring) + uint32_t ring, + int hang) { amdgpu_context_handle context_handle; amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4]; @@ -2425,7 +2439,8 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle, int bo_cmd_size = 4096; struct amdgpu_cs_request ibs_request = {0}; struct amdgpu_cs_ib_info ib_info= {0}; - uint32_t expired; + uint32_t expired, hang_state, hangs; + enum cs_type cs_type; amdgpu_bo_list_handle bo_list; struct amdgpu_cs_fence fence_status = {0}; @@ -2446,7 +2461,8 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle, CU_ASSERT_EQUAL(r, 0); memset(ptr_shader, 0, bo_shader_size); - r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY ); + cs_type = hang ? CS_HANG : CS_BUFFERCOPY; + r = amdgpu_dispatch_load_cs_shader(ptr_shader, cs_type); CU_ASSERT_EQUAL(r, 0); r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096, @@ -2532,14 +2548,21 @@ static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle, r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE, 0, &expired); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); - /* verify if memcpy test result meets with expected */ - i = 0; - while(i < bo_dst_size) { - CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]); - i++; + if (!hang) { + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(expired, true); + + /* verify if memcpy test result meets with expected */ + i = 0; + while(i < bo_dst_size) { + CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]); + i++; + } + } else { + r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); } r = amdgpu_bo_list_destroy(bo_list); @@ -2573,7 +2596,7 @@ static void amdgpu_compute_dispatch_test(void) for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id); - amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id); + amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id, 0); } } @@ -2590,7 +2613,25 @@ static void amdgpu_gfx_dispatch_test(void) for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id); - amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id); + amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id, 0); + } +} + +void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip_type) +{ + int r; + struct drm_amdgpu_info_hw_ip info; + uint32_t ring_id; + + r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &info); + CU_ASSERT_EQUAL(r, 0); + if (!info.available_rings) + printf("SKIP ... as there's no ring for ip %d\n", ip_type); + + for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { + amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0); + amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 1); + amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0); } } diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index 7d028829..61342d1a 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -114,6 +114,8 @@ static void amdgpu_deadlock_compute(void); static void amdgpu_illegal_reg_access(); static void amdgpu_illegal_mem_access(); static void amdgpu_deadlock_sdma(void); +static void amdgpu_dispatch_hang_gfx(void); +static void amdgpu_dispatch_hang_compute(void); CU_BOOL suite_deadlock_tests_enable(void) { @@ -188,6 +190,8 @@ CU_TestInfo deadlock_tests[] = { { "sdma ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_sdma }, { "illegal reg access test", amdgpu_illegal_reg_access }, { "illegal mem access test (set amdgpu.vm_fault_stop=2)", amdgpu_illegal_mem_access }, + { "gfx ring bad dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_gfx }, + { "compute ring bad dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_compute }, CU_TEST_INFO_NULL, }; @@ -488,3 +492,13 @@ static void amdgpu_illegal_mem_access() { bad_access_helper(0); } + +static void amdgpu_dispatch_hang_gfx(void) +{ + amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_GFX); +} + +static void amdgpu_dispatch_hang_compute(void) +{ + amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_COMPUTE); +} From patchwork Wed Nov 13 04:58:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Flora Cui X-Patchwork-Id: 11241097 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E426D1747 for ; Wed, 13 Nov 2019 04:58:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB9C022459 for ; Wed, 13 Nov 2019 04:58:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CB9C022459 Authentication-Results: mail.kernel.org; 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Wed, 13 Nov 2019 04:58:37 +0000 From: Flora Cui To: brahma_hybrid_dev@amd.com, dri-devel@lists.freedesktop.org Subject: [PATCH libdrm 2/4] tests/amdgpu: add bad slow dispatch test Date: Wed, 13 Nov 2019 12:58:10 +0800 Message-Id: <20191113045812.24465-2-flora.cui@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191113045812.24465-1-flora.cui@amd.com> References: <20191113045812.24465-1-flora.cui@amd.com> X-ClientProxiedBy: HK0P153CA0042.APCP153.PROD.OUTLOOK.COM (2603:1096:203:17::30) To MN2PR12MB3312.namprd12.prod.outlook.com (2603:10b6:208:ab::23) MIME-Version: 1.0 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [180.167.199.189] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 776cce40-333a-4bf2-8942-08d767f624d9 X-MS-TrafficTypeDiagnostic: MN2PR12MB2928: X-LD-Processed: 3dd8961f-e488-4e60-8e11-a82d994e183d,ExtAddr X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:565; X-Forefront-PRVS: 0220D4B98D X-Forefront-Antispam-Report: SFV:NSPM; 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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HMkkTuG4zdmykn9q4I9EayMYAKK26rS4i36QHevCQBg=; b=mbfMQtZTpd7RMEAwVudaLL7GsqQJ0yo8fUy6UjoYal1bSh93ZGkiHgevrU+cTlsFwroAV2oY7GkAyd675vPmsFA3I0w9wUGDM59f+ROnGOru/89e2OB585VP1/raYnOqPt7tS472llFH4AfAXfBSkOrbF413hwIwz5h4lHvBTrY= X-Mailman-Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Flora.Cui@amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Flora Cui Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" add gfx/compute bad slow dispatch test for gfx9 Signed-off-by: Flora Cui --- tests/amdgpu/amdgpu_test.c | 12 ++ tests/amdgpu/amdgpu_test.h | 1 + tests/amdgpu/basic_tests.c | 229 +++++++++++++++++++++++++++++++++- tests/amdgpu/deadlock_tests.c | 14 +++ 4 files changed, 255 insertions(+), 1 deletion(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 3ac9d8d2..bff90ed6 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -472,6 +472,18 @@ static void amdgpu_disable_suites() "compute ring bad dispatch test (set amdgpu.lockup_timeout=50)", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + /* This test was ran on GFX9 only */ + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + + /* This test was ran on GFX9 only */ + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index 2b01bf41..651e4baf 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -242,6 +242,7 @@ CU_BOOL suite_syncobj_timeline_tests_enable(void); extern CU_TestInfo syncobj_timeline_tests[]; void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip_type); +void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip_type); /** * Helper functions diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 71c9220d..20e949cc 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -312,7 +312,8 @@ static uint32_t shader_bin[] = { enum cs_type { CS_BUFFERCLEAR, CS_BUFFERCOPY, - CS_HANG + CS_HANG, + CS_HANG_SLOW }; static const uint32_t bufferclear_cs_shader_gfx9[] = { @@ -482,6 +483,37 @@ unsigned int memcpy_ps_hang[] = { 0xF800180F, 0x03020100, 0xBF810000 }; +struct amdgpu_test_shader { + uint32_t *shader; + uint32_t header_length; + uint32_t body_length; + uint32_t foot_length; +}; + +unsigned int memcpy_cs_hang_slow_ai_codes[] = { + 0xd1fd0000, 0x04010c08, 0xe00c2000, 0x80000100, + 0xbf8c0f70, 0xe01c2000, 0x80010100, 0xbf810000 +}; + +struct amdgpu_test_shader memcpy_cs_hang_slow_ai = { + memcpy_cs_hang_slow_ai_codes, + 4, + 3, + 1 +}; + +unsigned int memcpy_cs_hang_slow_rv_codes[] = { + 0x8e00860c, 0x32000000, 0xe00c2000, 0x80010100, + 0xbf8c0f70, 0xe01c2000, 0x80020100, 0xbf810000 +}; + +struct amdgpu_test_shader memcpy_cs_hang_slow_rv = { + memcpy_cs_hang_slow_rv_codes, + 4, + 3, + 1 +}; + int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size, unsigned alignment, unsigned heap, uint64_t alloc_flags, uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu, @@ -2183,6 +2215,37 @@ static void amdgpu_sync_dependency_test(void) free(ibs_request.dependencies); } +static int amdgpu_dispatch_load_cs_shader_hang_slow(uint32_t *ptr, int family) +{ + struct amdgpu_test_shader *shader; + int i, loop = 0x10000; + + switch (family) { + case AMDGPU_FAMILY_AI: + shader = &memcpy_cs_hang_slow_ai; + break; + case AMDGPU_FAMILY_RV: + shader = &memcpy_cs_hang_slow_rv; + break; + default: + return -1; + break; + } + + memcpy(ptr, shader->shader, shader->header_length * sizeof(uint32_t)); + + for (i = 0; i < loop; i++) + memcpy(ptr + shader->header_length + shader->body_length * i, + shader->shader + shader->header_length, + shader->body_length * sizeof(uint32_t)); + + memcpy(ptr + shader->header_length + shader->body_length * loop, + shader->shader + shader->header_length + shader->body_length, + shader->foot_length * sizeof(uint32_t)); + + return 0; +} + static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr, int cs_type) { @@ -2635,6 +2698,170 @@ void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip } } +static void amdgpu_memcpy_dispatch_hang_slow_test(amdgpu_device_handle device_handle, + uint32_t ip_type, uint32_t ring) +{ + amdgpu_context_handle context_handle; + amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4]; + volatile unsigned char *ptr_dst; + void *ptr_shader; + unsigned char *ptr_src; + uint32_t *ptr_cmd; + uint64_t mc_address_src, mc_address_dst, mc_address_shader, mc_address_cmd; + amdgpu_va_handle va_src, va_dst, va_shader, va_cmd; + int i, r; + int bo_dst_size = 0x4000000; + int bo_shader_size = 0x400000; + int bo_cmd_size = 4096; + struct amdgpu_cs_request ibs_request = {0}; + struct amdgpu_cs_ib_info ib_info= {0}; + uint32_t hang_state, hangs, expired; + struct amdgpu_gpu_info gpu_info = {0}; + amdgpu_bo_list_handle bo_list; + struct amdgpu_cs_fence fence_status = {0}; + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &bo_cmd, (void **)&ptr_cmd, + &mc_address_cmd, &va_cmd); + CU_ASSERT_EQUAL(r, 0); + memset(ptr_cmd, 0, bo_cmd_size); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_shader, &ptr_shader, + &mc_address_shader, &va_shader); + CU_ASSERT_EQUAL(r, 0); + memset(ptr_shader, 0, bo_shader_size); + + r = amdgpu_dispatch_load_cs_shader_hang_slow(ptr_shader, gpu_info.family_id); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_src, (void **)&ptr_src, + &mc_address_src, &va_src); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_dst, (void **)&ptr_dst, + &mc_address_dst, &va_dst); + CU_ASSERT_EQUAL(r, 0); + + memset(ptr_src, 0x55, bo_dst_size); + + i = 0; + i += amdgpu_dispatch_init(ptr_cmd + i, ip_type); + + /* Issue commands to set cu mask used in current dispatch */ + i += amdgpu_dispatch_write_cumask(ptr_cmd + i); + + /* Writes shader state to HW */ + i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader); + + /* Write constant data */ + /* Writes the texture resource constants data to the SGPRs */ + ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4); + ptr_cmd[i++] = 0x240; + ptr_cmd[i++] = mc_address_src; + ptr_cmd[i++] = (mc_address_src >> 32) | 0x100000; + ptr_cmd[i++] = 0x400000; + ptr_cmd[i++] = 0x74fac; + + /* Writes the UAV constant data to the SGPRs. */ + ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4); + ptr_cmd[i++] = 0x244; + ptr_cmd[i++] = mc_address_dst; + ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000; + ptr_cmd[i++] = 0x400000; + ptr_cmd[i++] = 0x74fac; + + /* dispatch direct command */ + ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3); + ptr_cmd[i++] = 0x10000; + ptr_cmd[i++] = 1; + ptr_cmd[i++] = 1; + ptr_cmd[i++] = 1; + + while (i & 7) + ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */ + + resources[0] = bo_shader; + resources[1] = bo_src; + resources[2] = bo_dst; + resources[3] = bo_cmd; + r = amdgpu_bo_list_create(device_handle, 4, resources, NULL, &bo_list); + CU_ASSERT_EQUAL(r, 0); + + ib_info.ib_mc_address = mc_address_cmd; + ib_info.size = i; + ibs_request.ip_type = ip_type; + ibs_request.ring = ring; + ibs_request.resources = bo_list; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.fence_info.handle = NULL; + r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); + CU_ASSERT_EQUAL(r, 0); + + fence_status.ip_type = ip_type; + fence_status.ip_instance = 0; + fence_status.ring = ring; + fence_status.context = context_handle; + fence_status.fence = ibs_request.seq_no; + + /* wait for IB accomplished */ + r = amdgpu_cs_query_fence_status(&fence_status, + AMDGPU_TIMEOUT_INFINITE, + 0, &expired); + + r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); + + r = amdgpu_bo_list_destroy(bo_list); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_src, va_src, mc_address_src, bo_dst_size); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, bo_shader_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_free(context_handle); + CU_ASSERT_EQUAL(r, 0); +} + +void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip_type) +{ + int r; + struct drm_amdgpu_info_hw_ip info; + uint32_t ring_id; + + r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &info); + CU_ASSERT_EQUAL(r, 0); + if (!info.available_rings) + printf("SKIP ... as there's no ring for ip %d\n", ip_type); + + for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { + amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0); + amdgpu_memcpy_dispatch_hang_slow_test(device_handle, ip_type, ring_id); + amdgpu_memcpy_dispatch_test(device_handle, ip_type, ring_id, 0); + } +} + static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type) { int i; diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index 61342d1a..444e3466 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -116,6 +116,8 @@ static void amdgpu_illegal_mem_access(); static void amdgpu_deadlock_sdma(void); static void amdgpu_dispatch_hang_gfx(void); static void amdgpu_dispatch_hang_compute(void); +static void amdgpu_dispatch_hang_slow_gfx(void); +static void amdgpu_dispatch_hang_slow_compute(void); CU_BOOL suite_deadlock_tests_enable(void) { @@ -192,6 +194,8 @@ CU_TestInfo deadlock_tests[] = { { "illegal mem access test (set amdgpu.vm_fault_stop=2)", amdgpu_illegal_mem_access }, { "gfx ring bad dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_gfx }, { "compute ring bad dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_compute }, + { "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_slow_gfx }, + { "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_slow_compute }, CU_TEST_INFO_NULL, }; @@ -502,3 +506,13 @@ static void amdgpu_dispatch_hang_compute(void) { amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_COMPUTE); } + +static void amdgpu_dispatch_hang_slow_gfx(void) +{ + amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_GFX); +} + +static void amdgpu_dispatch_hang_slow_compute(void) +{ + amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_COMPUTE); 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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TLp58h0eKRTxUAkzRC2XNRQEGu6aW+FI79eT9j0OfXA=; b=TflZHXR63c1R8Huia6VF1CKZbpAzUB2P/dRX7EYWPjnFXANW5uy4JzR8ZTLa5RRVq0f/rcrDTr9TgtZuEm1fFS5oLdjrS8pOdonwcxk+hF9mhxXzzf6KNj8eXDU97I0R5PTaw72GbFPByDOjYUHqsoQm1ZRcIfI3wI3y4QnUwtU= X-Mailman-Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Flora.Cui@amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Flora Cui Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" for gfx9 Signed-off-by: Flora Cui --- tests/amdgpu/amdgpu_test.c | 5 +++++ tests/amdgpu/amdgpu_test.h | 3 ++- tests/amdgpu/basic_tests.c | 41 ++++++++++++++++++++++++----------- tests/amdgpu/deadlock_tests.c | 20 +++++++++++++++++ 4 files changed, 55 insertions(+), 14 deletions(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index bff90ed6..65f5c301 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -484,6 +484,11 @@ static void amdgpu_disable_suites() "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index 651e4baf..6ca54b86 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -243,7 +243,8 @@ extern CU_TestInfo syncobj_timeline_tests[]; void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip_type); void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip_type); - +void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring, + int hang); /** * Helper functions */ diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 20e949cc..e55e6e14 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -362,7 +362,8 @@ static const uint32_t preamblecache_gfx9[] = { enum ps_type { PS_CONST, - PS_TEX + PS_TEX, + PS_HANG }; static const uint32_t ps_const_shader_gfx9[] = { @@ -2887,6 +2888,12 @@ static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type) patchinfo_code_size = ps_tex_shader_patchinfo_code_size_gfx9; patchcode_offset = ps_tex_shader_patchinfo_offset_gfx9; break; + case PS_HANG: + shader = memcpy_ps_hang; + shader_size = sizeof(memcpy_ps_hang); + + memcpy(ptr, shader, shader_size); + return 0; default: return -1; break; @@ -3340,7 +3347,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle, amdgpu_bo_handle bo_shader_vs, uint64_t mc_address_shader_ps, uint64_t mc_address_shader_vs, - uint32_t ring) + uint32_t ring, int hang) { amdgpu_context_handle context_handle; amdgpu_bo_handle bo_dst, bo_src, bo_cmd, resources[5]; @@ -3445,14 +3452,20 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle, r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE, 0, &expired); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); + if (!hang) { + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(expired, true); - /* verify if memcpy test result meets with expected */ - i = 0; - while(i < bo_size) { - CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]); - i++; + /* verify if memcpy test result meets with expected */ + i = 0; + while(i < bo_size) { + CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]); + i++; + } + } else { + r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); } r = amdgpu_bo_list_destroy(bo_list); @@ -3470,7 +3483,8 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle, CU_ASSERT_EQUAL(r, 0); } -static void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring) +void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring, + int hang) { amdgpu_bo_handle bo_shader_ps, bo_shader_vs; void *ptr_shader_ps; @@ -3478,6 +3492,7 @@ static void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t uint64_t mc_address_shader_ps, mc_address_shader_vs; amdgpu_va_handle va_shader_ps, va_shader_vs; int bo_shader_size = 4096; + enum ps_type ps_type = hang ? PS_HANG : PS_TEX; int r; r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096, @@ -3494,14 +3509,14 @@ static void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t CU_ASSERT_EQUAL(r, 0); memset(ptr_shader_vs, 0, bo_shader_size); - r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_TEX); + r = amdgpu_draw_load_ps_shader(ptr_shader_ps, ps_type); CU_ASSERT_EQUAL(r, 0); r = amdgpu_draw_load_vs_shader(ptr_shader_vs); CU_ASSERT_EQUAL(r, 0); amdgpu_memcpy_draw(device_handle, bo_shader_ps, bo_shader_vs, - mc_address_shader_ps, mc_address_shader_vs, ring); + mc_address_shader_ps, mc_address_shader_vs, ring, hang); r = amdgpu_bo_unmap_and_free(bo_shader_ps, va_shader_ps, mc_address_shader_ps, bo_shader_size); CU_ASSERT_EQUAL(r, 0); @@ -3523,7 +3538,7 @@ static void amdgpu_draw_test(void) for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { amdgpu_memset_draw_test(device_handle, ring_id); - amdgpu_memcpy_draw_test(device_handle, ring_id); + amdgpu_memcpy_draw_test(device_handle, ring_id, 0); } } diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index 444e3466..35b10b6a 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -118,6 +118,7 @@ static void amdgpu_dispatch_hang_gfx(void); static void amdgpu_dispatch_hang_compute(void); static void amdgpu_dispatch_hang_slow_gfx(void); static void amdgpu_dispatch_hang_slow_compute(void); +static void amdgpu_draw_hang_gfx(void); CU_BOOL suite_deadlock_tests_enable(void) { @@ -196,6 +197,7 @@ CU_TestInfo deadlock_tests[] = { { "compute ring bad dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_compute }, { "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_slow_gfx }, { "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_slow_compute }, + { "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_gfx }, CU_TEST_INFO_NULL, }; @@ -516,3 +518,21 @@ static void amdgpu_dispatch_hang_slow_compute(void) { amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_COMPUTE); } + +static void amdgpu_draw_hang_gfx(void) +{ + int r; + struct drm_amdgpu_info_hw_ip info; + uint32_t ring_id; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info); + CU_ASSERT_EQUAL(r, 0); + if (!info.available_rings) + printf("SKIP ... as there's no graphic ring\n"); + + for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { + amdgpu_memcpy_draw_test(device_handle, ring_id, 0); + amdgpu_memcpy_draw_test(device_handle, ring_id, 1); + amdgpu_memcpy_draw_test(device_handle, ring_id, 0); + } +} From patchwork Wed Nov 13 04:58:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Flora Cui X-Patchwork-Id: 11241101 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A3FC114ED for ; Wed, 13 Nov 2019 04:58:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B67922459 for ; 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Wed, 13 Nov 2019 04:58:41 +0000 From: Flora Cui To: brahma_hybrid_dev@amd.com, dri-devel@lists.freedesktop.org Subject: [PATCH libdrm 4/4] tests/amdgpu: add gfx ring bad slow draw test Date: Wed, 13 Nov 2019 12:58:12 +0800 Message-Id: <20191113045812.24465-4-flora.cui@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191113045812.24465-1-flora.cui@amd.com> References: <20191113045812.24465-1-flora.cui@amd.com> X-ClientProxiedBy: HK0P153CA0042.APCP153.PROD.OUTLOOK.COM (2603:1096:203:17::30) To MN2PR12MB3312.namprd12.prod.outlook.com (2603:10b6:208:ab::23) MIME-Version: 1.0 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [180.167.199.189] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: cf553c40-df2c-47b3-3b40-08d767f6274d X-MS-TrafficTypeDiagnostic: MN2PR12MB2928: X-LD-Processed: 3dd8961f-e488-4e60-8e11-a82d994e183d,ExtAddr X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:46; 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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VrFpWeIJnNW7hhufoOcFJDpmlJzxHKtoMRQ8hKAfdqA=; b=SCRV7F1iR25wPQG+rnyMsHbjuu6TN4jdWv9PcYO/jAX1S0oPhgOTx6Isc8ZhOBz6APqu+EfqHZNfpTUg5z4e/yn++zz1xYDK13xi7V7GrwMrO6Siaoo5QzBf9CrFDGmtxEJnLyD/yGfghyMm9FDwO5RJ5E1VCmTOfTEYFIM8Oc4= X-Mailman-Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Flora.Cui@amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Flora Cui Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" for gfx9 Signed-off-by: Flora Cui --- tests/amdgpu/amdgpu_test.c | 6 + tests/amdgpu/amdgpu_test.h | 2 + tests/amdgpu/basic_tests.c | 239 ++++++++++++++++++++++++++++++++-- tests/amdgpu/deadlock_tests.c | 18 +++ 4 files changed, 251 insertions(+), 14 deletions(-) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 65f5c301..52c6ae6d 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -489,6 +489,12 @@ static void amdgpu_disable_suites() "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + /* This test was ran on GFX9 only */ + //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) + if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, + "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) + fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); + if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index 6ca54b86..be9297e0 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -245,6 +245,8 @@ void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip_type); void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring, int hang); +void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring); + /** * Helper functions */ diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index e55e6e14..fae96840 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -363,7 +363,8 @@ static const uint32_t preamblecache_gfx9[] = { enum ps_type { PS_CONST, PS_TEX, - PS_HANG + PS_HANG, + PS_HANG_SLOW }; static const uint32_t ps_const_shader_gfx9[] = { @@ -515,6 +516,21 @@ struct amdgpu_test_shader memcpy_cs_hang_slow_rv = { 1 }; +unsigned int memcpy_ps_hang_slow_ai_codes[] = { + 0xbefc000c, 0xbe8e017e, 0xbefe077e, 0xd4080000, + 0xd4090001, 0xd40c0100, 0xd40d0101, 0xf0800f00, + 0x00400002, 0xbefe010e, 0xbf8c0f70, 0xbf800000, + 0xbf800000, 0xbf800000, 0xbf800000, 0xc400180f, + 0x03020100, 0xbf810000 +}; + +struct amdgpu_test_shader memcpy_ps_hang_slow_ai = { + memcpy_ps_hang_slow_ai_codes, + 7, + 2, + 9 +}; + int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size, unsigned alignment, unsigned heap, uint64_t alloc_flags, uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu, @@ -2863,6 +2879,35 @@ void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32 } } +static int amdgpu_draw_load_ps_shader_hang_slow(uint32_t *ptr, int family) +{ + struct amdgpu_test_shader *shader; + int i, loop = 0x40000; + + switch (family) { + case AMDGPU_FAMILY_AI: + case AMDGPU_FAMILY_RV: + shader = &memcpy_ps_hang_slow_ai; + break; + default: + return -1; + break; + } + + memcpy(ptr, shader->shader, shader->header_length * sizeof(uint32_t)); + + for (i = 0; i < loop; i++) + memcpy(ptr + shader->header_length + shader->body_length * i, + shader->shader + shader->header_length, + shader->body_length * sizeof(uint32_t)); + + memcpy(ptr + shader->header_length + shader->body_length * loop, + shader->shader + shader->header_length + shader->body_length, + shader->foot_length * sizeof(uint32_t)); + + return 0; +} + static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type) { int i; @@ -2950,7 +2995,8 @@ static int amdgpu_draw_init(uint32_t *ptr) } static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr, - uint64_t dst_addr) + uint64_t dst_addr, + int hang_slow) { int i = 0; @@ -2975,7 +3021,7 @@ static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr, ptr[i++] = 0x318; ptr[i++] = dst_addr >> 8; ptr[i++] = dst_addr >> 40; - ptr[i++] = 0x7c01f; + ptr[i++] = hang_slow ? 0x1ffc7ff : 0x7c01f; ptr[i++] = 0; ptr[i++] = 0x50438; ptr[i++] = 0x10140000; @@ -2984,7 +3030,7 @@ static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr, /* mmCB_MRT0_EPITCH */ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); ptr[i++] = 0x1e8; - ptr[i++] = 0x1f; + ptr[i++] = hang_slow ? 0x7ff : 0x1f; /* 0xA32B CB_COLOR1_BASE */ ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); @@ -3010,7 +3056,7 @@ static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr, return i; } -static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr) +static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr, int hang_slow) { int i = 0; const uint32_t *cached_cmd_ptr; @@ -3042,6 +3088,8 @@ static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr) cached_cmd_size = sizeof(cached_cmd_gfx9); memcpy(ptr + i, cached_cmd_ptr, cached_cmd_size); + if (hang_slow) + *(ptr + i + 12) = 0x8000800; i += cached_cmd_size/sizeof(uint32_t); return i; @@ -3049,7 +3097,8 @@ static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr) static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr, int ps_type, - uint64_t shader_addr) + uint64_t shader_addr, + int hang_slow) { int i = 0; @@ -3091,8 +3140,8 @@ static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr, ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4); ptr[i++] = 0x4c; i += 2; - ptr[i++] = 0x42000000; - ptr[i++] = 0x42000000; + ptr[i++] = hang_slow ? 0x45000000 : 0x42000000; + ptr[i++] = hang_slow ? 0x45000000 : 0x42000000; ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4); ptr[i++] = 0x50; @@ -3229,11 +3278,11 @@ void amdgpu_memset_draw(amdgpu_device_handle device_handle, i = 0; i += amdgpu_draw_init(ptr_cmd + i); - i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst); + i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 0); - i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i); + i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 0); - i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_vs); + i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_vs, 0); i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_ps); @@ -3392,11 +3441,11 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle, i = 0; i += amdgpu_draw_init(ptr_cmd + i); - i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst); + i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 0); - i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i); + i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 0); - i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_vs); + i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_vs, 0); i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps); @@ -3542,6 +3591,168 @@ static void amdgpu_draw_test(void) } } +void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring) +{ + amdgpu_context_handle context_handle; + amdgpu_bo_handle bo_shader_ps, bo_shader_vs; + amdgpu_bo_handle bo_dst, bo_src, bo_cmd, resources[5]; + void *ptr_shader_ps; + void *ptr_shader_vs; + volatile unsigned char *ptr_dst; + unsigned char *ptr_src; + uint32_t *ptr_cmd; + uint64_t mc_address_dst, mc_address_src, mc_address_cmd; + uint64_t mc_address_shader_ps, mc_address_shader_vs; + amdgpu_va_handle va_shader_ps, va_shader_vs; + amdgpu_va_handle va_dst, va_src, va_cmd; + struct amdgpu_gpu_info gpu_info = {0}; + int i, r; + int bo_size = 0x4000000; + int bo_shader_ps_size = 0x400000; + int bo_shader_vs_size = 4096; + int bo_cmd_size = 4096; + struct amdgpu_cs_request ibs_request = {0}; + struct amdgpu_cs_ib_info ib_info= {0}; + uint32_t hang_state, hangs, expired; + amdgpu_bo_list_handle bo_list; + struct amdgpu_cs_fence fence_status = {0}; + + r = amdgpu_query_gpu_info(device_handle, &gpu_info); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, + &bo_cmd, (void **)&ptr_cmd, + &mc_address_cmd, &va_cmd); + CU_ASSERT_EQUAL(r, 0); + memset(ptr_cmd, 0, bo_cmd_size); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_ps_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_shader_ps, &ptr_shader_ps, + &mc_address_shader_ps, &va_shader_ps); + CU_ASSERT_EQUAL(r, 0); + memset(ptr_shader_ps, 0, bo_shader_ps_size); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_vs_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_shader_vs, &ptr_shader_vs, + &mc_address_shader_vs, &va_shader_vs); + CU_ASSERT_EQUAL(r, 0); + memset(ptr_shader_vs, 0, bo_shader_vs_size); + + r = amdgpu_draw_load_ps_shader_hang_slow(ptr_shader_ps, gpu_info.family_id); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_draw_load_vs_shader(ptr_shader_vs); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_src, (void **)&ptr_src, + &mc_address_src, &va_src); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_dst, (void **)&ptr_dst, + &mc_address_dst, &va_dst); + CU_ASSERT_EQUAL(r, 0); + + memset(ptr_src, 0x55, bo_size); + + i = 0; + i += amdgpu_draw_init(ptr_cmd + i); + + i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 1); + + i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 1); + + i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, + mc_address_shader_vs, 1); + + i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps); + + ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 8); + ptr_cmd[i++] = 0xc; + ptr_cmd[i++] = mc_address_src >> 8; + ptr_cmd[i++] = mc_address_src >> 40 | 0x10e00000; + ptr_cmd[i++] = 0x1ffc7ff; + ptr_cmd[i++] = 0x90500fac; + ptr_cmd[i++] = 0xffe000; + i += 3; + + ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4); + ptr_cmd[i++] = 0x14; + ptr_cmd[i++] = 0x92; + i += 3; + + ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 1); + ptr_cmd[i++] = 0x191; + ptr_cmd[i++] = 0; + + i += amdgpu_draw_draw(ptr_cmd + i); + + while (i & 7) + ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */ + + resources[0] = bo_dst; + resources[1] = bo_src; + resources[2] = bo_shader_ps; + resources[3] = bo_shader_vs; + resources[4] = bo_cmd; + r = amdgpu_bo_list_create(device_handle, 5, resources, NULL, &bo_list); + CU_ASSERT_EQUAL(r, 0); + + ib_info.ib_mc_address = mc_address_cmd; + ib_info.size = i; + ibs_request.ip_type = AMDGPU_HW_IP_GFX; + ibs_request.ring = ring; + ibs_request.resources = bo_list; + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.fence_info.handle = NULL; + r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); + CU_ASSERT_EQUAL(r, 0); + + fence_status.ip_type = AMDGPU_HW_IP_GFX; + fence_status.ip_instance = 0; + fence_status.ring = ring; + fence_status.context = context_handle; + fence_status.fence = ibs_request.seq_no; + + /* wait for IB accomplished */ + r = amdgpu_cs_query_fence_status(&fence_status, + AMDGPU_TIMEOUT_INFINITE, + 0, &expired); + + r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); + + r = amdgpu_bo_list_destroy(bo_list); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_size); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_unmap_and_free(bo_src, va_src, mc_address_src, bo_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_unmap_and_free(bo_shader_ps, va_shader_ps, mc_address_shader_ps, bo_shader_ps_size); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_unmap_and_free(bo_shader_vs, va_shader_vs, mc_address_shader_vs, bo_shader_vs_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_free(context_handle); + CU_ASSERT_EQUAL(r, 0); +} + static void amdgpu_gpu_reset_test(void) { int r; diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c index 35b10b6a..b9dd2d0c 100644 --- a/tests/amdgpu/deadlock_tests.c +++ b/tests/amdgpu/deadlock_tests.c @@ -119,6 +119,7 @@ static void amdgpu_dispatch_hang_compute(void); static void amdgpu_dispatch_hang_slow_gfx(void); static void amdgpu_dispatch_hang_slow_compute(void); static void amdgpu_draw_hang_gfx(void); +static void amdgpu_draw_hang_slow_gfx(void); CU_BOOL suite_deadlock_tests_enable(void) { @@ -198,6 +199,7 @@ CU_TestInfo deadlock_tests[] = { { "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_slow_gfx }, { "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_slow_compute }, { "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_gfx }, + { "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_slow_gfx }, CU_TEST_INFO_NULL, }; @@ -536,3 +538,19 @@ static void amdgpu_draw_hang_gfx(void) amdgpu_memcpy_draw_test(device_handle, ring_id, 0); } } + +static void amdgpu_draw_hang_slow_gfx(void) +{ + struct drm_amdgpu_info_hw_ip info; + uint32_t ring_id; + int r; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info); + CU_ASSERT_EQUAL(r, 0); + + for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { + amdgpu_memcpy_draw_test(device_handle, ring_id, 0); + amdgpu_memcpy_draw_hang_slow_test(device_handle, ring_id); + amdgpu_memcpy_draw_test(device_handle, ring_id, 0); + } +}