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Wang" , Linux Kernel Mailing List , dl-linux-imx , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org According to the RM, the Audio and DMA (ADMA) subsystem is a collection of audio peripherals and some system modules. Add the ADMA specific clock ids to the dt-bindings clock file. Signed-off-by: Shengjiu Wang Signed-off-by: Abel Vesa --- include/dt-bindings/clock/imx8-clock.h | 96 +++++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index 673a8c6..6e0c752 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -131,7 +131,60 @@ #define IMX_ADMA_PWM_CLK 188 #define IMX_ADMA_LCD_CLK 189 -#define IMX_SCU_CLK_END 190 +#define IMX_ADMA_AUD_PLL0 190 +#define IMX_ADMA_AUD_PLL1 191 + +#define IMX_ADMA_AUD_PLL_DIV_CLK0_CLK 192 +#define IMX_ADMA_AUD_PLL_DIV_CLK1_CLK 193 +#define IMX_ADMA_AUD_REC_CLK0_CLK 194 +#define IMX_ADMA_AUD_REC_CLK1_CLK 195 + +/* CM40 SS */ +#define IMX_CM40_IPG_CLK 196 +#define IMX_CM40_I2C_DIV 197 + +#define IMX_SCU_CLK_END 198 + +#define IMX_ADMA_ACM_AUD_CLK0_SEL 0 +#define IMX_ADMA_ACM_AUD_CLK0_CLK 1 +#define IMX_ADMA_ACM_AUD_CLK1_SEL 2 +#define IMX_ADMA_ACM_AUD_CLK1_CLK 3 +#define IMX_ADMA_ACM_MCLKOUT0_SEL 4 +#define IMX_ADMA_ACM_MCLKOUT1_SEL 5 +#define IMX_ADMA_ACM_ESAI0_MCLK_SEL 6 +#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 7 +#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 8 +#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 9 +#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 10 +#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 11 +#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 12 +#define IMX_ADMA_ACM_SAI0_MCLK_SEL 13 +#define IMX_ADMA_ACM_SAI1_MCLK_SEL 14 +#define IMX_ADMA_ACM_SAI2_MCLK_SEL 15 +#define IMX_ADMA_ACM_SAI3_MCLK_SEL 16 +#define IMX_ADMA_ACM_SAI4_MCLK_SEL 17 +#define IMX_ADMA_ACM_SAI5_MCLK_SEL 18 +#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 19 +#define IMX_ADMA_ACM_MQS_TX_CLK_SEL 20 +#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 21 +#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 22 + +#define IMX_ADMA_EXT_AUD_MCLK0 23 +#define IMX_ADMA_EXT_AUD_MCLK1 24 +#define IMX_ADMA_ESAI0_RX_CLK 25 +#define IMX_ADMA_ESAI0_RX_HF_CLK 26 +#define IMX_ADMA_ESAI0_TX_CLK 27 +#define IMX_ADMA_ESAI0_TX_HF_CLK 28 +#define IMX_ADMA_SPDIF0_RX 29 +#define IMX_ADMA_SAI0_RX_BCLK 30 +#define IMX_ADMA_SAI0_TX_BCLK 31 +#define IMX_ADMA_SAI1_RX_BCLK 32 +#define IMX_ADMA_SAI1_TX_BCLK 33 +#define IMX_ADMA_SAI2_RX_BCLK 34 +#define IMX_ADMA_SAI3_RX_BCLK 35 +#define IMX_ADMA_SAI4_RX_BCLK 36 + +#define IMX_ADMA_ACM_CLK_END 37 /* LPCG clocks */ @@ -287,7 +340,46 @@ #define IMX_ADMA_LPCG_DSP_IPG_CLK 42 #define IMX_ADMA_LPCG_DSP_CORE_CLK 43 #define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44 +#define IMX_ADMA_LPCG_AMIX_IPG_CLK 45 +#define IMX_ADMA_LPCG_ESAI_0_IPG_CLK 46 +#define IMX_ADMA_LPCG_ESAI_0_EXTAL_CLK 47 +#define IMX_ADMA_LPCG_SAI_0_IPG_CLK 48 +#define IMX_ADMA_LPCG_SAI_0_MCLK 49 +#define IMX_ADMA_LPCG_SAI_1_IPG_CLK 50 +#define IMX_ADMA_LPCG_SAI_1_MCLK 51 +#define IMX_ADMA_LPCG_SAI_2_IPG_CLK 52 +#define IMX_ADMA_LPCG_SAI_2_MCLK 53 +#define IMX_ADMA_LPCG_SAI_3_IPG_CLK 54 +#define IMX_ADMA_LPCG_SAI_3_MCLK 55 +#define IMX_ADMA_LPCG_SAI_4_IPG_CLK 56 +#define IMX_ADMA_LPCG_SAI_4_MCLK 57 +#define IMX_ADMA_LPCG_SAI_5_IPG_CLK 58 +#define IMX_ADMA_LPCG_SAI_5_MCLK 59 +#define IMX_ADMA_LPCG_MQS_IPG_CLK 60 +#define IMX_ADMA_LPCG_MQS_MCLK 61 +#define IMX_ADMA_LPCG_GPT5_IPG_CLK 62 +#define IMX_ADMA_LPCG_GPT5_CLKIN 63 +#define IMX_ADMA_LPCG_GPT6_IPG_CLK 64 +#define IMX_ADMA_LPCG_GPT6_CLKIN 65 +#define IMX_ADMA_LPCG_GPT7_IPG_CLK 66 +#define IMX_ADMA_LPCG_GPT7_CLKIN 67 +#define IMX_ADMA_LPCG_GPT8_IPG_CLK 68 +#define IMX_ADMA_LPCG_GPT8_CLKIN 69 +#define IMX_ADMA_LPCG_GPT9_IPG_CLK 70 +#define IMX_ADMA_LPCG_GPT9_CLKIN 71 +#define IMX_ADMA_LPCG_GPT10_IPG_CLK 72 +#define IMX_ADMA_LPCG_GPT10_CLKIN 73 +#define IMX_ADMA_LPCG_MCLKOUT0 74 +#define IMX_ADMA_LPCG_MCLKOUT1 75 +#define IMX_ADMA_LPCG_SPDIF_0_TX_CLK 76 +#define IMX_ADMA_LPCG_SPDIF_0_GCLKW 77 +#define IMX_ADMA_LPCG_ASRC_0_IPG_CLK 79 +#define IMX_ADMA_LPCG_ASRC_1_IPG_CLK 80 +#define IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK 81 +#define IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK 82 +#define IMX_ADMA_LPCG_AUD_REC_CLK0_CLK 83 +#define IMX_ADMA_LPCG_AUD_REC_CLK1_CLK 84 -#define IMX_ADMA_LPCG_CLK_END 45 +#define IMX_ADMA_LPCG_CLK_END 85 #endif /* __DT_BINDINGS_CLOCK_IMX_H */ From patchwork Wed Nov 13 12:25:14 2019 Content-Type: text/plain; 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Wang" , Linux Kernel Mailing List , dl-linux-imx , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org According to the RM, the Audio and DMA (ADMA) subsystem is a collection of audio peripherals and some system modules. Register all the ADMA specific clocks through the LPCG and CCM driver. Signed-off-by: Shengjiu Wang Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8qxp-lpcg.c | 42 ++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8qxp.c | 8 ++++++++ 2 files changed, 50 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index c0aff7c..78a9064 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -77,6 +77,48 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = { { IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, }, { IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, }, { IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, }, + + { IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK, "aud_pll_div_clk0_lpcg_clk", "audio_pll_div_clk0_clk", 0, ADMA_PLL_CLK0_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK, "aud_pll_div_clk1_lpcg_clk", "audio_pll_div_clk1_clk", 0, ADMA_PLL_CLK1_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_AUD_REC_CLK0_CLK, "aud_rec_clk0_lpcg_clk", "audio_rec_clk0_clk", 0, ADMA_REC_CLK0_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_AUD_REC_CLK1_CLK, "aud_rec_clk1_lpcg_clk", "audio_rec_clk1_clk", 0, ADMA_REC_CLK1_LPCG, 0, 0, }, + + { IMX_ADMA_LPCG_AMIX_IPG_CLK, "amix_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_AMIX_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_ESAI_0_IPG_CLK, "esai0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_ESAI_0_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_ESAI_0_EXTAL_CLK, "esai0_lpcg_extal_clk", "acm_esai0_mclk_sel", 0, ADMA_ESAI_0_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_SAI_0_IPG_CLK, "sai0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_0_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_SAI_0_MCLK, "sai0_lpcg_mclk", "acm_sai0_mclk_sel", 0, ADMA_SAI_0_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_SAI_1_IPG_CLK, "sai1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_1_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_SAI_1_MCLK, "sai1_lpcg_mclk", "acm_sai1_mclk_sel", 0, ADMA_SAI_1_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_SAI_2_IPG_CLK, "sai2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_2_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_SAI_3_MCLK, "sai2_lpcg_mclk", "acm_sai2_mclk_sel", 0, ADMA_SAI_2_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_SAI_3_IPG_CLK, "sai3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_3_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_SAI_3_MCLK, "sai3_lpcg_mclk", "acm_sai3_mclk_sel", 0, ADMA_SAI_3_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_SAI_4_IPG_CLK, "sai4_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_4_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_SAI_4_MCLK, "sai4_lpcg_mclk", "acm_sai4_mclk_sel", 0, ADMA_SAI_4_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_SAI_5_IPG_CLK, "sai5_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_5_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_SAI_5_MCLK, "sai5_lpcg_mclk", "acm_sai5_mclk_sel", 0, ADMA_SAI_5_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_MQS_IPG_CLK, "mqs_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_MQS_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_MQS_MCLK, "mqs_lpcg_mclk", "acm_mqs_mclk_sel", 0, ADMA_MQS_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_GPT5_IPG_CLK, "gpt5_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_5_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_GPT5_CLKIN, "gpt5_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_5_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_GPT6_IPG_CLK, "gpt6_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_6_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_GPT6_CLKIN, "gpt6_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_6_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_GPT7_IPG_CLK, "gpt7_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_7_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_GPT7_CLKIN, "gpt7_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_7_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_GPT8_IPG_CLK, "gpt8_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_8_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_GPT8_CLKIN, "gpt8_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_8_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_GPT9_IPG_CLK, "gpt9_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_9_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_GPT9_CLKIN, "gpt9_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_9_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_GPT10_IPG_CLK, "gpt10_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_10_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_GPT10_CLKIN, "gpt10_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_10_LPCG, 0, 0, }, + + { IMX_ADMA_LPCG_MCLKOUT0, "mclkout0_lpcg", "acm_mclkout0_sel", 0, ADMA_MCLKOUT0_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_MCLKOUT1, "mclkout1_lpcg", "acm_mclkout1_sel", 0, ADMA_MCLKOUT1_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_SPDIF_0_GCLKW, "spdif0_lpcg_gclkw", "dma_ipg_clk_root", 0, ADMA_SPDIF_0_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_SPDIF_0_TX_CLK, "spdif0_lpcg_tx_clk", "acm_spdif0_mclk_sel", 0, ADMA_SPDIF_0_LPCG, 0, 0, }, + { IMX_ADMA_LPCG_ASRC_0_IPG_CLK, "asrc0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_ASRC_0_LPCG, 16, 0, }, + { IMX_ADMA_LPCG_ASRC_1_IPG_CLK, "asrc1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_ASRC_1_LPCG, 16, 0, }, }; static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = { diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 5e2903e..5e92577 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -94,6 +94,14 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) clks[IMX_ADMA_PWM_CLK] = imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER); clks[IMX_ADMA_LCD_CLK] = imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER); + clks[IMX_ADMA_AUD_PLL0] = imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL); + clks[IMX_ADMA_AUD_PLL1] = imx_clk_scu("audio_pll1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_PLL); + + clks[IMX_ADMA_AUD_PLL_DIV_CLK0_CLK] = imx_clk_scu("audio_pll_div_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC0); + clks[IMX_ADMA_AUD_PLL_DIV_CLK1_CLK] = imx_clk_scu("audio_pll_div_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC0); + clks[IMX_ADMA_AUD_REC_CLK0_CLK] = imx_clk_scu("audio_rec_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC1); + clks[IMX_ADMA_AUD_REC_CLK1_CLK] = imx_clk_scu("audio_rec_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC1); + /* Connectivity */ clks[IMX_CONN_SDHC0_CLK] = imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER); clks[IMX_CONN_SDHC1_CLK] = imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER); From patchwork Wed Nov 13 12:25:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11241811 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E06B013BD for ; Wed, 13 Nov 2019 12:25:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B9F0C2245B for ; Wed, 13 Nov 2019 12:25:53 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Wang" , Linux Kernel Mailing List , dl-linux-imx , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org According to the RM, the Audio Clock Mux (ACM) is a collection of control registers and multiplexers that are used to route the audio source clocks to the audio peripherals. Each audio peripheral has its dedicated audio clock mux (which differ based on usage) and control register. Control of ACM is behind the SCU firmware. ACM depends on SCU PD, so its init level has to be after SCU PD but before the LPCG. The fs_initcall ensures it's probed before LPCG clocks also avoiding unnecessary massive defer probe. Signed-off-by: Shengjiu Wang Signed-off-by: Dong Aisheng Signed-off-by: Abel Vesa --- drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-imx8qxp-acm.c | 189 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 190 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-imx8qxp-acm.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 77a3d71..6186839 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -28,7 +28,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \ obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o -obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o +obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o clk-imx8qxp-acm.o obj-$(CONFIG_SOC_IMX1) += clk-imx1.o obj-$(CONFIG_SOC_IMX21) += clk-imx21.o diff --git a/drivers/clk/imx/clk-imx8qxp-acm.c b/drivers/clk/imx/clk-imx8qxp-acm.c new file mode 100644 index 00000000..7c00fd3 --- /dev/null +++ b/drivers/clk/imx/clk-imx8qxp-acm.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-scu.h" + +#include + +static const char * const aud_clk_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", +}; + +static const char * const mclk_out_sels[] = { + "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "dummy", + "dummy", + "spdif0_rx", + "dummy", + "dummy", + "sai4_rx_bclk", +}; + +static const char * const sai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char * const esai_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char * const spdif_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static const char * const mqs_mclk_sels[] = { + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "acm_aud_clk0_sel", + "acm_aud_clk1_sel", +}; + +static int imx8qxp_acm_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk_onecell_data *clk_data; + struct resource *res; + struct clk **clks; + void __iomem *base; + int num_domains; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap(dev, res->start, resource_size(res)); + if (!base) + return -ENOMEM; + + clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->clks = kcalloc(IMX_ADMA_ACM_CLK_END, + sizeof(*clk_data->clks), GFP_KERNEL); + if (!clk_data->clks) + return -ENOMEM; + + clk_data->clk_num = IMX_ADMA_ACM_CLK_END; + + clks = clk_data->clks; + + num_domains = of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + for (i = 0; i < num_domains; i++) { + struct device *pd_dev; + struct device_link *link; + + pd_dev = dev_pm_domain_attach_by_id(&pdev->dev, i); + if (IS_ERR(pd_dev)) + return PTR_ERR(pd_dev); + + link = device_link_add(&pdev->dev, pd_dev, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (IS_ERR(link)) + return PTR_ERR(link); + } + + clks[IMX_ADMA_EXT_AUD_MCLK0] = imx_clk_fixed("ext_aud_mclk0", 0); + clks[IMX_ADMA_EXT_AUD_MCLK1] = imx_clk_fixed("ext_aud_mclk1", 0); + clks[IMX_ADMA_ESAI0_RX_CLK] = imx_clk_fixed("esai0_rx_clk", 0); + clks[IMX_ADMA_ESAI0_RX_HF_CLK] = imx_clk_fixed("esai0_rx_hf_clk", 0); + clks[IMX_ADMA_ESAI0_TX_CLK] = imx_clk_fixed("esai0_tx_clk", 0); + clks[IMX_ADMA_ESAI0_TX_HF_CLK] = imx_clk_fixed("esai0_tx_hf_clk", 0); + clks[IMX_ADMA_SPDIF0_RX] = imx_clk_fixed("spdif0_rx", 0); + clks[IMX_ADMA_SAI0_RX_BCLK] = imx_clk_fixed("sai0_rx_bclk", 0); + clks[IMX_ADMA_SAI0_TX_BCLK] = imx_clk_fixed("sai0_tx_bclk", 0); + clks[IMX_ADMA_SAI1_RX_BCLK] = imx_clk_fixed("sai1_rx_bclk", 0); + clks[IMX_ADMA_SAI1_TX_BCLK] = imx_clk_fixed("sai1_tx_bclk", 0); + clks[IMX_ADMA_SAI2_RX_BCLK] = imx_clk_fixed("sai2_rx_bclk", 0); + clks[IMX_ADMA_SAI3_RX_BCLK] = imx_clk_fixed("sai3_rx_bclk", 0); + clks[IMX_ADMA_SAI4_RX_BCLK] = imx_clk_fixed("sai4_rx_bclk", 0); + + + clks[IMX_ADMA_ACM_AUD_CLK0_SEL] = imx_clk_mux("acm_aud_clk0_sel", base+0x000000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + clks[IMX_ADMA_ACM_AUD_CLK1_CLK] = imx_clk_mux("acm_aud_clk1_sel", base+0x010000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels)); + + clks[IMX_ADMA_ACM_MCLKOUT0_SEL] = imx_clk_mux("acm_mclkout0_sel", base+0x020000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + clks[IMX_ADMA_ACM_MCLKOUT1_SEL] = imx_clk_mux("acm_mclkout1_sel", base+0x030000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels)); + + clks[IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL] = imx_clk_mux("acm_asrc0_mclk_sel", base+0x040000, 0, 2, NULL, 0); + clks[IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL] = imx_clk_mux("acm_asrc1_mclk_sel", base+0x050000, 0, 2, NULL, 0); + + clks[IMX_ADMA_ACM_ESAI0_MCLK_SEL] = imx_clk_mux("acm_esai0_mclk_sel", base+0x060000, 0, 2, esai_mclk_sels, ARRAY_SIZE(esai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI0_MCLK_SEL] = imx_clk_mux("acm_sai0_mclk_sel", base+0x0E0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI1_MCLK_SEL] = imx_clk_mux("acm_sai1_mclk_sel", base+0x0F0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI2_MCLK_SEL] = imx_clk_mux("acm_sai2_mclk_sel", base+0x100000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI3_MCLK_SEL] = imx_clk_mux("acm_sai3_mclk_sel", base+0x110000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI4_MCLK_SEL] = imx_clk_mux("acm_sai4_mclk_sel", base+0x140000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + clks[IMX_ADMA_ACM_SAI5_MCLK_SEL] = imx_clk_mux("acm_sai5_mclk_sel", base+0x150000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels)); + + clks[IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL] = imx_clk_mux("acm_spdif0_mclk_sel", base+0x1A0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels)); + clks[IMX_ADMA_ACM_MQS_TX_CLK_SEL] = imx_clk_mux("acm_mqs_mclk_sel", base+0x1C0000, 0, 2, mqs_mclk_sels, ARRAY_SIZE(mqs_mclk_sels)); + + for (i = 0; i < clk_data->clk_num; i++) { + if (IS_ERR(clks[i])) + pr_warn("i.MX clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); + } + + return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); +} + +static const struct of_device_id imx8qxp_acm_match[] = { + { .compatible = "nxp,imx8qxp-acm", }, + { /* sentinel */ } +}; + +static struct platform_driver imx8qxp_acm_clk_driver = { + .driver = { + .name = "imx8qxp-acm", + .of_match_table = imx8qxp_acm_match, + .suppress_bind_attrs = true, + }, + .probe = imx8qxp_acm_clk_probe, +}; + +static int __init imx8qxp_acm_init(void) +{ + return platform_driver_register(&imx8qxp_acm_clk_driver); +} +fs_initcall(imx8qxp_acm_init);