From patchwork Thu Nov 14 18:35:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244325 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 62020184C for ; Thu, 14 Nov 2019 18:36:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4294720723 for ; Thu, 14 Nov 2019 18:36:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="JAEX+gBm"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="d6rd8ElG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727065AbfKNSfl (ORCPT ); Thu, 14 Nov 2019 13:35:41 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55686 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726098AbfKNSfk (ORCPT ); Thu, 14 Nov 2019 13:35:40 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 56296613BE; Thu, 14 Nov 2019 18:35:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756539; bh=XquyuQfB91e7bn6lPpm0Lbdv5e0EOYKYUsj1XyHNfvE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JAEX+gBmfI2kLBD7BaLvoY5Et8AbB1BrksNtJOjmKgVLv6cSY53WLfNetVsAYnsT/ TS/q/e3kF2F5jxGZTNwfsI/QxKkulbuTGKnszQBVrk0ZFrAA6XxdHyb7+kK2JZIkbu eNqtzSCmmYpV5qCZ+o272N6RN9RGExOcuxs+PKWY= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7CB0D60FBB; Thu, 14 Nov 2019 18:35:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756535; bh=XquyuQfB91e7bn6lPpm0Lbdv5e0EOYKYUsj1XyHNfvE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d6rd8ElGstGfxVny9JyYXujWx4iS+aDN70IVuiIhJ0MZa/Sc6rkg9ToV9vWvFTxDC 6oOUKjwwe8CxISPNwM4W9ykY924tdf6z80/Rns8NUDAaYY9/CNpZXNPr5+vSBf6gjg Le8j1wCHe2LqrprQx+85AfzF2s8lY3IcXEoQyXJ4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7CB0D60FBB Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 01/12] irqdomain: add bus token DOMAIN_BUS_WAKEUP Date: Thu, 14 Nov 2019 11:35:10 -0700 Message-Id: <1573756521-27373-2-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A single controller can handle normal interrupts and wake-up interrupts independently, with a different numbering space. It is thus crucial to allow the driver for such a controller discriminate between the two. A simple way to do so is to tag the wake-up irqdomain with a "bus token" that indicates the wake-up domain. This slightly abuses the notion of bus, but also radically simplifies the design of such a driver. Between two evils, we choose the least damaging. Suggested-by: Stephen Boyd Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- include/linux/irqdomain.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index 583e7ab..3c340db 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -83,6 +83,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_IPI, DOMAIN_BUS_FSL_MC_MSI, DOMAIN_BUS_TI_SCI_INTA_MSI, + DOMAIN_BUS_WAKEUP, }; /** From patchwork Thu Nov 14 18:35:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244323 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BD3D0109A for ; Thu, 14 Nov 2019 18:36:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9D78320723 for ; Thu, 14 Nov 2019 18:36:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="VB9ejuNK"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="D8chIzwx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727073AbfKNSfl (ORCPT ); Thu, 14 Nov 2019 13:35:41 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55714 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726598AbfKNSfk (ORCPT ); Thu, 14 Nov 2019 13:35:40 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2E6C9613C2; Thu, 14 Nov 2019 18:35:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756540; bh=0/Uz7FcvwScHpeSWK38veIDpYtyw95icYg5VdTw1P70=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VB9ejuNKIzm3jv52T+rd3l7m/JbJzvlFBOGysdN8Ma+AaU4KuEelODOUGDsQOmWSC wYQoNiXXghHtOwGXd6oH/Wgbf+xNLM/CrpVKBmKwhM9H48nG1N0v4FHWPa74e9X1HP WulIAIfNvIVBR8DhEtF+915aMKBYDP+Qsvs3kdoE= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DF5A1611AC; Thu, 14 Nov 2019 18:35:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756537; bh=0/Uz7FcvwScHpeSWK38veIDpYtyw95icYg5VdTw1P70=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D8chIzwxUAPLJ1xk/nYpHjihiXBp2WhJZ7VdUwIop2VO3/DfQvA/dslbC2SzJRj8W zD+HlPJwNhAXpqj9NyxnvqPB2f/RFMZthkXBi5EkiloXMt5Cbh6q4rCMavfNrjBuJ5 l9epsJWy4CQKk8X3ECR/t3a+5Q5CpG6IQGnRfE70= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DF5A1611AC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 02/12] drivers: irqchip: qcom-pdc: update max PDC interrupts Date: Thu, 14 Nov 2019 11:35:11 -0700 Message-Id: <1573756521-27373-3-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Newer SoCs have increased the number of interrupts routed to the PDC interrupt controller. Update the definition of max PDC interrupts. Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- drivers/irqchip/qcom-pdc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index c175333..690cf10 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #include @@ -18,7 +18,7 @@ #include #include -#define PDC_MAX_IRQS 126 +#define PDC_MAX_IRQS 168 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) From patchwork Thu Nov 14 18:35:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244301 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9A5E21390 for ; Thu, 14 Nov 2019 18:35:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 794B420727 for ; Thu, 14 Nov 2019 18:35:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="OXKkcg3W"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="hHWj26L7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727140AbfKNSfn (ORCPT ); Thu, 14 Nov 2019 13:35:43 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55806 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727135AbfKNSfn (ORCPT ); Thu, 14 Nov 2019 13:35:43 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4CE6361204; Thu, 14 Nov 2019 18:35:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756542; bh=R1rxmSTHgqlaRZ55YLFsSuuTMYGKyL4GiFq9O9APVvY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OXKkcg3WJ3ldd3uYoKgFboV316H7F/0c2YWMguXy7pu5OqZ1LnMJGatJekfo7tni8 SP4N7YiA+GBNeqd5ToLG5z2QU28bOZpe8340UihJtIehduPhjN4b2J9UW5sdA9X4m8 FPb8svcC5rTwAbC11Kd7m+FN6mTwoDaoIHznlNrU= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 54C62611AD; Thu, 14 Nov 2019 18:35:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756538; bh=R1rxmSTHgqlaRZ55YLFsSuuTMYGKyL4GiFq9O9APVvY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hHWj26L7rzDueRrR8a//QOmSo5A1TgyC7J1DYlvqY2ZB3qU20U7hPQjLFiBMTpSHF ySmuXFhlk4vknLIDx7TvcmUJyWTcrvSt2ss8XitlCNygU2HU+sVm6b6xIQIpjRm1kX rx/IHklb0+HcOkR9Ba+69BiKPaHnFGi27YgqPxnA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 54C62611AD Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 03/12] drivers: irqchip: pdc: Do not toggle IRQ_ENABLE during mask/unmask Date: Thu, 14 Nov 2019 11:35:12 -0700 Message-Id: <1573756521-27373-4-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When an interrupt is to be serviced, the convention is to mask the interrupt at the chip and unmask after servicing the interrupt. Enabling and disabling the interrupt at the PDC irqchip causes an interrupt storm due to the way dual edge interrupts are handled in hardware. Skip configuring the PDC when the IRQ is masked and unmasked, instead use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE register at the PDC. The PDC's IRQ_ENABLE register is only used during the monitoring mode when the system is asleep and is not needed for active mode detection. Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- drivers/irqchip/qcom-pdc.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 690cf10..527c29e 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -63,15 +63,25 @@ static void pdc_enable_intr(struct irq_data *d, bool on) raw_spin_unlock(&pdc_lock); } -static void qcom_pdc_gic_mask(struct irq_data *d) +static void qcom_pdc_gic_disable(struct irq_data *d) { pdc_enable_intr(d, false); + irq_chip_disable_parent(d); +} + +static void qcom_pdc_gic_enable(struct irq_data *d) +{ + pdc_enable_intr(d, true); + irq_chip_enable_parent(d); +} + +static void qcom_pdc_gic_mask(struct irq_data *d) +{ irq_chip_mask_parent(d); } static void qcom_pdc_gic_unmask(struct irq_data *d) { - pdc_enable_intr(d, true); irq_chip_unmask_parent(d); } @@ -148,6 +158,8 @@ static struct irq_chip qcom_pdc_gic_chip = { .irq_eoi = irq_chip_eoi_parent, .irq_mask = qcom_pdc_gic_mask, .irq_unmask = qcom_pdc_gic_unmask, + .irq_disable = qcom_pdc_gic_disable, + .irq_enable = qcom_pdc_gic_enable, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_set_type = qcom_pdc_gic_set_type, .flags = IRQCHIP_MASK_ON_SUSPEND | From patchwork Thu Nov 14 18:35:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244319 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 53BF01805 for ; Thu, 14 Nov 2019 18:36:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 29F172072C for ; Thu, 14 Nov 2019 18:36:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="M6sT193M"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="M9A7hzIc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727151AbfKNSfp (ORCPT ); Thu, 14 Nov 2019 13:35:45 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55874 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbfKNSfp (ORCPT ); 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Thu, 14 Nov 2019 18:35:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756540; bh=ZmBKYPVW69JmgeBwlmjWI8Od+QSS9E3yj6apmrrzxEM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M9A7hzIclK4tdRy/dLy5PrNc7tLEhWqKQneTDF2S211sJK+u54EgZkGsX4PqOZu6y 8YLLoFEJMiu77dQjl7IKGmLB8ysiVlDyI5bGUCgAulmXbQlQTXzMVQRZ1CPIPmzXos vuH/8Ez7O+IoM8R2KnkpAg8fyLwaMS8Wic9FwsGA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 06154611AC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 04/12] drivers: irqchip: add PDC irqdomain for wakeup capable GPIOs Date: Thu, 14 Nov 2019 11:35:13 -0700 Message-Id: <1573756521-27373-5-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introduce a new domain for wakeup capable GPIOs. The domain can be requested using the bus token DOMAIN_BUS_WAKEUP. In the following patches, we will specify PDC as the wakeup-parent for the TLMM GPIO irqchip. Requesting a wakeup GPIO will setup the GPIO and the corresponding PDC interrupt as its parent. Co-developed-by: Stephen Boyd Signed-off-by: Stephen Boyd Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- Changes in v1: - Include irqdomain.h Changes in RFC v2: - Move irq_domain_qcom_handle_wakeup to the patch where it is used - Replace #define definitons - Add Signed-off-by and other minor changes --- drivers/irqchip/qcom-pdc.c | 104 +++++++++++++++++++++++++++++++++++++++---- include/linux/soc/qcom/irq.h | 21 +++++++++ 2 files changed, 116 insertions(+), 9 deletions(-) create mode 100644 include/linux/soc/qcom/irq.h diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 527c29e..4f2c762 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -13,12 +13,13 @@ #include #include #include +#include #include -#include #include #include #define PDC_MAX_IRQS 168 +#define PDC_MAX_GPIO_IRQS 256 #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) @@ -26,6 +27,8 @@ #define IRQ_ENABLE_BANK 0x10 #define IRQ_i_CFG 0x110 +#define PDC_NO_PARENT_IRQ ~0UL + struct pdc_pin_region { u32 pin_base; u32 parent_base; @@ -65,23 +68,35 @@ static void pdc_enable_intr(struct irq_data *d, bool on) static void qcom_pdc_gic_disable(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + pdc_enable_intr(d, false); irq_chip_disable_parent(d); } static void qcom_pdc_gic_enable(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + pdc_enable_intr(d, true); irq_chip_enable_parent(d); } static void qcom_pdc_gic_mask(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + irq_chip_mask_parent(d); } static void qcom_pdc_gic_unmask(struct irq_data *d) { + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return; + irq_chip_unmask_parent(d); } @@ -124,6 +139,9 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) int pin_out = d->hwirq; enum pdc_irq_config_bits pdc_type; + if (pin_out == GPIO_NO_WAKE_IRQ) + return 0; + switch (type) { case IRQ_TYPE_EDGE_RISING: pdc_type = PDC_EDGE_RISING; @@ -181,8 +199,7 @@ static irq_hw_number_t get_parent_hwirq(int pin) return (region->parent_base + pin - region->pin_base); } - WARN_ON(1); - return ~0UL; + return PDC_NO_PARENT_IRQ; } static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec, @@ -211,17 +228,17 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); if (ret) - return -EINVAL; - - parent_hwirq = get_parent_hwirq(hwirq); - if (parent_hwirq == ~0UL) - return -EINVAL; + return ret; ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &qcom_pdc_gic_chip, NULL); if (ret) return ret; + parent_hwirq = get_parent_hwirq(hwirq); + if (parent_hwirq == PDC_NO_PARENT_IRQ) + return 0; + if (type & IRQ_TYPE_EDGE_BOTH) type = IRQ_TYPE_EDGE_RISING; @@ -244,6 +261,60 @@ static const struct irq_domain_ops qcom_pdc_ops = { .free = irq_domain_free_irqs_common, }; +static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *data) +{ + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq, parent_hwirq; + unsigned int type; + int ret; + + ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &qcom_pdc_gic_chip, NULL); + if (ret) + return ret; + + if (hwirq == GPIO_NO_WAKE_IRQ) + return 0; + + parent_hwirq = get_parent_hwirq(hwirq); + if (parent_hwirq == PDC_NO_PARENT_IRQ) + return 0; + + if (type & IRQ_TYPE_EDGE_BOTH) + type = IRQ_TYPE_EDGE_RISING; + + if (type & IRQ_TYPE_LEVEL_MASK) + type = IRQ_TYPE_LEVEL_HIGH; + + parent_fwspec.fwnode = domain->parent->fwnode; + parent_fwspec.param_count = 3; + parent_fwspec.param[0] = 0; + parent_fwspec.param[1] = parent_hwirq; + parent_fwspec.param[2] = type; + + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, + &parent_fwspec); +} + +static int qcom_pdc_gpio_domain_select(struct irq_domain *d, + struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token) +{ + return bus_token == DOMAIN_BUS_WAKEUP; +} + +static const struct irq_domain_ops qcom_pdc_gpio_ops = { + .select = qcom_pdc_gpio_domain_select, + .alloc = qcom_pdc_gpio_alloc, + .free = irq_domain_free_irqs_common, +}; + static int pdc_setup_pin_mapping(struct device_node *np) { int ret, n; @@ -282,7 +353,7 @@ static int pdc_setup_pin_mapping(struct device_node *np) static int qcom_pdc_init(struct device_node *node, struct device_node *parent) { - struct irq_domain *parent_domain, *pdc_domain; + struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; int ret; pdc_base = of_iomap(node, 0); @@ -313,8 +384,23 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) goto fail; } + pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, + IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, + PDC_MAX_GPIO_IRQS, + of_fwnode_handle(node), + &qcom_pdc_gpio_ops, NULL); + if (!pdc_gpio_domain) { + pr_err("%pOF: PDC domain add failed for GPIO domain\n", node); + ret = -ENOMEM; + goto remove; + } + + irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP); + return 0; +remove: + irq_domain_remove(pdc_domain); fail: kfree(pdc_region); iounmap(pdc_base); diff --git a/include/linux/soc/qcom/irq.h b/include/linux/soc/qcom/irq.h new file mode 100644 index 0000000..637c0bf --- /dev/null +++ b/include/linux/soc/qcom/irq.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __QCOM_IRQ_H +#define __QCOM_IRQ_H + +#include + +#define GPIO_NO_WAKE_IRQ ~0U + +/** + * QCOM specific IRQ domain flags that distinguishes the handling of wakeup + * capable interrupts by different interrupt controllers. + * + * IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP: Line must be masked at TLMM and the + * interrupt configuration is done at PDC + * IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP: Interrupt configuration is handled at TLMM + */ +#define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0) +#define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1) + +#endif From patchwork Thu Nov 14 18:35:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244321 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E80A184E for ; Thu, 14 Nov 2019 18:36:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7DC1920709 for ; Thu, 14 Nov 2019 18:36:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="QDjReYuJ"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="K6G0pOnU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726952AbfKNSgV (ORCPT ); Thu, 14 Nov 2019 13:36:21 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55896 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726852AbfKNSfp (ORCPT ); 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Thu, 14 Nov 2019 18:35:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756541; bh=Xe3y4lO0o+G7wd7o5uty7IuBxQRp8lK4R1EoiDy8RUA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K6G0pOnU+LLlzlxbBo5KXbLCH/r/X7tbVbNBniOYwp3+xJAexZIlv8B6ldEy/uX3b T8ykRXPWFW5KrX4vuKF+vK8yppAp9HUBB4jAehxgFX5QFODGDciaujW6fo0pQF8xM9 XOHVDibsttYHxxMQcaOTRlkA9l/iJhUeiPeLjCGY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5CF31613E4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer , devicetree@vger.kernel.org Subject: [PATCH 05/12] of: irq: document properties for wakeup interrupt parent Date: Thu, 14 Nov 2019 11:35:14 -0700 Message-Id: <1573756521-27373-6-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some interrupt controllers in a SoC, are always powered on and have a select interrupts routed to them, so that they can wakeup the SoC from suspend. Add wakeup-parent DT property to refer to these interrupt controllers. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer Reviewed-by: Rob Herring Reviewed-by: Linus Walleij Reviewed-by: Stephen Boyd --- Changes in v1: - Remove whitespace at end of patch --- .../devicetree/bindings/interrupt-controller/interrupts.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt index 4a3ee25..4ebfa00 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt @@ -108,3 +108,15 @@ commonly used: sensitivity = <7>; }; }; + +3) Interrupt wakeup parent +-------------------------- + +Some interrupt controllers in a SoC, are always powered on and have a select +interrupts routed to them, so that they can wakeup the SoC from suspend. These +interrupt controllers do not fall into the category of a parent interrupt +controller and can be specified by the "wakeup-parent" property and contain a +single phandle referring to the wakeup capable interrupt controller. + + Example: + wakeup-parent = <&pdc_intc>; From patchwork Thu Nov 14 18:35:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244305 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1BC6A109A for ; Thu, 14 Nov 2019 18:35:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E71BB20725 for ; Thu, 14 Nov 2019 18:35:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="MC7sllaq"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="FIOsLReJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726956AbfKNSfu (ORCPT ); Thu, 14 Nov 2019 13:35:50 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:56026 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726977AbfKNSfu (ORCPT ); Thu, 14 Nov 2019 13:35:50 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id AF9E460D62; Thu, 14 Nov 2019 18:35:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756548; bh=HWa3T7WBLldguTdBL77UhjGPppY1kGqNexVz8j95mJo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MC7sllaqTs29s6iwUp7NdjvAhJSCTkYMzZ9eJqiSLOGf7Nn79kZYmxdaH2WcK60BK UY6IhH8uQ0KDMZqzal4k8lOUTGg4vBlCS1KA2IqzA/2G1rTr5JT1mhThJzHnpu6Anv z51cZ0MO6uQYXJXe4kSiTgaFxXE8ZJL+mTJcNuow= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DA55E613B7; Thu, 14 Nov 2019 18:35:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756543; bh=HWa3T7WBLldguTdBL77UhjGPppY1kGqNexVz8j95mJo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FIOsLReJDEVG0gGkMYRICaj9bGp1TBT1gz79A2HdgBuIPTo7kCDHYLJAwlq9HubUu gD4B7guu7Gb+i31UScJ+I4nNg1cR3lTp83ETLnno2iOepi6Jzs7qieJPwviHeuoWJl OqKnISeq03YkZ25rXTYpxctHNNHEJKKCCo38FJ3c= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DA55E613B7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 06/12] genirq: Introduce irq_chip_get/set_parent_state calls Date: Thu, 14 Nov 2019 11:35:15 -0700 Message-Id: <1573756521-27373-7-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Maulik Shah On certain QTI chipsets some GPIOs are direct-connect interrupts to the GIC to be used as regular interrupt lines. When the GPIOs are not used for interrupt generation the interrupt line is disabled. But disabling the interrupt at GIC does not prevent the interrupt to be reported as pending at GIC_ISPEND. Later, when drivers call enable_irq() on the interrupt, an unwanted interrupt occurs. Introduce get and set methods for irqchip's parent to clear it's pending irq state. This then can be invoked by the GPIO interrupt controller on the parents in it hierarchy to clear the interrupt before enabling the interrupt. Signed-off-by: Maulik Shah [updated commit text and minor code fixes] Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- Changes in RFC v2 - - Rephrase commit text - Address code review comments --- include/linux/irq.h | 6 ++++++ kernel/irq/chip.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index fb301cf..7853eb9 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -610,6 +610,12 @@ extern int irq_chip_pm_put(struct irq_data *data); #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY extern void handle_fasteoi_ack_irq(struct irq_desc *desc); extern void handle_fasteoi_mask_irq(struct irq_desc *desc); +extern int irq_chip_set_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool val); +extern int irq_chip_get_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool *state); extern void irq_chip_enable_parent(struct irq_data *data); extern void irq_chip_disable_parent(struct irq_data *data); extern void irq_chip_ack_parent(struct irq_data *data); diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index b76703b..b3fa2d8 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -1298,6 +1298,50 @@ EXPORT_SYMBOL_GPL(handle_fasteoi_mask_irq); #endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */ /** + * irq_chip_set_parent_state - set the state of a parent interrupt. + * + * @data: Pointer to interrupt specific data + * @which: State to be restored (one of IRQCHIP_STATE_*) + * @val: Value corresponding to @which + * + * Conditional success, if the underlying irqchip does not implement it. + */ +int irq_chip_set_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool val) +{ + data = data->parent_data; + + if (!data || !data->chip->irq_set_irqchip_state) + return 0; + + return data->chip->irq_set_irqchip_state(data, which, val); +} +EXPORT_SYMBOL_GPL(irq_chip_set_parent_state); + +/** + * irq_chip_get_parent_state - get the state of a parent interrupt. + * + * @data: Pointer to interrupt specific data + * @which: one of IRQCHIP_STATE_* the caller wants to know + * @state: a pointer to a boolean where the state is to be stored + * + * Conditional success, if the underlying irqchip does not implement it. + */ +int irq_chip_get_parent_state(struct irq_data *data, + enum irqchip_irq_state which, + bool *state) +{ + data = data->parent_data; + + if (!data || !data->chip->irq_get_irqchip_state) + return 0; + + return data->chip->irq_get_irqchip_state(data, which, state); +} +EXPORT_SYMBOL_GPL(irq_chip_get_parent_state); + +/** * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if * NULL) * @data: Pointer to interrupt specific data From patchwork Thu Nov 14 18:35:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244317 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B9801820 for ; Thu, 14 Nov 2019 18:36:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4ADAD2072C for ; Thu, 14 Nov 2019 18:36:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="KwXeerra"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="h7V/ayRF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726977AbfKNSfx (ORCPT ); Thu, 14 Nov 2019 13:35:53 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:56160 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727216AbfKNSfx (ORCPT ); Thu, 14 Nov 2019 13:35:53 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2705F61430; Thu, 14 Nov 2019 18:35:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756552; bh=JALI74oPt0loOZVjDocXpHtFDX27FozLuw7q5iVvea0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KwXeerrawviiOvd6LcrsPvl52Jv5bSNVZ4rg7lSAsUhMbCXpkjlta0pD+kAZOHmli mv2zC5PAk37BOnrajRJazOHtb/lah8hhaDcHEE5onJDjLsq3YJGlh3ESzHQey6MrHa zZMp1AKJaz/e3JjiPI37mGHDCnMHGJUkJ/II6Sn0= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 55AA061421; Thu, 14 Nov 2019 18:35:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756544; bh=JALI74oPt0loOZVjDocXpHtFDX27FozLuw7q5iVvea0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h7V/ayRF86tJ9R3dN7LaKQNVgzb5iDfDQBt+er2IpW2wRZQBHHEMWLkyl2Ve7ccWx DvdWVjzFq0scyaQCRuKbvUJGy9LgzHCYEwiz1+Rb1JLGy1AsJKYFqFpU/7d26IoLve 0iFR8Jl9XOMR0/d5CjXbVdYT51rlXy7Coq9doxno= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 55AA061421 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 07/12] drivers: irqchip: pdc: Add irqchip set/get state calls Date: Thu, 14 Nov 2019 11:35:16 -0700 Message-Id: <1573756521-27373-8-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Maulik Shah Add irqchip calls to set/get interrupt state from the parent interrupt controller. When GPIOs are renabled as interrupt lines, it is desirable to clear the interrupt state at the GIC. This avoids any unwanted interrupt as a result of stale pending state recorded when the line was used as a GPIO. Signed-off-by: Maulik Shah [updated commit text, rearranged code] Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- drivers/irqchip/qcom-pdc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 4f2c762..6ae9e1f 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -50,6 +51,26 @@ static u32 pdc_reg_read(int reg, u32 i) return readl_relaxed(pdc_base + reg + i * sizeof(u32)); } +static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool *state) +{ + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return 0; + + return irq_chip_get_parent_state(d, which, state); +} + +static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool value) +{ + if (d->hwirq == GPIO_NO_WAKE_IRQ) + return 0; + + return irq_chip_set_parent_state(d, which, value); +} + static void pdc_enable_intr(struct irq_data *d, bool on) { int pin_out = d->hwirq; @@ -178,6 +199,8 @@ static struct irq_chip qcom_pdc_gic_chip = { .irq_unmask = qcom_pdc_gic_unmask, .irq_disable = qcom_pdc_gic_disable, .irq_enable = qcom_pdc_gic_enable, + .irq_get_irqchip_state = qcom_pdc_gic_get_irqchip_state, + .irq_set_irqchip_state = qcom_pdc_gic_set_irqchip_state, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_set_type = qcom_pdc_gic_set_type, .flags = IRQCHIP_MASK_ON_SUSPEND | From patchwork Thu Nov 14 18:35:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244313 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C925E13BD for ; Thu, 14 Nov 2019 18:36:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8D0C620709 for ; Thu, 14 Nov 2019 18:36:13 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 14 Nov 2019 18:35:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756546; bh=0LRnMfFLTnJAiH50BqlXIqMQu7Zo1rx9i3nlLGhbtzc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eImowdnkGs6cMMgS+Z9O0Iqw9lnG32xz4ynT44zGI/xIq3P2xLUyDHUUK4h9Mj+87 BBvExZ0s4V9YvyRzOZq7/sdm6gSUcGG6SQRCMMCnjaMX9EKtTC0h2iT3wYSIOFy0cv pUlb3w59TD9ODSMbkTjGb2/1edypcJn7k3IKlvCw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D698761434 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 08/12] drivers: pinctrl: msm: setup GPIO chip in hierarchy Date: Thu, 14 Nov 2019 11:35:17 -0700 Message-Id: <1573756521-27373-9-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some GPIOs are marked as wakeup capable and are routed to another interrupt controller that is an always-domain and can detect interrupts even most of the SoC is powered off. The wakeup interrupt controller wakes up the GIC and replays the interrupt at the GIC. Setup the TLMM irqchip in hierarchy with the wakeup interrupt controller and ensure the wakeup GPIOs are handled correctly. Signed-off-by: Maulik Shah Signed-off-by: Lina Iyer ---- Changes in v1: - Address minor review comments - Remove redundant call to set irq handler - Move irq_domain_qcom_handle_wakeup() to this patch Changes in RFC v2: - Rebase on top of GPIO hierarchy support in linux-next - Set the chained irq handler for summary line Reviewed-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 113 +++++++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm.h | 16 ++++++ include/linux/soc/qcom/irq.h | 13 +++++ 3 files changed, 142 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 763da0b..c245686 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -23,6 +23,8 @@ #include #include +#include + #include "../core.h" #include "../pinconf.h" #include "pinctrl-msm.h" @@ -44,6 +46,7 @@ * @enabled_irqs: Bitmap of currently enabled irqs. * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge * detection. + * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt contrroller * @soc; Reference to soc_data of platform specific data. * @regs: Base addresses for the TLMM tiles. */ @@ -61,6 +64,7 @@ struct msm_pinctrl { DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO); const struct msm_pinctrl_soc_data *soc; void __iomem *regs[MAX_NR_TILES]; @@ -707,6 +711,12 @@ static void msm_gpio_irq_mask(struct irq_data *d) unsigned long flags; u32 val; + if (d->parent_data) + irq_chip_mask_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -751,6 +761,12 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear) unsigned long flags; u32 val; + if (d->parent_data) + irq_chip_unmask_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -778,10 +794,37 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear) static void msm_gpio_irq_enable(struct irq_data *d) { + /* + * Clear the interrupt that may be pending before we enable + * the line. + * This is especially a problem with the GPIOs routed to the + * PDC. These GPIOs are direct-connect interrupts to the GIC. + * Disabling the interrupt line at the PDC does not prevent + * the interrupt from being latched at the GIC. The state at + * GIC needs to be cleared before enabling. + */ + if (d->parent_data) { + irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0); + irq_chip_enable_parent(d); + } msm_gpio_irq_clear_unmask(d, true); } +static void msm_gpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + + if (d->parent_data) + irq_chip_disable_parent(d); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + + msm_gpio_irq_mask(d); +} + static void msm_gpio_irq_unmask(struct irq_data *d) { msm_gpio_irq_clear_unmask(d, false); @@ -795,6 +838,9 @@ static void msm_gpio_irq_ack(struct irq_data *d) unsigned long flags; u32 val; + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -820,6 +866,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) unsigned long flags; u32 val; + if (d->parent_data) + irq_chip_set_type_parent(d, type); + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return 0; + g = &pctrl->soc->groups[d->hwirq]; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -912,6 +964,15 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) struct msm_pinctrl *pctrl = gpiochip_get_data(gc); unsigned long flags; + if (d->parent_data) + irq_chip_set_wake_parent(d, on); + + /* + * While they may not wake up when the TLMM is powered off, + * some GPIOs would like to wakeup the system from suspend + * when TLMM is powered on. To allow that, enable the GPIO + * summary line to be wakeup capable at GIC. + */ raw_spin_lock_irqsave(&pctrl->lock, flags); irq_set_irq_wake(pctrl->irq, on); @@ -990,6 +1051,30 @@ static void msm_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } +static int msm_gpio_wakeirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); + const struct msm_gpio_wakeirq_map *map; + int i; + + *parent = GPIO_NO_WAKE_IRQ; + *parent_type = IRQ_TYPE_EDGE_RISING; + + for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { + map = &pctrl->soc->wakeirq_map[i]; + if (map->gpio == child) { + *parent = map->wakeirq; + break; + } + } + + return 0; +} + static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) { if (pctrl->soc->reserved_gpios) @@ -1004,6 +1089,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) struct gpio_irq_chip *girq; int ret; unsigned ngpio = pctrl->soc->ngpios; + struct device_node *np; if (WARN_ON(ngpio > MAX_NR_GPIO)) return -EINVAL; @@ -1020,17 +1106,44 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.name = "msmgpio"; pctrl->irq_chip.irq_enable = msm_gpio_irq_enable; + pctrl->irq_chip.irq_disable = msm_gpio_irq_disable; pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; + pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent; pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; + np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); + if (np) { + int i; + bool skip; + unsigned int gpio; + + chip->irq.parent_domain = irq_find_matching_host(np, + DOMAIN_BUS_WAKEUP); + of_node_put(np); + if (!chip->irq.parent_domain) + return -EPROBE_DEFER; + chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; + + /* + * Let's skip handling the GPIOs, if the parent irqchip + * handling the direct connect IRQ of the GPIO. + */ + skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); + for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { + gpio = pctrl->soc->wakeirq_map[i].gpio; + set_bit(gpio, pctrl->skip_wake_irqs); + } + } + girq = &chip->irq; girq->chip = &pctrl->irq_chip; girq->parent_handler = msm_gpio_irq_handler; + girq->fwnode = pctrl->dev->fwnode; girq->num_parents = 1; girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), GFP_KERNEL); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 48569cda8..1547020 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -5,6 +5,8 @@ #ifndef __PINCTRL_MSM_H__ #define __PINCTRL_MSM_H__ +#include + struct pinctrl_pin_desc; /** @@ -92,6 +94,16 @@ struct msm_pingroup { }; /** + * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins + * @gpio: The GPIOs that are wakeup capable + * @wakeirq: The interrupt at the always-on interrupt controller + */ +struct msm_gpio_wakeirq_map { + unsigned int gpio; + unsigned int wakeirq; +}; + +/** * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration * @pins: An array describing all pins the pin controller affects. * @npins: The number of entries in @pins. @@ -101,6 +113,8 @@ struct msm_pingroup { * @ngroups: The numbmer of entries in @groups. * @ngpio: The number of pingroups the driver should expose as GPIOs. * @pull_no_keeper: The SoC does not support keeper bias. + * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM + * @nwakeirq_map: The number of entries in @hierarchy_map */ struct msm_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -114,6 +128,8 @@ struct msm_pinctrl_soc_data { const char *const *tiles; unsigned int ntiles; const int *reserved_gpios; + const struct msm_gpio_wakeirq_map *wakeirq_map; + unsigned int nwakeirq_map; }; extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; diff --git a/include/linux/soc/qcom/irq.h b/include/linux/soc/qcom/irq.h index 637c0bf..e01391c 100644 --- a/include/linux/soc/qcom/irq.h +++ b/include/linux/soc/qcom/irq.h @@ -18,4 +18,17 @@ #define IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 0) #define IRQ_DOMAIN_FLAG_QCOM_MPM_WAKEUP (IRQ_DOMAIN_FLAG_NONCORE << 1) +/** + * irq_domain_qcom_handle_wakeup: Return if the domain handles interrupt + * configuration + * @d: irq domain + * + * This QCOM specific irq domain call returns if the interrupt controller + * requires the interrupt be masked at the child interrupt controller. + */ +static inline bool irq_domain_qcom_handle_wakeup(struct irq_domain *d) +{ + return (d->flags & IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP); +} + #endif From patchwork Thu Nov 14 18:35:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244315 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 16CB517E8 for ; Thu, 14 Nov 2019 18:36:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E919120740 for ; Thu, 14 Nov 2019 18:36:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="LBfyAnWM"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="dVTejDTt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727223AbfKNSgO (ORCPT ); Thu, 14 Nov 2019 13:36:14 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:56196 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727237AbfKNSfz (ORCPT ); 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Thu, 14 Nov 2019 18:35:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756547; bh=7Y5bMRJss2Ev4CyRFfq17Trlj1RSHvdmtcSH456kNAo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dVTejDTtoEBoGGGywhNr8uBRvHFHdU6Wk0LOwxOEp76p5RSBTkcfoK9jjlWe21mFG FJw9ZnUVhP2LDF7m154waxQond7rZIpBwfsl/QIgI1euer8/jkwoz536zI/RtN/BCv HcNlY1jMlRoZuv3+Ze+ViMdcLEWKnDMHEpAhIriE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5486F61466 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 09/12] drivers: pinctrl: sdm845: add PDC wakeup interrupt map for GPIOs Date: Thu, 14 Nov 2019 11:35:18 -0700 Message-Id: <1573756521-27373-10-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add interrupt parents for wakeup capable GPIOs for Qualcomm SDM845 SoC. Signed-off-by: Lina Iyer Reviewed-by: Linus Walleij Reviewed-by: Stephen Boyd --- Changes in RFC v2: - Rearranged GPIO wakeup parent map --- drivers/pinctrl/qcom/pinctrl-sdm845.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index ce49597..2834d2c 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ #include @@ -1282,6 +1282,24 @@ static const int sdm845_acpi_reserved_gpios[] = { 0, 1, 2, 3, 81, 82, 83, 84, -1 }; +static const struct msm_gpio_wakeirq_map sdm845_pdc_map[] = { + { 1, 30 }, { 3, 31 }, { 5, 32 }, { 10, 33 }, { 11, 34 }, + { 20, 35 }, { 22, 36 }, { 24, 37 }, { 26, 38 }, { 30, 39 }, + { 31, 117 }, { 32, 41 }, { 34, 42 }, { 36, 43 }, { 37, 44 }, + { 38, 45 }, { 39, 46 }, { 40, 47 }, { 41, 115 }, { 43, 49 }, + { 44, 50 }, { 46, 51 }, { 48, 52 }, { 49, 118 }, { 52, 54 }, + { 53, 55 }, { 54, 56 }, { 56, 57 }, { 57, 58 }, { 58, 59 }, + { 59, 60 }, { 60, 61 }, { 61, 62 }, { 62, 63 }, { 63, 64 }, + { 64, 65 }, { 66, 66 }, { 68, 67 }, { 71, 68 }, { 73, 69 }, + { 77, 70 }, { 78, 71 }, { 79, 72 }, { 80, 73 }, { 84, 74 }, + { 85, 75 }, { 86, 76 }, { 88, 77 }, { 89, 116 }, { 91, 79 }, + { 92, 80 }, { 95, 81 }, { 96, 82 }, { 97, 83 }, { 101, 84 }, + { 103, 85 }, { 104, 86 }, { 115, 90 }, { 116, 91 }, { 117, 92 }, + { 118, 93 }, { 119, 94 }, { 120, 95 }, { 121, 96 }, { 122, 97 }, + { 123, 98 }, { 124, 99 }, { 125, 100 }, { 127, 102 }, { 128, 103 }, + { 129, 104 }, { 130, 105 }, { 132, 106 }, { 133, 107 }, { 145, 108 }, +}; + static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .pins = sdm845_pins, .npins = ARRAY_SIZE(sdm845_pins), @@ -1290,6 +1308,9 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .groups = sdm845_groups, .ngroups = ARRAY_SIZE(sdm845_groups), .ngpios = 151, + .wakeirq_map = sdm845_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sdm845_pdc_map), + }; static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = { From patchwork Thu Nov 14 18:35:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244307 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2A474913 for ; Thu, 14 Nov 2019 18:36:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B58B20731 for ; Thu, 14 Nov 2019 18:36:08 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 14 Nov 2019 18:35:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756548; bh=lyzaaL3HufBnwLI3PVEjtKaYbwKVvY1v+lgNTQKPi+4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SZX+hyqavHR5p0zSsxZl6yDgJVn4a8tZl9UhMlIUkx6Lhqq/kh+31MjBIFDA1+H3X eMaqfHH1D4a7GAzNvDW26Zz8jNkG0p8IecsaYMJNAmf1YY34Et1tC1Gg48vZAlgzUX QRKm4RBnbL8pRNFqm4hrkirFNfa5aNtgR37odsRQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B77566145C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 10/12] arm64: dts: qcom: add PDC interrupt controller for SDM845 Date: Thu, 14 Nov 2019 11:35:19 -0700 Message-Id: <1573756521-27373-11-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add PDC interrupt controller device bindings for SDM845. Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index da8aa59..fb060a4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2939,6 +2939,15 @@ #power-domain-cells = <1>; }; + pdc_intc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>; + qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + pdc_reset: reset-controller@b2e0000 { compatible = "qcom,sdm845-pdc-global"; reg = <0 0x0b2e0000 0 0x20000>; From patchwork Thu Nov 14 18:35:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244311 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6164817E0 for ; Thu, 14 Nov 2019 18:36:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 40B542072E for ; Thu, 14 Nov 2019 18:36:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="PLINxus/"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="gQkCAQeA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727315AbfKNSgA (ORCPT ); Thu, 14 Nov 2019 13:36:00 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:56318 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727241AbfKNSgA (ORCPT ); Thu, 14 Nov 2019 13:36:00 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 388E9611A9; Thu, 14 Nov 2019 18:35:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756559; bh=5rMhQxOWOs0dQWBJGBgaZChmSbMUKsUU5kePCG8JbCc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PLINxus/p0a+ZS1bUD6p143S6bUVCzDsigKH/tZgodzTE7xwUMF8Kh9783Fj6KhWl 2Ew+4CBHeI1fP1+KO2vbjO5fJHCWfVJQAV2eKqFyLeuA89IeWPRXxO+/iE4gNzJC8N U8xsh6Wdae4p51fu8oaF3zNm/xTJ+kUOk6GtVcgA= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 32C6461476; Thu, 14 Nov 2019 18:35:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756550; bh=5rMhQxOWOs0dQWBJGBgaZChmSbMUKsUU5kePCG8JbCc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gQkCAQeAVkfJZqM4DGEipreBKD2oEfv56vMoc9zGAbqQmDuXrkOe+GT0xHEcaY576 tsFAItzX67sLpbC56wAEm3GuXL5ckR/1DcB5TbTINg3TNfODoQNwcz8dvv5oVBs12V DJIuqztlALYbI8zoDO2nmPdz+zxh05OlVSObP878= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 32C6461476 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 11/12] arm64: dts: qcom: setup PDC as the wakeup parent for TLMM on SDM845 Date: Thu, 14 Nov 2019 11:35:20 -0700 Message-Id: <1573756521-27373-12-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PDC always-on interrupt controller can detect certain GPIOs even when the TLMM interrupt controller is powered off. Link the PDC as TLMM's wakeup parent. Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index fb060a4..6d2dfd7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1447,6 +1447,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 150>; + wakeup-parent = <&pdc_intc>; qspi_clk: qspi-clk { pinmux { From patchwork Thu Nov 14 18:35:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 11244309 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 590061390 for ; Thu, 14 Nov 2019 18:36:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 394632072C for ; Thu, 14 Nov 2019 18:36:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="ic4Ycdcv"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="o8mP17dy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727362AbfKNSgH (ORCPT ); Thu, 14 Nov 2019 13:36:07 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:56490 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727223AbfKNSgH (ORCPT ); Thu, 14 Nov 2019 13:36:07 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id C50C96147C; Thu, 14 Nov 2019 18:35:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756565; bh=CNUnNySiEOI8Ft3kUF1s7qMezRd7NbAEq1RYYdi4qE8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ic4YcdcvqBhUL109WwbeqMJRn1WeUuWhpqCBUYvamA1IckRH3Xwcqthb56s6FmEZr dgKvwDs1F7NWMoUaWDfVEX4dhxobM0IFg5besdVSvqHdPp+aZHjfHD71PdJiVccVXh e/jx9IMOS2tIZCPS5SXxXhMeh6zYPxsczItrwFcw= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9A8946145C; Thu, 14 Nov 2019 18:35:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573756551; bh=CNUnNySiEOI8Ft3kUF1s7qMezRd7NbAEq1RYYdi4qE8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o8mP17dyftkPeELm8pJUUdkEjat1b52KkbEBsM298TU+bcXj7Tj/QrulT/qGqGIJD BnC6MfkixLkO4Cr/+2o6KAvZUcicpw2KvZuF4/+HFJ0xhyRfQee/Z4VqRKUOoIfL2e hWLdKhBsB8qQUCO6/ELE0I04xNYnbRtCAp2bxIPc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9A8946145C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: swboyd@chromium.org, maz@kernel.org, linus.walleij@linaro.org, bjorn.andersson@linaro.org Cc: evgreen@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mkshah@codeaurora.org, linux-gpio@vger.kernel.org, agross@kernel.org, dianders@chromium.org, Lina Iyer Subject: [PATCH 12/12] arm64: defconfig: enable PDC interrupt controller for Qualcomm SDM845 Date: Thu, 14 Nov 2019 11:35:21 -0700 Message-Id: <1573756521-27373-13-git-send-email-ilina@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> References: <1573756521-27373-1-git-send-email-ilina@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable PDC interrupt controller for SDM845 devices. The interrupt controller can detect wakeup capable interrupts when the SoC is in a low power state. Signed-off-by: Lina Iyer Reviewed-by: Stephen Boyd --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c9a867a..8d8d4d5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -749,6 +749,7 @@ CONFIG_ARCH_R8A77970=y CONFIG_ARCH_R8A77980=y CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77995=y +CONFIG_QCOM_PDC=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y