From patchwork Fri Nov 15 20:01:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247065 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 625726C1 for ; Fri, 15 Nov 2019 20:02:47 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 44BFA20733 for ; Fri, 15 Nov 2019 20:02:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 44BFA20733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhma-0005Xa-EY; Fri, 15 Nov 2019 20:01:28 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhmZ-0005XV-C4 for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:01:27 +0000 X-Inumbo-ID: b22be5d4-07e2-11ea-adbe-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id b22be5d4-07e2-11ea-adbe-bc764e2007e4; Fri, 15 Nov 2019 20:01:23 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:01:05 -0500 Message-ID: <20191115200115.44890-2-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_10_69 X-Spam-Flag: NO Subject: [Xen-devel] [XEN PATCH v3 01/11] xen: arm: fix indentation of struct vtimer X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Julien Grall , Ian Campbell , Stefano Stabellini , Julien Grall , Volodymyr Babchuk Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Ian Campbell Signed-off-by: Ian Campbell Reviewed-by: Julien Grall [1] Acked-by: Stefano Stabellini [2] [1] https://lists.xenproject.org/archives/html/xen-devel/2015-11/msg00985.html [2] https://lists.xenproject.org/archives/html/xen-devel/2015-12/msg02646.html Acked-by: Julien Grall --- v3: * Rebase (no conflicts) * Add Reviewed-by and Acked-by from a few years ago --- xen/include/asm-arm/domain.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 86ebdd2bcf..f3f3fb7d7f 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -35,11 +35,11 @@ enum domain_type { #define is_domain_direct_mapped(d) ((d) == hardware_domain) struct vtimer { - struct vcpu *v; - int irq; - struct timer timer; - uint32_t ctl; - uint64_t cval; + struct vcpu *v; + int irq; + struct timer timer; + uint32_t ctl; + uint64_t cval; }; struct arch_domain From patchwork Fri Nov 15 20:01:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247069 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B1086C1 for ; Fri, 15 Nov 2019 20:02:48 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 812CF2073A for ; Fri, 15 Nov 2019 20:02:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 812CF2073A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhmf-0005YP-Nf; Fri, 15 Nov 2019 20:01:33 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhme-0005Xr-CH for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:01:32 +0000 X-Inumbo-ID: b2eb62ec-07e2-11ea-adbe-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id b2eb62ec-07e2-11ea-adbe-bc764e2007e4; Fri, 15 Nov 2019 20:01:24 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:01:06 -0500 Message-ID: <20191115200115.44890-3-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_10_69 X-Spam-Flag: NO Subject: [Xen-devel] [XEN PATCH v3 02/11] xen: arm: fix typo in the description of struct pending_irq->desc X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Julien Grall , Ian Campbell , Stefano Stabellini , Julien Grall , Volodymyr Babchuk Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Ian Campbell s/it/if/ makes more sense. Signed-off-by: Ian Campbell Reviewed-by: Julien Grall [1] Acked-by: Stefano Stabellini [2] [1] https://lists.xenproject.org/archives/html/xen-devel/2015-11/msg00986.html [2] https://lists.xenproject.org/archives/html/xen-devel/2015-12/msg02645.html Acked-by: Julien Grall --- v3: * Rebase (no conflicts) * Add Reviewed-by and Acked-by from a few years ago --- xen/include/asm-arm/vgic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 447d24ea59..ce1e3c4bbd 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -77,7 +77,7 @@ struct pending_irq #define GIC_IRQ_GUEST_MIGRATING 4 #define GIC_IRQ_GUEST_PRISTINE_LPI 5 unsigned long status; - struct irq_desc *desc; /* only set it the irq corresponds to a physical irq */ + struct irq_desc *desc; /* only set if the irq corresponds to a physical irq */ unsigned int irq; #define GIC_INVALID_LR (uint8_t)~0 uint8_t lr; From patchwork Fri Nov 15 20:01:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247071 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C7D886C1 for ; Fri, 15 Nov 2019 20:02:53 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ADE2220733 for ; Fri, 15 Nov 2019 20:02:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ADE2220733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhmk-0005Zu-1O; Fri, 15 Nov 2019 20:01:38 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhmj-0005Zg-CW for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:01:37 +0000 X-Inumbo-ID: b3d339d2-07e2-11ea-adbe-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id b3d339d2-07e2-11ea-adbe-bc764e2007e4; Fri, 15 Nov 2019 20:01:25 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:01:07 -0500 Message-ID: <20191115200115.44890-4-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_10_69 X-Spam-Flag: NO Subject: [Xen-devel] [XEN PATCH v3 03/11] xen: arm: Refactor route_irq_to_guest X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Ian Campbell Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Ian Campbell Split out the bit which allocates the struct irqaction and calls __setup_irq into a new function (setup_guest_irq). I'm going to want to call this a second time in a subsequent patch. Note that the action is now allocated and initialised with the desc lock held (since it is taken by the caller). I don't think this is an issue (and avoiding this would make things more complex) Signed-off-by: Ian Campbell Signed-off-by: Stewart Hildebrand --- v2: New patch (maybe, it's been a while...) v3: Rebase + trivial fixups --- Note: I have not given much thought regarding Julien's comment in [1] [1] https://lists.xenproject.org/archives/html/xen-devel/2015-11/msg01041.html --- xen/arch/arm/irq.c | 108 +++++++++++++++++++++++++++------------------ 1 file changed, 64 insertions(+), 44 deletions(-) diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 3877657a52..9cc0a54867 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -407,61 +407,25 @@ bool irq_type_set_by_domain(const struct domain *d) return (d == hardware_domain); } -/* - * Route an IRQ to a specific guest. - * For now only SPIs are assignable to the guest. - */ -int route_irq_to_guest(struct domain *d, unsigned int virq, - unsigned int irq, const char * devname) +static int setup_guest_irq(struct irq_desc *desc, unsigned int virq, + unsigned int irqflags, + struct irq_guest *info, const char *devname) { + const unsigned irq = desc->irq; struct irqaction *action; - struct irq_guest *info; - struct irq_desc *desc; - unsigned long flags; - int retval = 0; - - if ( virq >= vgic_num_irqs(d) ) - { - printk(XENLOG_G_ERR - "the vIRQ number %u is too high for domain %u (max = %u)\n", - irq, d->domain_id, vgic_num_irqs(d)); - return -EINVAL; - } - - /* Only routing to virtual SPIs is supported */ - if ( virq < NR_LOCAL_IRQS ) - { - printk(XENLOG_G_ERR "IRQ can only be routed to an SPI\n"); - return -EINVAL; - } + int retval; + struct domain *d = info->d; - if ( !is_assignable_irq(irq) ) - { - printk(XENLOG_G_ERR "the IRQ%u is not routable\n", irq); - return -EINVAL; - } - desc = irq_to_desc(irq); + ASSERT(spin_is_locked(&desc->lock)); action = xmalloc(struct irqaction); if ( !action ) return -ENOMEM; - info = xmalloc(struct irq_guest); - if ( !info ) - { - xfree(action); - return -ENOMEM; - } - - info->d = d; - info->virq = virq; - action->dev_id = info; action->name = devname; action->free_on_release = 1; - spin_lock_irqsave(&desc->lock, flags); - if ( !irq_type_set_by_domain(d) && desc->arch.type == IRQ_TYPE_INVALID ) { printk(XENLOG_G_ERR "IRQ %u has not been configured\n", irq); @@ -496,6 +460,8 @@ int route_irq_to_guest(struct domain *d, unsigned int virq, d->domain_id, irq, irq_get_guest_info(desc)->virq); retval = -EBUSY; } + else + retval = 0; } else { @@ -509,6 +475,61 @@ int route_irq_to_guest(struct domain *d, unsigned int virq, if ( retval ) goto out; + return 0; + +out: + xfree(action); + return retval; +} + +/* + * Route an IRQ to a specific guest. + * For now only SPIs are assignable to the guest. + */ +int route_irq_to_guest(struct domain *d, unsigned int virq, + unsigned int irq, const char * devname) +{ + struct irq_guest *info; + struct irq_desc *desc; + unsigned long flags; + int retval; + + if ( virq >= vgic_num_irqs(d) ) + { + printk(XENLOG_G_ERR + "the vIRQ number %u is too high for domain %u (max = %u)\n", + irq, d->domain_id, vgic_num_irqs(d)); + return -EINVAL; + } + + /* Only routing to virtual SPIs is supported */ + if ( virq < NR_LOCAL_IRQS ) + { + printk(XENLOG_G_ERR "IRQ can only be routed to an SPI\n"); + return -EINVAL; + } + + if ( !is_assignable_irq(irq) ) + { + printk(XENLOG_G_ERR "the IRQ%u is not routable\n", irq); + return -EINVAL; + } + + desc = irq_to_desc(irq); + + info = xmalloc(struct irq_guest); + if ( !info ) + return -ENOMEM; + + info->d = d; + info->virq = virq; + + spin_lock_irqsave(&desc->lock, flags); + + retval = setup_guest_irq(desc, virq, flags, info, devname); + if ( retval ) + goto out; + retval = gic_route_irq_to_guest(d, virq, desc, GIC_PRI_IRQ); spin_unlock_irqrestore(&desc->lock, flags); @@ -523,7 +544,6 @@ int route_irq_to_guest(struct domain *d, unsigned int virq, out: spin_unlock_irqrestore(&desc->lock, flags); - xfree(action); free_info: xfree(info); From patchwork Fri Nov 15 20:01:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247073 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0C6AB13BD for ; Fri, 15 Nov 2019 20:03:06 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E670220733 for ; Fri, 15 Nov 2019 20:03:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E670220733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhmp-0005bk-BL; Fri, 15 Nov 2019 20:01:43 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhmo-0005bM-CW for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:01:42 +0000 X-Inumbo-ID: b4c74a40-07e2-11ea-adbe-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id b4c74a40-07e2-11ea-adbe-bc764e2007e4; Fri, 15 Nov 2019 20:01:28 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:01:08 -0500 Message-ID: <20191115200115.44890-5-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_0_4 X-Spam-Flag: NO Subject: [Xen-devel] [XEN PATCH v3 04/11] xen: arm: remove is_assignable_irq X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" It only had 1 caller. Reverse the condition for readability. Signed-off-by: Stewart Hildebrand --- v3: new patch --- xen/arch/arm/irq.c | 9 ++------- xen/include/asm-arm/irq.h | 2 -- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 9cc0a54867..c80782026f 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -390,12 +390,6 @@ err: return rc; } -bool is_assignable_irq(unsigned int irq) -{ - /* For now, we can only route SPIs to the guest */ - return (irq >= NR_LOCAL_IRQS) && (irq < gic_number_lines()); -} - /* * Only the hardware domain is allowed to set the configure the * interrupt type for now. @@ -509,7 +503,8 @@ int route_irq_to_guest(struct domain *d, unsigned int virq, return -EINVAL; } - if ( !is_assignable_irq(irq) ) + /* For now, we can only route SPIs to the guest */ + if ( (irq < NR_LOCAL_IRQS) || (irq >= gic_number_lines()) ) { printk(XENLOG_G_ERR "the IRQ%u is not routable\n", irq); return -EINVAL; diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index e45d574598..e14001b5c6 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -70,8 +70,6 @@ static inline bool is_lpi(unsigned int irq) #define domain_pirq_to_irq(d, pirq) (pirq) -bool is_assignable_irq(unsigned int irq); - void init_IRQ(void); void init_secondary_IRQ(void); From patchwork Fri Nov 15 20:10:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247081 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 247126C1 for ; Fri, 15 Nov 2019 20:12:11 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F30C4206D9 for ; Fri, 15 Nov 2019 20:12:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F30C4206D9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhvc-0006tI-FT; Fri, 15 Nov 2019 20:10:48 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhvb-0006tD-1m for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:10:47 +0000 X-Inumbo-ID: 0052a7a6-07e4-11ea-b678-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 0052a7a6-07e4-11ea-b678-bc764e2007e4; Fri, 15 Nov 2019 20:10:45 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:10:31 -0500 Message-ID: <20191115201037.44982-1-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_10_69 X-Spam-Flag: NO Subject: [Xen-devel] [XEN PATCH v3 05/11] xen: arm: add interfaces to save/restore the state of a PPI. X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Ian Campbell Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Ian Campbell Make use of the GICD I[SC]ACTIVER registers to save and restore the active state of the interrupt. For edge triggered interrupts we also need to context switch the pending bit via I[SC]PENDR. Note that for level triggered interrupts SPENDR sets a latch which is only cleared by ICPENDR (and not by h/w state changes), therefore we do not want to context switch the pending state for level PPIs -- instead we rely on the context switch of the peripheral to restore the correct level. Unused as yet, will be used by the vtimer code shortly. Signed-off-by: Ian Campbell Signed-off-by: Stewart Hildebrand --- v3: Address feedback from v2 [1]: * Add a comment to explain that PPI are always below 31. * Use uint32_t for pendingr, activer, enabler * Fixup register names in gic-v3.c * Add newlines for clarity * Make gicv3_irq_enable/disable declarations static * Use readl_relaxed (not readl_gicd) in gic-v3.c * Add note to comment explaining devices using PPI being quiet during save/restore. Suggested by Julien. * Test on QEMU's model of GICv3 Note: I have not given any thought to the comments in [2] regarding disabling IRQ or enable/disable state. [1] https://lists.xenproject.org/archives/html/xen-devel/2015-11/msg01049.html [2] https://lists.xenproject.org/archives/html/xen-devel/2015-11/msg01051.html --- xen/arch/arm/gic-v2.c | 69 ++++++++++++++++++++++++++++++++++++ xen/arch/arm/gic-v3.c | 69 ++++++++++++++++++++++++++++++++++++ xen/arch/arm/gic.c | 54 ++++++++++++++++++++++++++++ xen/arch/arm/irq.c | 7 ++++ xen/include/asm-arm/domain.h | 11 ++++++ xen/include/asm-arm/gic.h | 22 ++++++++++++ xen/include/asm-arm/irq.h | 2 ++ 7 files changed, 234 insertions(+) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 256988c665..13f106cb61 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -123,6 +123,9 @@ static DEFINE_PER_CPU(u8, gic_cpu_id); /* Maximum cpu interface per GIC */ #define NR_GIC_CPU_IF 8 +static void gicv2_irq_enable(struct irq_desc *desc); +static void gicv2_irq_disable(struct irq_desc *desc); + static inline void writeb_gicd(uint8_t val, unsigned int offset) { writeb_relaxed(val, gicv2.map_dbase + offset); @@ -191,6 +194,38 @@ static void gicv2_save_state(struct vcpu *v) writel_gich(0, GICH_HCR); } +static void gicv2_save_and_mask_hwppi(struct irq_desc *desc, + struct hwppi_state *s) +{ + const uint32_t mask = (1u << desc->irq); /* PPIs are IRQ# 16-31 */ + const uint32_t pendingr = readl_gicd(GICD_ISPENDR); + const uint32_t activer = readl_gicd(GICD_ISACTIVER); + const uint32_t enabler = readl_gicd(GICD_ISENABLER); + const bool is_edge = !!(desc->arch.type & DT_IRQ_TYPE_EDGE_BOTH); + + s->active = !!(activer & mask); + s->enabled = !!(enabler & mask); + s->pending = !!(pendingr & mask); + + /* Write a 1 to IC...R to clear the corresponding bit of state */ + if ( s->active ) + writel_gicd(mask, GICD_ICACTIVER); + + /* + * For an edge interrupt clear the pending state, for a level interrupt + * this clears the latch there is no need since saving the peripheral state + * (and/or restoring the next VCPU) will cause the correct action. + */ + if ( is_edge && s->pending ) + writel_gicd(mask, GICD_ICPENDR); + + if ( s->enabled ) + gicv2_irq_disable(desc); + + ASSERT(!(readl_gicd(GICD_ISACTIVER) & mask)); + ASSERT(!(readl_gicd(GICD_ISENABLER) & mask)); +} + static void gicv2_restore_state(const struct vcpu *v) { int i; @@ -203,6 +238,38 @@ static void gicv2_restore_state(const struct vcpu *v) writel_gich(GICH_HCR_EN, GICH_HCR); } +static void gicv2_restore_hwppi(struct irq_desc *desc, + const struct hwppi_state *s) +{ + const uint32_t mask = (1u << desc->irq); /* PPIs are IRQ# 16-31 */ + const bool is_edge = !!(desc->arch.type & DT_IRQ_TYPE_EDGE_BOTH); + + /* + * The IRQ must always have been set inactive and masked etc by + * the saving of the previous state via save_and_mask_hwppi. + */ + ASSERT(!(readl_gicd(GICD_ISACTIVER) & mask)); + ASSERT(!(readl_gicd(GICD_ISENABLER) & mask)); + + if ( s->active ) + writel_gicd(mask, GICD_ICACTIVER); + + /* + * Restore pending state for edge triggered interrupts only. For + * level triggered interrupts the level will be restored as + * necessary by restoring the state of the relevant peripheral. + * + * For a level triggered interrupt ISPENDR acts as a *latch* which + * is only cleared by ICPENDR (i.e. the input level is no longer + * relevant). We certainly do not want that here. + */ + if ( is_edge && s->pending ) + writel_gicd(mask, GICD_ISPENDR); + + if ( s->enabled ) + gicv2_irq_enable(desc); +} + static void gicv2_dump_state(const struct vcpu *v) { int i; @@ -1335,7 +1402,9 @@ const static struct gic_hw_operations gicv2_ops = { .init = gicv2_init, .secondary_init = gicv2_secondary_cpu_init, .save_state = gicv2_save_state, + .save_and_mask_hwppi = gicv2_save_and_mask_hwppi, .restore_state = gicv2_restore_state, + .restore_hwppi = gicv2_restore_hwppi, .dump_state = gicv2_dump_state, .gic_host_irq_type = &gicv2_host_irq_type, .gic_guest_irq_type = &gicv2_guest_irq_type, diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 0f6cbf6224..be5ea61ab5 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -63,6 +63,9 @@ static DEFINE_PER_CPU(void __iomem*, rbase); #define GICD_RDIST_BASE (this_cpu(rbase)) #define GICD_RDIST_SGI_BASE (GICD_RDIST_BASE + SZ_64K) +static void gicv3_irq_enable(struct irq_desc *desc); +static void gicv3_irq_disable(struct irq_desc *desc); + /* * Saves all 16(Max) LR registers. Though number of LRs implemented * is implementation specific. @@ -375,6 +378,38 @@ static void gicv3_save_state(struct vcpu *v) v->arch.gic.v3.sre_el1 = READ_SYSREG32(ICC_SRE_EL1); } +static void gicv3_save_and_mask_hwppi(struct irq_desc *desc, + struct hwppi_state *s) +{ + const uint32_t mask = (1u << desc->irq); /* PPIs are IRQ# 16-31 */ + const uint32_t pendingr = readl_relaxed(GICD_RDIST_SGI_BASE + GICR_ISPENDR0); + const uint32_t activer = readl_relaxed(GICD_RDIST_SGI_BASE + GICR_ISACTIVER0); + const uint32_t enabler = readl_relaxed(GICD_RDIST_SGI_BASE + GICR_ISENABLER0); + const bool is_edge = !!(desc->arch.type & DT_IRQ_TYPE_EDGE_BOTH); + + s->active = !!(activer & mask); + s->enabled = !!(enabler & mask); + s->pending = !!(pendingr & mask); + + /* Write a 1 to IC...R to clear the corresponding bit of state */ + if ( s->active ) + writel_relaxed(mask, GICD_RDIST_SGI_BASE + GICR_ICACTIVER0); + + /* + * For an edge interrupt clear the pending state, for a level interrupt + * this clears the latch there is no need since saving the peripheral state + * (and/or restoring the next VCPU) will cause the correct action. + */ + if ( is_edge && s->pending ) + writel_relaxed(mask, GICD_RDIST_SGI_BASE + GICR_ICPENDR0); + + if ( s->enabled ) + gicv3_irq_disable(desc); + + ASSERT(!(readl_relaxed(GICD_RDIST_SGI_BASE + GICR_ISACTIVER0) & mask)); + ASSERT(!(readl_relaxed(GICD_RDIST_SGI_BASE + GICR_ISENABLER0) & mask)); +} + static void gicv3_restore_state(const struct vcpu *v) { uint32_t val; @@ -410,6 +445,38 @@ static void gicv3_restore_state(const struct vcpu *v) dsb(sy); } +static void gicv3_restore_hwppi(struct irq_desc *desc, + const struct hwppi_state *s) +{ + const uint32_t mask = (1u << desc->irq); /* PPIs are IRQ# 16-31 */ + const bool is_edge = !!(desc->arch.type & DT_IRQ_TYPE_EDGE_BOTH); + + /* + * The IRQ must always have been set inactive and masked etc by + * the saving of the previous state via save_and_mask_hwppi. + */ + ASSERT(!(readl_relaxed(GICD_RDIST_SGI_BASE + GICR_ISACTIVER0) & mask)); + ASSERT(!(readl_relaxed(GICD_RDIST_SGI_BASE + GICR_ISENABLER0) & mask)); + + if ( s->active ) + writel_relaxed(mask, GICD_RDIST_SGI_BASE + GICR_ICACTIVER0); + + /* + * Restore pending state for edge triggered interrupts only. For + * level triggered interrupts the level will be restored as + * necessary by restoring the state of the relevant peripheral. + * + * For a level triggered interrupt ISPENDR acts as a *latch* which + * is only cleared by ICPENDR (i.e. the input level is no longer + * relevant). We certainly do not want that here. + */ + if ( is_edge && s->pending ) + writel_relaxed(mask, GICD_RDIST_SGI_BASE + GICR_ISPENDR0); + + if ( s->enabled ) + gicv3_irq_enable(desc); +} + static void gicv3_dump_state(const struct vcpu *v) { int i; @@ -1835,7 +1902,9 @@ static const struct gic_hw_operations gicv3_ops = { .info = &gicv3_info, .init = gicv3_init, .save_state = gicv3_save_state, + .save_and_mask_hwppi = gicv3_save_and_mask_hwppi, .restore_state = gicv3_restore_state, + .restore_hwppi = gicv3_restore_hwppi, .dump_state = gicv3_dump_state, .gic_host_irq_type = &gicv3_host_irq_type, .gic_guest_irq_type = &gicv3_guest_irq_type, diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 113655a789..75921724dd 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -64,6 +64,17 @@ unsigned int gic_number_lines(void) return gic_hw_ops->info->nr_lines; } +void gic_hwppi_state_init(struct hwppi_state *s, unsigned irq) +{ + memset(s, 0, sizeof(*s)); + s->irq = irq; +} + +void gic_hwppi_set_pending(struct hwppi_state *s) +{ + s->pending = true; +} + void gic_save_state(struct vcpu *v) { ASSERT(!local_irq_is_enabled()); @@ -78,6 +89,25 @@ void gic_save_state(struct vcpu *v) isb(); } +void gic_save_and_mask_hwppi(struct vcpu *v, const unsigned virq, + struct hwppi_state *s) +{ + struct pending_irq *p = irq_to_pending(v, virq); + struct irq_desc *desc = p->desc; + + spin_lock(&desc->lock); + + ASSERT(virq >= 16 && virq < 32); + ASSERT(desc->irq >= 16 && desc->irq < 32); + ASSERT(!is_idle_vcpu(v)); + + s->inprogress = test_and_clear_bit(_IRQ_INPROGRESS, &desc->status); + + gic_hw_ops->save_and_mask_hwppi(desc, s); + + spin_unlock(&desc->lock); +} + void gic_restore_state(struct vcpu *v) { ASSERT(!local_irq_is_enabled()); @@ -89,6 +119,30 @@ void gic_restore_state(struct vcpu *v) isb(); } +void gic_restore_hwppi(struct vcpu *v, + const unsigned virq, + const struct hwppi_state *s) +{ + struct pending_irq *p = irq_to_pending(v, virq); + struct irq_desc *desc = irq_to_desc(s->irq); + + spin_lock(&desc->lock); + + ASSERT(virq >= 16 && virq < 32); + ASSERT(!is_idle_vcpu(v)); + + p->desc = desc; /* Migrate to new physical processor */ + + irq_set_virq(desc, virq); + + gic_hw_ops->restore_hwppi(desc, s); + + if ( s->inprogress ) + set_bit(_IRQ_INPROGRESS, &desc->status); + + spin_unlock(&desc->lock); +} + /* desc->irq needs to be disabled before calling this function */ void gic_set_irq_type(struct irq_desc *desc, unsigned int type) { diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index c80782026f..1a8e599c2e 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -150,6 +150,13 @@ static inline struct irq_guest *irq_get_guest_info(struct irq_desc *desc) return desc->action->dev_id; } +void irq_set_virq(struct irq_desc *desc, unsigned virq) +{ + struct irq_guest *info = irq_get_guest_info(desc); + ASSERT(test_bit(_IRQ_PER_CPU, &desc->status)); + info->virq = virq; +} + static inline struct domain *irq_get_domain(struct irq_desc *desc) { return irq_get_guest_info(desc)->d; diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index f3f3fb7d7f..c3f4cd5069 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -34,6 +34,17 @@ enum domain_type { /* The hardware domain has always its memory direct mapped. */ #define is_domain_direct_mapped(d) ((d) == hardware_domain) +struct hwppi_state { + /* h/w state */ + unsigned irq; + unsigned long enabled:1; + unsigned long pending:1; + unsigned long active:1; + + /* Xen s/w state */ + unsigned long inprogress:1; +}; + struct vtimer { struct vcpu *v; int irq; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 793d324b33..1164e0c7a6 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -275,6 +275,26 @@ extern int gicv_setup(struct domain *d); extern void gic_save_state(struct vcpu *v); extern void gic_restore_state(struct vcpu *v); +/* + * Save/restore the state of a single PPI which must be routed to + * (that is, is defined to be injected to the current + * vcpu). + * + * We expect the device which use this PPI to be quiet while we + * save/restore. + * + * For instance we want to disable the timer before saving the state. + * Otherwise we will mess up the state. + */ +struct hwppi_state; +extern void gic_hwppi_state_init(struct hwppi_state *s, unsigned irq); +extern void gic_hwppi_set_pending(struct hwppi_state *s); +extern void gic_save_and_mask_hwppi(struct vcpu *v, unsigned irq, + struct hwppi_state *s); +extern void gic_restore_hwppi(struct vcpu *v, + const unsigned virq, + const struct hwppi_state *s); + /* SGI (AKA IPIs) */ enum gic_sgi { GIC_SGI_EVENT_CHECK = 0, @@ -325,8 +345,10 @@ struct gic_hw_operations { int (*init)(void); /* Save GIC registers */ void (*save_state)(struct vcpu *); + void (*save_and_mask_hwppi)(struct irq_desc *desc, struct hwppi_state *s); /* Restore GIC registers */ void (*restore_state)(const struct vcpu *); + void (*restore_hwppi)(struct irq_desc *desc, const struct hwppi_state *s); /* Dump GIC LR register information */ void (*dump_state)(const struct vcpu *); diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index e14001b5c6..3b37a21c06 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -96,6 +96,8 @@ void irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_mask); */ bool irq_type_set_by_domain(const struct domain *d); +void irq_set_virq(struct irq_desc *desc, unsigned virq); + #endif /* _ASM_HW_IRQ_H */ /* * Local variables: From patchwork Fri Nov 15 20:10:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247079 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F2E0138C for ; Fri, 15 Nov 2019 20:12:10 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E863C206D9 for ; Fri, 15 Nov 2019 20:12:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E863C206D9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhvh-0006th-O0; Fri, 15 Nov 2019 20:10:53 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhvf-0006tS-WF for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:10:52 +0000 X-Inumbo-ID: 02c57bc6-07e4-11ea-b678-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 02c57bc6-07e4-11ea-b678-bc764e2007e4; Fri, 15 Nov 2019 20:10:47 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:10:32 -0500 Message-ID: <20191115201037.44982-2-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_0_4 X-Spam-Flag: NO Subject: [Xen-devel] [XEN PATCH v3 06/11] Add NR_SGIS and NR_PPIS definitions to irq.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" These will be used in a follow-up patch. Signed-off-by: Stewart Hildebrand --- v3: new patch --- xen/include/asm-arm/irq.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index 3b37a21c06..367fe6269c 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -33,7 +33,9 @@ struct arch_irq_desc { unsigned int type; }; -#define NR_LOCAL_IRQS 32 +#define NR_SGIS 16 +#define NR_PPIS 16 +#define NR_LOCAL_IRQS (NR_SGIS + NR_PPIS) /* * This only covers the interrupts that Xen cares about, so SGIs, PPIs and From patchwork Fri Nov 15 20:10:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247083 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 590DC159A for ; Fri, 15 Nov 2019 20:12:11 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FCA0206D9 for ; Fri, 15 Nov 2019 20:12:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3FCA0206D9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhvm-0006un-1L; Fri, 15 Nov 2019 20:10:58 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhvl-0006uQ-0S for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:10:57 +0000 X-Inumbo-ID: 035e0738-07e4-11ea-b678-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 035e0738-07e4-11ea-b678-bc764e2007e4; Fri, 15 Nov 2019 20:10:48 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:10:33 -0500 Message-ID: <20191115201037.44982-3-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_0_4 X-Spam-Flag: NO Subject: [Xen-devel] [XEN PATCH v3 07/11] xen: arm: vgic: allow delivery of PPIs to guests X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Allow vgic_get_hw_irq_desc to be called with a vcpu argument. Use vcpu argument in vgic_connect_hw_irq. vgic_connect_hw_irq is called for PPIs and SPIs, not SGIs. Enforce with ASSERTs. Signed-off-by: Stewart Hildebrand --- v3: new patch --- Note: I have only modified the old vgic to allow delivery of PPIs. --- xen/arch/arm/gic-vgic.c | 24 ++++++++++++++++-------- xen/arch/arm/vgic.c | 6 +++--- 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 98c021f1a8..2c66a8fa92 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -418,7 +418,7 @@ struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, { struct pending_irq *p; - ASSERT(!v && virq >= 32); + ASSERT((!v && (virq >= 32)) || (!d && v && (virq >= 16) && (virq < 32))); if ( !v ) v = d->vcpu[0]; @@ -434,15 +434,23 @@ int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, struct irq_desc *desc, bool connect) { unsigned long flags; - /* - * Use vcpu0 to retrieve the pending_irq struct. Given that we only - * route SPIs to guests, it doesn't make any difference. - */ - struct vcpu *v_target = vgic_get_target_vcpu(d->vcpu[0], virq); - struct vgic_irq_rank *rank = vgic_rank_irq(v_target, virq); - struct pending_irq *p = irq_to_pending(v_target, virq); + struct vcpu *v_target; + struct vgic_irq_rank *rank; + struct pending_irq *p; int ret = 0; + if (v) + v_target = v; + else + /* Use vcpu0 to retrieve the pending_irq struct. */ + v_target = vgic_get_target_vcpu(d->vcpu[0], virq); + + rank = vgic_rank_irq(v_target, virq); + p = irq_to_pending(v_target, virq); + + ASSERT(virq >= NR_SGIS); + ASSERT(p->irq >= NR_SGIS); + /* "desc" is optional when we disconnect an IRQ. */ ASSERT(!connect || desc); diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 82f524a35c..c3933c2687 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -410,10 +410,10 @@ void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) irq_set_affinity(p->desc, cpumask_of(v_target->processor)); spin_lock_irqsave(&p->desc->lock, flags); /* - * The irq cannot be a PPI, we only support delivery of SPIs - * to guests. + * The irq cannot be a SGI, we only support delivery of SPIs + * and PPIs to guests. */ - ASSERT(irq >= 32); + ASSERT(irq >= NR_SGIS); if ( irq_type_set_by_domain(d) ) gic_set_irq_type(p->desc, vgic_get_virq_type(v, n, i)); p->desc->handler->enable(p->desc); From patchwork Fri Nov 15 20:10:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247085 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED1376C1 for ; Fri, 15 Nov 2019 20:12:11 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D3EAA206D9 for ; Fri, 15 Nov 2019 20:12:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D3EAA206D9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhvr-0006xA-AX; Fri, 15 Nov 2019 20:11:03 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhvq-0006wp-0L for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:11:02 +0000 X-Inumbo-ID: 0417c844-07e4-11ea-b678-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 0417c844-07e4-11ea-b678-bc764e2007e4; Fri, 15 Nov 2019 20:10:49 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:10:34 -0500 Message-ID: <20191115201037.44982-4-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_0_4 X-Spam-Flag: NO Subject: [Xen-devel] [RFC XEN PATCH v3 08/11] xen: arm: vgic: don't fail if IRQ is already connected X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" There are some IRQs that happen to have multiple "interrupts = < ... >;" properties with the same IRQ in the device tree. For example: interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; In this case it seems that we are invoking vgic_connect_hw_irq multiple times for the same IRQ. Rework the checks to allow booting in this scenario. I have not seen any cases where the pre-existing p->desc is any different from the new desc, so BUG() out if they're different for now. Signed-off-by: Stewart Hildebrand --- v3: new patch I tested on Xilinx Zynq UltraScale+ with the old vGIC. I have not fully tested with CONFIG_NEW_VGIC. This hack only became necessary after introducing the PPI series, and I'm not entirely sure what the reason is for that. I'm also unsure if BUG()ing out is the right thing to do in case of desc != p->desc, or what conditions would even trigger this? Is this function exposed to guests? --- xen/arch/arm/gic-vgic.c | 9 +++++++-- xen/arch/arm/vgic/vgic.c | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 2c66a8fa92..5c16e66b32 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -460,9 +460,14 @@ int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, if ( connect ) { /* The VIRQ should not be already enabled by the guest */ - if ( !p->desc && - !test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + if ( !test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + { + if (p->desc && p->desc != desc) + { + BUG(); + } p->desc = desc; + } else ret = -EBUSY; } diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index f0f2ea5021..aa775f7668 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -882,6 +882,10 @@ int vgic_connect_hw_irq(struct domain *d, struct vcpu *vcpu, irq->hw = true; irq->hwintid = desc->irq; } + else if ( irq->hw && !irq->enabled && irq->hwintid == desc->irq ) + { + /* The IRQ was already connected. No action is necessary. */ + } else ret = -EBUSY; } From patchwork Fri Nov 15 20:10:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247087 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8DA856C1 for ; Fri, 15 Nov 2019 20:12:18 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 68C402073A for ; Fri, 15 Nov 2019 20:12:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 68C402073A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhvw-0006zA-KR; Fri, 15 Nov 2019 20:11:08 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhvv-0006yc-0h for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:11:07 +0000 X-Inumbo-ID: 04d86d92-07e4-11ea-b678-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 04d86d92-07e4-11ea-b678-bc764e2007e4; Fri, 15 Nov 2019 20:10:51 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:10:35 -0500 Message-ID: <20191115201037.44982-5-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_10_69 X-Spam-Flag: NO Subject: [Xen-devel] [XEN PATCH v3 09/11] xen: arm: gic: supporting routing a PPI to the current vcpu. X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Ian Campbell Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Ian Campbell That is whichever vcpu is resident when the interrupt fires. An interrupt is in this state when both IRQ_GUEST and IRQ_PER_CPU are set in the descriptor status. Only PPIs can be in this mode. This requires some peripheral specific code to make use of the previously introduced functionality to save and restore the PPI state. The vtimer driver will do so shortly. Signed-off-by: Ian Campbell Signed-off-by: Stewart Hildebrand --- v3: * Change calls to gic_set_irq_properties() to gic_set_irq_type() and gic_set_irq_priority() due to following commits: 16580cde5a xen/arm: gic: Do not configure affinity during routing 23e8118b8e xen/arm: gic: split set_irq_properties * Partially address feedback from v2 [1]: * Clarify a comment. * Switch loglevel back to XENLOG_G_ERR and bump a parameter to the next line to comply with line length coding style. * Call vgic_get_hw_irq_desc from gic_save_and_mask_hwppi * Call vgic_connect_hw_irq from gic_restore_hwppi --- Note: I have not yet addressed feedback from [1] regarding differentiating between CPU0/CPU1 in the error message. I also have not yet given much thought to Julien's comment in [1] "Why do you set the parameter virq to irq?" I hope to investigate further if time allows, but if anyone has any input I'd like to hear it. [1] https://lists.xenproject.org/archives/html/xen-devel/2015-11/msg01064.html --- xen/arch/arm/gic.c | 33 ++++++++++++++-- xen/arch/arm/irq.c | 80 +++++++++++++++++++++++++++++++++++---- xen/include/asm-arm/gic.h | 2 + xen/include/asm-arm/irq.h | 1 + 4 files changed, 104 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 75921724dd..982afaadbd 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -92,8 +92,7 @@ void gic_save_state(struct vcpu *v) void gic_save_and_mask_hwppi(struct vcpu *v, const unsigned virq, struct hwppi_state *s) { - struct pending_irq *p = irq_to_pending(v, virq); - struct irq_desc *desc = p->desc; + struct irq_desc *desc = vgic_get_hw_irq_desc(NULL, v, virq); spin_lock(&desc->lock); @@ -123,7 +122,6 @@ void gic_restore_hwppi(struct vcpu *v, const unsigned virq, const struct hwppi_state *s) { - struct pending_irq *p = irq_to_pending(v, virq); struct irq_desc *desc = irq_to_desc(s->irq); spin_lock(&desc->lock); @@ -131,7 +129,8 @@ void gic_restore_hwppi(struct vcpu *v, ASSERT(virq >= 16 && virq < 32); ASSERT(!is_idle_vcpu(v)); - p->desc = desc; /* Migrate to new physical processor */ + /* Migrate to new physical processor */ + vgic_connect_hw_irq(v->domain, v, virq, desc, true); irq_set_virq(desc, virq); @@ -178,6 +177,32 @@ void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) gic_set_irq_priority(desc, priority); } +/* + * Program the GIC to route an interrupt to the current guest. + * + * That is, the IRQ is delivered to whichever VCPU happens to be + * resident on the PCPU when the interrupt arrives. + * + * Currently the interrupt *must* be a PPI and the code responsible + * for the related hardware must save and restore the PPI with + * gic_save_and_mask_hwppi/gic_restore_hwppi. + */ +int gic_route_irq_to_current_guest(struct irq_desc *desc, + unsigned int priority) +{ + ASSERT(spin_is_locked(&desc->lock)); + ASSERT(desc->irq >= 16 && desc->irq < 32); + + desc->handler = gic_hw_ops->gic_guest_irq_type; + set_bit(_IRQ_GUEST, &desc->status); + set_bit(_IRQ_PER_CPU, &desc->status); + + gic_set_irq_type(desc, desc->arch.type); + gic_set_irq_priority(desc, GIC_PRI_IRQ); + + return 0; +} + /* Program the GIC to route an interrupt to a guest * - desc.lock must be held */ diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 1a8e599c2e..17dec64203 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -236,6 +236,7 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int is_fiq) if ( test_bit(_IRQ_GUEST, &desc->status) ) { struct irq_guest *info = irq_get_guest_info(desc); + struct vcpu *v; perfc_incr(guest_irqs); desc->handler->end(desc); @@ -243,10 +244,15 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int is_fiq) set_bit(_IRQ_INPROGRESS, &desc->status); /* - * The irq cannot be a PPI, we only support delivery of SPIs to - * guests. + * A PPI exposed to a guest must always be in IRQ_GUEST|IRQ_PER_CPU + * mode ("route to active VCPU"), so we use current. + * + * For SPI, we use NULL. In this case, vgic_inject_irq() will look up + * the required target for delivery to a specific guest. */ - vgic_inject_irq(info->d, NULL, info->virq, true); + v = test_bit(_IRQ_PER_CPU, &desc->status) ? current : NULL; + vgic_inject_irq(info->d, v, info->virq, true); + goto out_no_end; } @@ -362,11 +368,15 @@ int setup_irq(unsigned int irq, unsigned int irqflags, struct irqaction *new) if ( test_bit(_IRQ_GUEST, &desc->status) ) { - struct domain *d = irq_get_domain(desc); + struct irq_guest *info = irq_get_guest_info(desc); spin_unlock_irqrestore(&desc->lock, flags); - printk(XENLOG_ERR "ERROR: IRQ %u is already in use by the domain %u\n", - irq, d->domain_id); + if ( !test_bit(_IRQ_PER_CPU, &desc->status) ) + printk(XENLOG_ERR "ERROR: IRQ %u is already in use by domain %u\n", + irq, info->d->domain_id); + else + printk(XENLOG_ERR + "ERROR: IRQ %u is already in use by \n", irq); return -EBUSY; } @@ -450,8 +460,14 @@ static int setup_guest_irq(struct irq_desc *desc, unsigned int virq, if ( d != ad ) { - printk(XENLOG_G_ERR "IRQ %u is already used by domain %u\n", - irq, ad->domain_id); + if ( !test_bit(_IRQ_PER_CPU, &desc->status) ) + printk(XENLOG_G_ERR + "ERROR: IRQ %u is already used by domain %u\n", + irq, ad->domain_id); + else + printk(XENLOG_G_ERR + "ERROR: IRQ %u is already used by \n", + irq); retval = -EBUSY; } else if ( irq_get_guest_info(desc)->virq != virq ) @@ -552,6 +568,54 @@ free_info: return retval; } +/* + * Route a PPI such that it is always delivered to the current vcpu on + * the pcpu. The driver for the peripheral must use + * gic_{save_and_mask,restore}_hwppi as part of the context switch. + */ +int route_hwppi_to_current_vcpu(unsigned int irq, const char *devname) +{ + struct irq_guest *info; + struct irq_desc *desc; + unsigned long flags; + int retval = 0; + + /* Can only route PPIs to current VCPU */ + if ( irq < 16 || irq >= 32 ) + return -EINVAL; + + desc = irq_to_desc(irq); + + info = xmalloc(struct irq_guest); + if ( !info ) + return -ENOMEM; + + info->d = NULL; /* Routed to current vcpu, so no specific domain */ + /* info->virq is set by gic_restore_hwppi. */ + + spin_lock_irqsave(&desc->lock, flags); + + retval = setup_guest_irq(desc, irq, flags, info, devname); + if ( retval ) + { + xfree(info); + return retval; + } + + retval = gic_route_irq_to_current_guest(desc, GIC_PRI_IRQ); + + spin_unlock_irqrestore(&desc->lock, flags); + + if ( retval ) + { + release_irq(desc->irq, info); + xfree(info); + return retval; + } + + return 0; +} + int release_guest_irq(struct domain *d, unsigned int virq) { struct irq_desc *desc; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 1164e0c7a6..6a0910e13e 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -244,6 +244,8 @@ extern void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority); extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, struct irq_desc *desc, unsigned int priority); +int gic_route_irq_to_current_guest(struct irq_desc *desc, + unsigned int priority); /* Remove an IRQ passthrough to a guest */ int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index 367fe6269c..c51265180b 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -77,6 +77,7 @@ void init_secondary_IRQ(void); int route_irq_to_guest(struct domain *d, unsigned int virq, unsigned int irq, const char *devname); +int route_hwppi_to_current_vcpu(unsigned int irq, const char *devname); int release_guest_irq(struct domain *d, unsigned int irq); void arch_move_irqs(struct vcpu *v); From patchwork Fri Nov 15 20:14:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247097 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF3386C1 for ; Fri, 15 Nov 2019 20:15:36 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C2DAE206D9 for ; Fri, 15 Nov 2019 20:15:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C2DAE206D9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhyy-0007SY-Ag; Fri, 15 Nov 2019 20:14:16 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhyx-0007ST-G5 for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:14:15 +0000 X-Inumbo-ID: 7d850246-07e4-11ea-adbe-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 7d850246-07e4-11ea-adbe-bc764e2007e4; Fri, 15 Nov 2019 20:14:14 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:14:06 -0500 Message-ID: <20191115201407.45042-1-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_10_69 X-Spam-Flag: NO Subject: [Xen-devel] [RFC XEN PATCH v3 10/11] xen: arm: context switch vtimer PPI state. X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Ian Campbell Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Ian Campbell ... instead of artificially masking the timer interrupt in the timer state and relying on the guest to unmask (which it isn't required to do per the h/w spec, although Linux does). By using the newly added hwppi save/restore functionality we make use of the GICD I[SC]ACTIVER registers to save and restore the active state of the interrupt, which prevents the nested invocations which the current masking works around. Signed-off-by: Ian Campbell Signed-off-by: Stewart Hildebrand --- v2: Rebased, in particular over Julien's passthrough stuff which reworked a bunch of IRQ related stuff. Also largely rewritten since precursor patches now lay very different groundwork. v3: Address feedback from v2 [1]: * Remove virt_timer_irqs performance counter since it is now unused. * Add caveat to comment about not using I*ACTIVER register. * HACK: don't initialize pending_irq->irq in vtimer for new vGIC to allows us to build with CONFIG_NEW_VGIC=y [1] https://lists.xenproject.org/archives/html/xen-devel/2015-11/msg01065.html --- Note: Regarding Stefano's comment in [2], I did test it with the call to gic_hwppi_set_pending removed, and I was able to boot dom0. [2] https://lists.xenproject.org/archives/html/xen-devel/2015-12/msg02683.html --- xen/arch/arm/time.c | 26 ++---------------- xen/arch/arm/vtimer.c | 45 +++++++++++++++++++++++++++++--- xen/include/asm-arm/domain.h | 1 + xen/include/asm-arm/perfc_defn.h | 1 - 4 files changed, 44 insertions(+), 29 deletions(-) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index 739bcf186c..e3a23b8e16 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -243,28 +243,6 @@ static void timer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) } } -static void vtimer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) -{ - /* - * Edge-triggered interrupts can be used for the virtual timer. Even - * if the timer output signal is masked in the context switch, the - * GIC will keep track that of any interrupts raised while IRQS are - * disabled. As soon as IRQs are re-enabled, the virtual interrupt - * will be injected to Xen. - * - * If an IDLE vCPU was scheduled next then we should ignore the - * interrupt. - */ - if ( unlikely(is_idle_vcpu(current)) ) - return; - - perfc_incr(virt_timer_irqs); - - current->arch.virt_timer.ctl = READ_SYSREG32(CNTV_CTL_EL0); - WRITE_SYSREG32(current->arch.virt_timer.ctl | CNTx_CTL_MASK, CNTV_CTL_EL0); - vgic_inject_irq(current->domain, current, current->arch.virt_timer.irq, true); -} - /* * Arch timer interrupt really ought to be level triggered, since the * design of the timer/comparator mechanism is based around that @@ -304,8 +282,8 @@ void init_timer_interrupt(void) request_irq(timer_irq[TIMER_HYP_PPI], 0, timer_interrupt, "hyptimer", NULL); - request_irq(timer_irq[TIMER_VIRT_PPI], 0, vtimer_interrupt, - "virtimer", NULL); + route_hwppi_to_current_vcpu(timer_irq[TIMER_VIRT_PPI], "virtimer"); + request_irq(timer_irq[TIMER_PHYS_NONSECURE_PPI], 0, timer_interrupt, "phytimer", NULL); diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index e6aebdac9e..6e3498952d 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -55,9 +55,19 @@ static void phys_timer_expired(void *data) static void virt_timer_expired(void *data) { struct vtimer *t = data; - t->ctl |= CNTx_CTL_MASK; - vgic_inject_irq(t->v->domain, t->v, t->irq, true); - perfc_incr(vtimer_virt_inject); + t->ctl |= CNTx_CTL_PENDING; + if ( !(t->ctl & CNTx_CTL_MASK) ) + { + /* + * An edge triggered interrupt should now be pending. Since + * this timer can never expire while the domain is scheduled + * we know that the gic_restore_hwppi in virt_timer_restore + * will cause the real hwppi to occur and be routed. + */ + gic_hwppi_set_pending(&t->ppi_state); + vcpu_unblock(t->v); + perfc_incr(vtimer_virt_inject); + } } int domain_vtimer_init(struct domain *d, struct xen_arch_domainconfig *config) @@ -98,9 +108,14 @@ int domain_vtimer_init(struct domain *d, struct xen_arch_domainconfig *config) int vcpu_vtimer_init(struct vcpu *v) { +#ifndef CONFIG_NEW_VGIC + struct pending_irq *p; +#endif struct vtimer *t = &v->arch.phys_timer; bool d0 = is_hardware_domain(v->domain); + const unsigned host_vtimer_irq_ppi = timer_get_irq(TIMER_VIRT_PPI); + /* * Hardware domain uses the hardware interrupts, guests get the virtual * platform. @@ -118,10 +133,18 @@ int vcpu_vtimer_init(struct vcpu *v) init_timer(&t->timer, virt_timer_expired, t, v->processor); t->ctl = 0; t->irq = d0 - ? timer_get_irq(TIMER_VIRT_PPI) + ? host_vtimer_irq_ppi : GUEST_TIMER_VIRT_PPI; t->v = v; +#ifndef CONFIG_NEW_VGIC + p = irq_to_pending(v, t->irq); + p->irq = t->irq; +#endif + + gic_hwppi_state_init(&v->arch.virt_timer.ppi_state, + host_vtimer_irq_ppi); + v->arch.vtimer_initialized = 1; return 0; @@ -149,6 +172,16 @@ void virt_timer_save(struct vcpu *v) set_timer(&v->arch.virt_timer.timer, ticks_to_ns(v->arch.virt_timer.cval + v->domain->arch.virt_timer_base.offset - boot_count)); } + + /* + * Since the vtimer irq is a PPI we don't need to worry about + * racing against it becoming active while we are saving the + * state, since that requires the guest to be reading the IAR, + * as long as the guest is not using I*ACTIVER register which we + * don't yet implement. + */ + gic_save_and_mask_hwppi(v, v->arch.virt_timer.irq, + &v->arch.virt_timer.ppi_state); } void virt_timer_restore(struct vcpu *v) @@ -162,6 +195,10 @@ void virt_timer_restore(struct vcpu *v) WRITE_SYSREG64(v->domain->arch.virt_timer_base.offset, CNTVOFF_EL2); WRITE_SYSREG64(v->arch.virt_timer.cval, CNTV_CVAL_EL0); WRITE_SYSREG32(v->arch.virt_timer.ctl, CNTV_CTL_EL0); + + gic_restore_hwppi(v, + v->arch.virt_timer.irq, + &v->arch.virt_timer.ppi_state); } static bool vtimer_cntp_ctl(struct cpu_user_regs *regs, uint32_t *r, bool read) diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index c3f4cd5069..b8fe142960 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -51,6 +51,7 @@ struct vtimer { struct timer timer; uint32_t ctl; uint64_t cval; + struct hwppi_state ppi_state; }; struct arch_domain diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_defn.h index 6a83185163..198dd4eadb 100644 --- a/xen/include/asm-arm/perfc_defn.h +++ b/xen/include/asm-arm/perfc_defn.h @@ -70,7 +70,6 @@ PERFCOUNTER(guest_irqs, "#GUEST-IRQS") PERFCOUNTER(hyp_timer_irqs, "Hypervisor timer interrupts") PERFCOUNTER(phys_timer_irqs, "Physical timer interrupts") -PERFCOUNTER(virt_timer_irqs, "Virtual timer interrupts") PERFCOUNTER(maintenance_irqs, "Maintenance interrupts") PERFCOUNTER(atomics_guest, "atomics: guest access") From patchwork Fri Nov 15 20:14:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 11247095 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C177F930 for ; Fri, 15 Nov 2019 20:15:28 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A792F206D9 for ; Fri, 15 Nov 2019 20:15:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A792F206D9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dornerworks.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhz3-0007TC-K8; Fri, 15 Nov 2019 20:14:21 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iVhz2-0007T3-ES for xen-devel@lists.xenproject.org; Fri, 15 Nov 2019 20:14:20 +0000 X-Inumbo-ID: 7eff7278-07e4-11ea-adbe-bc764e2007e4 Received: from webmail.dornerworks.com (unknown [12.207.209.150]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 7eff7278-07e4-11ea-adbe-bc764e2007e4; Fri, 15 Nov 2019 20:14:16 +0000 (UTC) From: Stewart Hildebrand To: Date: Fri, 15 Nov 2019 15:14:07 -0500 Message-ID: <20191115201407.45042-2-stewart.hildebrand@dornerworks.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> References: <20191115200115.44890-1-stewart.hildebrand@dornerworks.com> MIME-Version: 1.0 X-Originating-IP: [172.27.14.58] X-ClientProxiedBy: Mcbain.dw.local (172.27.1.45) To Mcbain.dw.local (172.27.1.45) X-spam-status: No, score=-2.9 required=3.5 tests=ALL_TRUSTED, BAYES_00, MAILSHELL_SCORE_0_4 X-Spam-Flag: NO Subject: [Xen-devel] [HACK XEN PATCH v3 11/11] HACK: Force virt timer to PPI0 (IRQ16) X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Ian Campbell Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Ian Campbell Just for testing so the guest vtimer ppi it isn't the same as the physical virt timer PPI on my platform, and therefore allows to exercise the non-1:1 bits of the code. --- xen/include/public/arch-arm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index c365b1b39e..e7ab984a3b 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -451,7 +451,7 @@ typedef uint64_t xen_callback_t; #define GUEST_MAX_VCPUS 128 /* Interrupts */ -#define GUEST_TIMER_VIRT_PPI 27 +#define GUEST_TIMER_VIRT_PPI 16 #define GUEST_TIMER_PHYS_S_PPI 29 #define GUEST_TIMER_PHYS_NS_PPI 30 #define GUEST_EVTCHN_PPI 31