From patchwork Sun Nov 17 14:07:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11248417 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ADDD714ED for ; Sun, 17 Nov 2019 14:07:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 840CF20871 for ; Sun, 17 Nov 2019 14:07:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="EVVkWJcF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726244AbfKQOHp (ORCPT ); Sun, 17 Nov 2019 09:07:45 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:35423 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726237AbfKQOHp (ORCPT ); Sun, 17 Nov 2019 09:07:45 -0500 Received: by mail-wr1-f68.google.com with SMTP id s5so16399724wrw.2; Sun, 17 Nov 2019 06:07:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tiyYxTb8Rk/mH72C96BXIjZ0994JQE265VRKbdZ6Y4s=; b=EVVkWJcFjAUrdne3BkCeB4MZ1JQmeLwk168bJwNqsL7WjU+GOUeD6/qGmmqltNv+pb +gB2wG9KbzlzWwFQb6WRV5ac1d950G8wG6UGLncopSi6JOof9v6RfpFc0wxZH4iTi3pG 1Y32KlJ11z3OQLFduc78NnjwMiekx/m50BD56AMK3tNx+wbX2jtzBk8TTBjjTWJF9W4P 3WqUeWOeQIT+YSDKFtwsofghZyWxQoILvQZFMJBXG2WEx73NVvCClFJCZsn0pGz0IYCy k1SY9jXB/xKS75alrQvK7A1SB52LgIwKMwMbF3Us0axjaE9ZLGjR83DS8AmZhZGK6Kea Y6hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tiyYxTb8Rk/mH72C96BXIjZ0994JQE265VRKbdZ6Y4s=; b=QRf4HuJOyLcw0xEvHPcUPs8MfHED9dZb94lYFij5gSPOorHFSRgA66/P4h13zWZkSZ CqWArmBPoBOW/WTUz+hdnJfIydwUh9HiO3o3TUw1SdnBI9DFo3oQo7oTsMrAXUir9R5g dY/MBiS+c/C0l/l1jL9L+hsVL0Y8pW0d0K5X4+lpO8eizXgJv/wPG5tCFlG97ymkqOtQ Ea9P7rn9uVLvzCUB1BdybJI01LcQRiGfVnGuser9AGHY8TqDOWcAuKfQK9SwG1mD95xm nAu3JZqj/OXnN5Nf9mbbpNX8Mv1EZpGsjhT2aKWvXqPoNrjQsEe0r+Api2SAVG7Ezwac ywqg== X-Gm-Message-State: APjAAAXNO5VaFs4KN5Z2C9wViIDAJKGEPGJQXbRr4iqwPTgFB4qmgJHk w18YvEDdWap3CMHEvIt9zjc= X-Google-Smtp-Source: APXvYqzMq+83TkjxUSM11kZkx3mF/4DvBV0+2sGks49oMiHitp16MlZiefH8kui2kfgFepTTKQYiCA== X-Received: by 2002:a5d:54c4:: with SMTP id x4mr25727213wrv.247.1573999661231; Sun, 17 Nov 2019 06:07:41 -0800 (PST) Received: from localhost.localdomain (p200300F1371CB100428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:371c:b100:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id n23sm16632977wmc.18.2019.11.17.06.07.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2019 06:07:40 -0800 (PST) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, Martin Blumenstingl , Rob Herring Subject: [PATCH v3 1/2] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Date: Sun, 17 Nov 2019 15:07:30 +0100 Message-Id: <20191117140731.137378-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191117140731.137378-1-martin.blumenstingl@googlemail.com> References: <20191117140731.137378-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in the MMCBUS registers. There is no public documentation on this, but the GPL u-boot sources from the Amlogic BSP show that: - it uses the same XTAL input as the main clock controller - it contains a PLL which seems to be implemented just like the other PLLs in this SoC - there is a power-of-two PLL post-divider Add the documentation and header file for this DDR clock controller. Reviewed-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Martin Blumenstingl --- .../clock/amlogic,meson8-ddr-clkc.yaml | 50 +++++++++++++++++++ include/dt-bindings/clock/meson8-ddr-clkc.h | 4 ++ 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml new file mode 100644 index 000000000000..4b8669f870ec --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic DDR Clock Controller Device Tree Bindings + +maintainers: + - Martin Blumenstingl + +properties: + compatible: + enum: + - amlogic,meson8-ddr-clkc + - amlogic,meson8b-ddr-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/meson8-ddr-clkc.h b/include/dt-bindings/clock/meson8-ddr-clkc.h new file mode 100644 index 000000000000..a8e0fa2987ab --- /dev/null +++ b/include/dt-bindings/clock/meson8-ddr-clkc.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#define DDR_CLKID_DDR_PLL_DCO 0 +#define DDR_CLKID_DDR_PLL 1 From patchwork Sun Nov 17 14:07:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11248419 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E03CE159A for ; Sun, 17 Nov 2019 14:07:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B45F820871 for ; Sun, 17 Nov 2019 14:07:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="Puy6cZj+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726273AbfKQOHs (ORCPT ); Sun, 17 Nov 2019 09:07:48 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:34370 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726037AbfKQOHp (ORCPT ); Sun, 17 Nov 2019 09:07:45 -0500 Received: by mail-wm1-f65.google.com with SMTP id j18so13849765wmk.1; Sun, 17 Nov 2019 06:07:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rUS5IGpkaPi+dGpzM4Vf2xl/ff80v7YNdleQ2dpR1UA=; b=Puy6cZj+QzezYj/UZ9GHaqRR7K0lgC91UdC59TjF/uHRPqpJq0DbZPWZ/SYDn+ccEU YunqDqp4gTh7iTFhFX30iwA7IY5UcZ1hvRCdlFsv44r4vM0/35xctLsnFSppx2l0RuCZ 3qLG2cumXE97mA9ln052vHxW2zXL4TRlXeZImCIfA6TasApGLmvZ4XRAESdHFpAVOexX 4A5YGMHRR7e/+73kpU7xeveS87qtBrxXsAQ57Quai77Z3VqN9pwsBdtnjXfoG6BANyT2 c+68owKC573nV5j9nYjBGNHrQxFqwNC2oIA7dskMmP/VLFkVdbQSpXsf9WHfrbKVSnVo hdlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rUS5IGpkaPi+dGpzM4Vf2xl/ff80v7YNdleQ2dpR1UA=; b=Qn6i5KWYoLJWPBXujYlWFmKO9DpRobWrM3sZUXe92v1BC9ssLNVup17/P4DZHsxJEK Ck7GQ2hP9VcdM6m9oMqQu+8JvLx7W7jb/irhBjkzKJz+cy4M37aHpeswyQ8PJfbbSFRw 8q2aqgYThM7fVyRaP8L8S0uhQCG0SZ1nMk5H8cW1AElH47DWX6Jp0p+3m+5epxt8eGYZ kRoOl3RROINpQeufshdf4+9iI4td7NRnxMunYUCxTRqq2RITTep72zUGrcN45STrQXax KOEjbyVOPlOgDLilpFMIuNnWe1GfDmE21oYU49i45FNUO+YgOoTGK16VxTFoi3Vb1TU0 a13A== X-Gm-Message-State: APjAAAWXqKsu0yaqXEIbugRClMtNwfkqRwwpUnmtMWxuzMCeMha59axN NBSGE3PZmOsNUhnNZa1D5wNTj0lb X-Google-Smtp-Source: APXvYqyr0QEnccVZAjzuk6go6SoJxKQv25UhH0zdyvgJurN2iaqv8W3Qbh12jxLUu4HK4MJQOf6N6g== X-Received: by 2002:a1c:6144:: with SMTP id v65mr25353746wmb.53.1573999662210; Sun, 17 Nov 2019 06:07:42 -0800 (PST) Received: from localhost.localdomain (p200300F1371CB100428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:371c:b100:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id n23sm16632977wmc.18.2019.11.17.06.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2019 06:07:41 -0800 (PST) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, Martin Blumenstingl Subject: [PATCH v3 2/2] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller Date: Sun, 17 Nov 2019 15:07:31 +0100 Message-Id: <20191117140731.137378-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191117140731.137378-1-martin.blumenstingl@googlemail.com> References: <20191117140731.137378-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the MMCBUS registers. There is no public documentation, but the u-boot GPL sources from the Amlogic BSP show that the DDR clock controller is identical on all three SoCs: #define CFG_DDR_CLK 792 #define CFG_PLL_M (((CFG_DDR_CLK/12)*12)/24) #define CFG_PLL_N 1 #define CFG_PLL_OD 1 // from set_ddr_clock: t_ddr_pll_cntl= (CFG_PLL_OD << 16)|(CFG_PLL_N<<9)|(CFG_PLL_M<<0) writel(timing_reg->t_ddr_pll_cntl|(1<<29),AM_DDR_PLL_CNTL); writel(readl(AM_DDR_PLL_CNTL) & (~(1<<29)),AM_DDR_PLL_CNTL); // from hx_ddr_power_down_enter: shut down DDR PLL writel(readl(AM_DDR_PLL_CNTL)|(1<<30),AM_DDR_PLL_CNTL); do { ... } while((readl(AM_DDR_PLL_CNTL)&(1<<31))==0) This translates to: - AM_DDR_PLL_CNTL[29] is the reset bit - AM_DDR_PLL_CNTL[30] is the enable bit - AM_DDR_PLL_CNTL[31] is the lock bit - AM_DDR_PLL_CNTL[8:0] is the m value (assuming the width is 9 bits based on the start of the n value) - AM_DDR_PLL_CNTL[13:9] is the n value (assuming the width is 5 bits based on the start of the od) - AM_DDR_PLL_CNTL[17:16] is the od (assuming the width is 2 bits based on other PLLs on this SoC) Add a driver for this PLL setup because it's used as one of the inputs of the audio clocks. There may be more clocks inside that clock controller - those can be added in subsequent patches. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/meson8-ddr.c | 149 +++++++++++++++++++++++++++++++++ 2 files changed, 150 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/meson8-ddr.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 3939f218587a..6eca2a406ee3 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -18,4 +18,4 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o -obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o +obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c new file mode 100644 index 000000000000..4b73ea244b63 --- /dev/null +++ b/drivers/clk/meson/meson8-ddr.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Amlogic Meson8 DDR clock controller + * + * Copyright (C) 2019 Martin Blumenstingl + */ + +#include + +#include +#include + +#include "clk-regmap.h" +#include "clk-pll.h" + +#define AM_DDR_PLL_CNTL 0x00 +#define AM_DDR_PLL_CNTL1 0x04 +#define AM_DDR_PLL_CNTL2 0x08 +#define AM_DDR_PLL_CNTL3 0x0c +#define AM_DDR_PLL_CNTL4 0x10 +#define AM_DDR_PLL_STS 0x14 +#define DDR_CLK_CNTL 0x18 +#define DDR_CLK_STS 0x1c + +static struct clk_regmap meson8_ddr_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 30, + .width = 1, + }, + .m = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .l = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 29, + .width = 1, + }, + }, + .hw.init = &(struct clk_init_data){ + .name = "ddr_pll_dco", + .ops = &meson_clk_pll_ro_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap meson8_ddr_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = AM_DDR_PLL_CNTL, + .shift = 16, + .width = 2, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "ddr_pll", + .ops = &clk_regmap_divider_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &meson8_ddr_pll_dco.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = { + .hws = { + [DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw, + [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw, + }, + .num = 2, +}; + +static struct clk_regmap *const meson8_ddr_clk_regmaps[] = { + &meson8_ddr_pll_dco, + &meson8_ddr_pll, +}; + +static const struct regmap_config meson8_ddr_clkc_regmap_config = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = DDR_CLK_STS, +}; + +static int meson8_ddr_clkc_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + void __iomem *base; + struct clk_hw *hw; + int ret, i; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, + &meson8_ddr_clkc_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Populate regmap */ + for (i = 0; i < ARRAY_SIZE(meson8_ddr_clk_regmaps); i++) + meson8_ddr_clk_regmaps[i]->map = regmap; + + /* Register all clks */ + for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) { + hw = meson8_ddr_clk_hw_onecell_data.hws[i]; + + ret = devm_clk_hw_register(&pdev->dev, hw); + if (ret) { + dev_err(&pdev->dev, "Clock registration failed\n"); + return ret; + } + } + + return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + &meson8_ddr_clk_hw_onecell_data); +} + +static const struct of_device_id meson8_ddr_clkc_match_table[] = { + { .compatible = "amlogic,meson8-ddr-clkc" }, + { .compatible = "amlogic,meson8b-ddr-clkc" }, + { /* sentinel */ } +}; + +static struct platform_driver meson8_ddr_clkc_driver = { + .probe = meson8_ddr_clkc_probe, + .driver = { + .name = "meson8-ddr-clkc", + .of_match_table = meson8_ddr_clkc_match_table, + }, +}; + +builtin_platform_driver(meson8_ddr_clkc_driver);