From patchwork Thu Nov 21 05:02:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11255287 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA0C0138C for ; Thu, 21 Nov 2019 05:02:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A7B9120B7C for ; Thu, 21 Nov 2019 05:02:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="nsFjzqbb" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A7B9120B7C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KLGyUbM9zUEyMWB4xh6EGaW9klqHvTe6HxQ5IxdYRoM=; b=nsFjzqbb5qG0e4 h+XbgSX7aCi5G56Vi2CeSuyDlHUcWzrkFcYzX62+n08oIZzYrvMnJ2Pr1vkTFQGYCOxrSrM1Tpka7 108y//s0ko7qZwTzYc9fATnj26P43Z/Yd6ebgDqq36zRqVStS+AY9WAvE15jD/h3pBmDdx+LABkHc z70nmopwNiJ7WlVhGzuw5Uzecd7YQW+h7XjKk38xhIJ3N3826FRfM7QFJS42yQZQzkGnz6dVD7iVO MEvYTVUDy1hWzUHCUfp6vjhsC+e/i2UflyPQrv6CUlPcXCxP24n17yg86yvohV5ZHPkiohuFX3xCq Y+RXGxINZCGHPDv5i9Fg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXec2-0004Hc-B4; Thu, 21 Nov 2019 05:02:38 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebm-00044X-24; Thu, 21 Nov 2019 05:02:23 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 355E0AFD4; Thu, 21 Nov 2019 05:02:18 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v5 1/9] dt-bindings: interrupt-controller: Add Realtek RTD1195/RTD1295 mux Date: Thu, 21 Nov 2019 06:02:00 +0100 Message-Id: <20191121050208.11324-2-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_210222_244058_AAA2761D X-CRM114-Status: GOOD ( 11.09 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Rob Herring , Thomas Gleixner , =?utf-8?q?Andreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add binding for Realtek RTD1295 and RTD1195 IRQ mux. Acked-by: Rob Herring [AF: Converted to YAML schema] Signed-off-by: Andreas Färber --- v4 -> v5: Unchanged v3 -> v4: * Squashed RTD1195 * Converted to YAML schema * Renamed file from realtek,rtd119x-mux to realtek,rtd1195-mux v2 -> v3: * Renamed non-iso irq mux to "misc" for clarity v1 -> v2: * Dropped reference to common interrupt.txt bindings (Rob) .../interrupt-controller/realtek,rtd1195-mux.yaml | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml new file mode 100644 index 000000000000..5cf3a28cedba --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtd1195-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTD1195/1295 IRQ Mux Controller + +maintainers: + - Andreas Färber + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + enum: + - realtek,rtd1195-misc-irq-mux + - realtek,rtd1195-iso-irq-mux + - realtek,rtd1295-misc-irq-mux + - realtek,rtd1295-iso-irq-mux + + reg: + maxItems: 1 + + interrupts: + description: Specifies the interrupt line which is mux'ed. + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + +examples: + - | + #include + + interrupt-controller@98007000 { + compatible = "realtek,rtd1295-iso-irq-mux"; + reg = <0x98007000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; +... From patchwork Thu Nov 21 05:02:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11255299 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CAE82138C for ; Thu, 21 Nov 2019 05:04:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A104E20672 for ; Thu, 21 Nov 2019 05:04:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="AMMIO+4U" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A104E20672 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yglaNaFmIy0cEIIsqRGu4lGHlc2k+rGM62NoFLufcpI=; b=AMMIO+4U0sc+A3 LFViZMxJtOzi915oO7DNRhGHFiXa9dMVkOWJmDU/Qz5V07aRadBe9fy13DiTTfi1rMbabLG1mpXJK yJ9tpi5ObEDVXvXThMtWvAe86tb1SeV9Xuh32rSOkFcMLlKOa0lrRVfdMpfrCBkEhK6EFcyV9G5Bg W5+SRE/aWk3KNGhXcqT/3ai6OuefRaAB0emvll7nlZz4uPqdk9SWowMiIV5FrN4vWepT3X5zDk4X5 kA2JxwUDQRF2GfFQCrUNareKH9JXHNz5Yu7x0gpiTIK2ZopCCI6W7XBLEdIFxYTRwR9lM9fZN20k6 tRB+g5dTgRmJYbIpjDTQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXedT-0005mL-Gv; Thu, 21 Nov 2019 05:04:07 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebm-00044Z-24; Thu, 21 Nov 2019 05:02:27 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id F1E1DAFF6; Thu, 21 Nov 2019 05:02:18 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v5 2/9] irqchip: Add Realtek RTD1295 mux driver Date: Thu, 21 Nov 2019 06:02:01 +0100 Message-Id: <20191121050208.11324-3-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_210222_394923_18F4BC50 X-CRM114-Status: GOOD ( 14.58 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Tai , Aleix Roca Nonell , Marc Zyngier , linux-kernel@vger.kernel.org, Thomas Gleixner , =?utf-8?q?Andreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org, Jason Cooper Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This irq mux driver implements the RTD1295 SoC's non-linear mapping between status and enable bits. Based in part on QNAP's arch/arm/mach-rtk119x/rtk_irq_mux.c and Synology's drivers/irqchip/irq-rtk.c code. Signed-off-by: Andreas Färber Cc: Aleix Roca Nonell Signed-off-by: James Tai Signed-off-by: Andreas Färber --- v4 -> v5: * Renamed enable/disable to unmask/mask (Marc) * Factored out ack (Marc) * Clear all interrupts just in case * Added and mapped WDOG_NMI * Suppress mapping NMIs and reserved bits (Marc) * Dropped mask checks in mask/unmask (Marc) * Dropped mask check in interrupt handler * Renamed misc bits by inserting MIS_ for consistency * Duplicate irq_chip into rtd1195_mux_data * Renamed irq_chip from long rtd1195-mux to iso/misc, tidying /proc/interrupts v3 -> v4: * Drop no-op .irq_set_affinity callback (Thomas) * Clear all interrupts (James) * Updated SPDX-License-identifier * Use tabular formatting (Thomas) * Adopt different braces style (Thomas) * Use raw_spinlock_t (Thomas) * Shortened callback from isr_to_scpu_int_en_mask to isr_to_int_en_mask (Thomas) * Fixed of_iomap() error handling to not use IS_ERR() * Don't mask unmapped NMIs by checking for a non-zero mask * Cache SCPU_INT_EN to avoid superfluous reads (Thomas) * Renamed functions and variables from rtd119x to rtd1195 v2 -> v3: * Adopted spin_lock_irq{save,restore}() (Marc) * Adopted single-write masking (Marc) * Adopted misc compatible string * Introduced explicit bit mapping * Adopted looped processing of pending interrupts (Marc) * Replaced unmask implementation with UMSK_ISR write * Introduced enable/disable ops and dropped no longer needed UART0 quirk v1 -> v2: * Renamed struct fields to avoid ambiguity (Marc) * Refactored offset lookup to avoid per-compatible init functions * Inserted white lines to clarify balanced locking (Marc) * Dropped forwarding of set_affinity to GIC (Marc) * Added spinlocks for consistency (Marc) * Limited initialization quirk to iso mux * Fixed spinlock initialization (Andrew) drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-rtd1195-mux.c | 291 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 292 insertions(+) create mode 100644 drivers/irqchip/irq-rtd1195-mux.c diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e806dda690ea..d678881eebc8 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -104,3 +104,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_ARCH_REALTEK) += irq-rtd1195-mux.o diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c new file mode 100644 index 000000000000..0e86973aafca --- /dev/null +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek RTD1295 IRQ mux + * + * Copyright (c) 2017-2019 Andreas Färber + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define UMSK_ISR_WRITE_DATA BIT(0) +#define ISR_WRITE_DATA BIT(0) + +struct rtd1195_irq_mux_info { + const char *name; + unsigned int isr_offset; + unsigned int umsk_isr_offset; + unsigned int scpu_int_en_offset; + const u32 *isr_to_int_en_mask; +}; + +#define SCPU_INT_EN_RSV_MASK 0 +#define SCPU_INT_EN_NMI_MASK GENMASK(31, 0) + +struct rtd1195_irq_mux_data { + void __iomem *reg_isr; + void __iomem *reg_umsk_isr; + void __iomem *reg_scpu_int_en; + const struct rtd1195_irq_mux_info *info; + int irq; + u32 scpu_int_en; + struct irq_chip chip; + struct irq_domain *domain; + raw_spinlock_t lock; +}; + +static void rtd1195_mux_irq_handle(struct irq_desc *desc) +{ + struct rtd1195_irq_mux_data *mux = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 isr; + int i; + + chained_irq_enter(chip, desc); + + isr = readl_relaxed(mux->reg_isr); + + while (isr) { + i = __ffs(isr); + isr &= ~BIT(i); + + generic_handle_irq(irq_find_mapping(mux->domain, i)); + } + + chained_irq_exit(chip, desc); +} + +static void rtd1195_mux_ack_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data); + + writel_relaxed(BIT(data->hwirq) & ~ISR_WRITE_DATA, mux->reg_isr); +} + +static void rtd1195_mux_mask_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data); + u32 mask = mux->info->isr_to_int_en_mask[data->hwirq]; + unsigned long flags; + + raw_spin_lock_irqsave(&mux->lock, flags); + + mux->scpu_int_en &= ~mask; + writel_relaxed(mux->scpu_int_en, mux->reg_scpu_int_en); + + raw_spin_unlock_irqrestore(&mux->lock, flags); +} + +static void rtd1195_mux_unmask_irq(struct irq_data *data) +{ + struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data); + u32 mask = mux->info->isr_to_int_en_mask[data->hwirq]; + unsigned long flags; + + raw_spin_lock_irqsave(&mux->lock, flags); + + mux->scpu_int_en |= mask; + writel_relaxed(mux->scpu_int_en, mux->reg_scpu_int_en); + + raw_spin_unlock_irqrestore(&mux->lock, flags); +} + +static const struct irq_chip rtd1195_mux_irq_chip = { + .irq_ack = rtd1195_mux_ack_irq, + .irq_mask = rtd1195_mux_mask_irq, + .irq_unmask = rtd1195_mux_unmask_irq, +}; + +static int rtd1195_mux_irq_domain_map(struct irq_domain *d, + unsigned int irq, irq_hw_number_t hw) +{ + struct rtd1195_irq_mux_data *mux = d->host_data; + u32 mask; + + if (BIT(hw) == ISR_WRITE_DATA) + return -EINVAL; + + mask = mux->info->isr_to_int_en_mask[hw]; + if (mask == SCPU_INT_EN_RSV_MASK) + return -EINVAL; + + if (mask == SCPU_INT_EN_NMI_MASK) + return -ENOTSUPP; + + irq_set_chip_and_handler(irq, &mux->chip, handle_level_irq); + irq_set_chip_data(irq, mux); + irq_set_probe(irq); + + return 0; +} + +static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = rtd1195_mux_irq_domain_map, +}; + +enum rtd1295_iso_isr_bits { + RTD1295_ISO_ISR_UR0_SHIFT = 2, + RTD1295_ISO_ISR_IRDA_SHIFT = 5, + RTD1295_ISO_ISR_I2C0_SHIFT = 8, + RTD1295_ISO_ISR_I2C1_SHIFT = 11, + RTD1295_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1295_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1295_ISO_ISR_GPIOA_SHIFT = 19, + RTD1295_ISO_ISR_GPIODA_SHIFT = 20, + RTD1295_ISO_ISR_GPHY_DV_SHIFT = 29, + RTD1295_ISO_ISR_GPHY_AV_SHIFT = 30, + RTD1295_ISO_ISR_I2C1_REQ_SHIFT = 31, +}; + +static const u32 rtd1295_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1295_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1295_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1295_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1295_ISO_ISR_I2C1_SHIFT] = BIT(11), + [RTD1295_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1295_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1295_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1295_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1295_ISO_ISR_GPHY_DV_SHIFT] = BIT(29), + [RTD1295_ISO_ISR_GPHY_AV_SHIFT] = BIT(30), + [RTD1295_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31), +}; + +enum rtd1295_misc_isr_bits { + RTD1295_MIS_ISR_WDOG_NMI_SHIFT = 2, + RTD1295_MIS_ISR_UR1_SHIFT = 3, + RTD1295_MIS_ISR_UR1_TO_SHIFT = 5, + RTD1295_MIS_ISR_UR2_SHIFT = 8, + RTD1295_MIS_ISR_RTC_MIN_SHIFT = 10, + RTD1295_MIS_ISR_RTC_HOUR_SHIFT = 11, + RTD1295_MIS_ISR_RTC_DATA_SHIFT = 12, + RTD1295_MIS_ISR_UR2_TO_SHIFT = 13, + RTD1295_MIS_ISR_I2C5_SHIFT = 14, + RTD1295_MIS_ISR_I2C4_SHIFT = 15, + RTD1295_MIS_ISR_GPIOA_SHIFT = 19, + RTD1295_MIS_ISR_GPIODA_SHIFT = 20, + RTD1295_MIS_ISR_LSADC0_SHIFT = 21, + RTD1295_MIS_ISR_LSADC1_SHIFT = 22, + RTD1295_MIS_ISR_I2C3_SHIFT = 23, + RTD1295_MIS_ISR_SC0_SHIFT = 24, + RTD1295_MIS_ISR_I2C2_SHIFT = 26, + RTD1295_MIS_ISR_GSPI_SHIFT = 27, + RTD1295_MIS_ISR_FAN_SHIFT = 29, +}; + +static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1295_MIS_ISR_UR1_SHIFT] = BIT(3), + [RTD1295_MIS_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1295_MIS_ISR_UR2_TO_SHIFT] = BIT(6), + [RTD1295_MIS_ISR_UR2_SHIFT] = BIT(7), + [RTD1295_MIS_ISR_RTC_MIN_SHIFT] = BIT(10), + [RTD1295_MIS_ISR_RTC_HOUR_SHIFT] = BIT(11), + [RTD1295_MIS_ISR_RTC_DATA_SHIFT] = BIT(12), + [RTD1295_MIS_ISR_I2C5_SHIFT] = BIT(14), + [RTD1295_MIS_ISR_I2C4_SHIFT] = BIT(15), + [RTD1295_MIS_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1295_MIS_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1295_MIS_ISR_LSADC0_SHIFT] = BIT(21), + [RTD1295_MIS_ISR_LSADC1_SHIFT] = BIT(22), + [RTD1295_MIS_ISR_SC0_SHIFT] = BIT(24), + [RTD1295_MIS_ISR_I2C2_SHIFT] = BIT(26), + [RTD1295_MIS_ISR_GSPI_SHIFT] = BIT(27), + [RTD1295_MIS_ISR_I2C3_SHIFT] = BIT(28), + [RTD1295_MIS_ISR_FAN_SHIFT] = BIT(29), + [RTD1295_MIS_ISR_WDOG_NMI_SHIFT] = SCPU_INT_EN_NMI_MASK, +}; + +static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { + .name = "iso", + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, +}; + +static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { + .name = "misc", + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1295_misc_isr_to_scpu_int_en_mask, +}; + +static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { + { + .compatible = "realtek,rtd1295-iso-irq-mux", + .data = &rtd1295_iso_irq_mux_info, + }, + { + .compatible = "realtek,rtd1295-misc-irq-mux", + .data = &rtd1295_misc_irq_mux_info, + }, + { + } +}; + +static int __init rtd1195_irq_mux_init(struct device_node *node, + struct device_node *parent) +{ + struct rtd1195_irq_mux_data *mux; + const struct of_device_id *match; + const struct rtd1195_irq_mux_info *info; + void __iomem *base; + + match = of_match_node(rtd1295_irq_mux_dt_matches, node); + if (!match) + return -EINVAL; + + info = match->data; + if (!info) + return -EINVAL; + + base = of_iomap(node, 0); + if (!base) + return -EIO; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + mux->info = info; + mux->reg_isr = base + info->isr_offset; + mux->reg_umsk_isr = base + info->umsk_isr_offset; + mux->reg_scpu_int_en = base + info->scpu_int_en_offset; + mux->chip = rtd1195_mux_irq_chip; + mux->chip.name = info->name; + + mux->irq = irq_of_parse_and_map(node, 0); + if (mux->irq <= 0) { + kfree(mux); + return -EINVAL; + } + + raw_spin_lock_init(&mux->lock); + + /* Disable (mask) all interrupts */ + writel_relaxed(mux->scpu_int_en, mux->reg_scpu_int_en); + + /* Ack (clear) all interrupts - not all are in UMSK_ISR, so use ISR */ + writel_relaxed(~ISR_WRITE_DATA, mux->reg_isr); + + mux->domain = irq_domain_add_linear(node, 32, + &rtd1195_mux_irq_domain_ops, mux); + if (!mux->domain) { + kfree(mux); + return -ENOMEM; + } + + irq_set_chained_handler_and_data(mux->irq, rtd1195_mux_irq_handle, mux); + + return 0; +} +IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init); From patchwork Thu Nov 21 05:02:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11255285 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8CB98138C for ; Thu, 21 Nov 2019 05:02:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 604DE208A3 for ; Thu, 21 Nov 2019 05:02:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="WAFE3GFw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 604DE208A3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Bof9KG+coxj4grlIPEXA8d8Vm+078rmLnSCZMa9CABk=; b=WAFE3GFwBs8SgO GSiq2UjInA4P0lb/AQzGuOaoFepYkEBXRl5BXmdzUwc2dmEM0adOJv3WO8Szlp/4acLNNtPLSG6E1 u2YOHdGhHq6h1IwQf4VtYzGTezSM9IvoFZ4mx5l96L2WLOX4d1b6gDYbDp2aMBukyLDWBnjiB7jZ0 RaaOr6LpIaVHgSAQ8z4o71bS4Vf20VQfbXqYe0tLVbZuqi1o6rIO+XxpYKCrqKzrrSrPZU3pUDLl6 qWQRVDyyatkj9P+ZvNkNlimBOIQQ3iP5Ax52+7OHI8o3TwRN90OQ6dbPVg8XUtSEcBLHAdpMteRoY C/nrhFmBf8/ktbG9a81A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebp-00046e-0m; Thu, 21 Nov 2019 05:02:25 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebm-00044a-28; Thu, 21 Nov 2019 05:02:23 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 3B77BB00A; Thu, 21 Nov 2019 05:02:19 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v5 3/9] irqchip: rtd1195-mux: Implement irq_get_irqchip_state Date: Thu, 21 Nov 2019 06:02:02 +0100 Message-Id: <20191121050208.11324-4-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_210222_244333_66CDA51E X-CRM114-Status: GOOD ( 10.75 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Thomas Gleixner , =?utf-8?q?Andreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Implement the .irq_get_irqchip_state callback to retrieve pending, active and masked interrupt status. Signed-off-by: Andreas Färber --- v5: New drivers/irqchip/irq-rtd1195-mux.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index 0e86973aafca..2f1bcfd9d5d6 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -96,10 +97,45 @@ static void rtd1195_mux_unmask_irq(struct irq_data *data) raw_spin_unlock_irqrestore(&mux->lock, flags); } +static int rtd1195_mux_get_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, bool *state) +{ + struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data); + u32 val; + + switch (which) { + case IRQCHIP_STATE_PENDING: + /* + * UMSK_ISR provides the unmasked pending interrupts, + * except UART and I2C. + */ + val = readl_relaxed(mux->reg_umsk_isr); + *state = !!(val & BIT(data->hwirq)); + break; + case IRQCHIP_STATE_ACTIVE: + /* + * ISR provides the masked pending interrupts, + * including UART and I2C. + */ + val = readl_relaxed(mux->reg_isr); + *state = !!(val & BIT(data->hwirq)); + break; + case IRQCHIP_STATE_MASKED: + val = mux->info->isr_to_int_en_mask[data->hwirq]; + *state = !(mux->scpu_int_en & val); + break; + default: + return -EINVAL; + } + + return 0; +} + static const struct irq_chip rtd1195_mux_irq_chip = { .irq_ack = rtd1195_mux_ack_irq, .irq_mask = rtd1195_mux_mask_irq, .irq_unmask = rtd1195_mux_unmask_irq, + .irq_get_irqchip_state = rtd1195_mux_get_irqchip_state, }; static int rtd1195_mux_irq_domain_map(struct irq_domain *d, From patchwork Thu Nov 21 05:02:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11255289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 52EA814C0 for ; Thu, 21 Nov 2019 05:03:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2E6972084D for ; Thu, 21 Nov 2019 05:03:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="U1MHNWYZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2E6972084D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IHGNKLAhzPqIspSyFHYXyhU3UGWvC9UpL2UN/VgD/Mw=; b=U1MHNWYZjvkoHq z7ml8SVxt8uoDzBQdW4LeX2it5EqeiCRU2VgBqgbEErpciMmVzSnaUcYQiKWf1/i2nycAuCLB04Tp VfNAmLGNZFE9AMKQt+oiNoxMhCbZRAbmX5RRqZWJNLGHZAozZhpNYNLCLXdcb152BS0kHnmUH2Q3Q /a+ZtIIrew7O4C5rHBY2hEidsx4Ni8YSKdIdOzG5YeBRR8A0DBkLj3SJg32uTpZIHq1ePxCvJ5ZUD KVnaooU39nfBQsQAyxlzTte5t0Qe2ywCiGzgmm6iT4xO7Z/qTK/razKMcx0F4Gk8ivzWWOFxKC2t8 ZN3eekwMUTeFJep/o4Iw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXecN-0004Zn-KS; Thu, 21 Nov 2019 05:02:59 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebm-00044b-8v; Thu, 21 Nov 2019 05:02:25 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id A2994B016; Thu, 21 Nov 2019 05:02:19 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v5 4/9] arm64: dts: realtek: rtd129x: Add irq muxes and UART interrupts Date: Thu, 21 Nov 2019 06:02:03 +0100 Message-Id: <20191121050208.11324-5-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_210222_491308_C9985AEC X-CRM114-Status: UNSURE ( 9.83 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , =?utf-8?q?A?= =?utf-8?q?ndreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add iso and misc IRQ mux DT nodes to RTD129x SoC family. Update the UART DT nodes with interrupts from these muxes, so that UART0 can be used without earlycon. Signed-off-by: Andreas Färber --- v4 -> v5: Unchanged v3 -> v4: * Rebased onto chip-info and r-bus * Dropped schema-violating second interrupts for UART1 and UART2 v2 -> v3: * Added nodes to rtd129x.dtsi instead of rtd1295.dtsi * Adopted misc compatible string * Renamed node label from irq_mux to misc_irq_mux for clarity v1 -> v2: * Rebased arch/arm64/boot/dts/realtek/rtd129x.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 7d56c9f5d48a..188b4f256917 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -86,6 +86,14 @@ #reset-cells = <1>; }; + iso_irq_mux: interrupt-controller@7000 { + compatible = "realtek,rtd1295-iso-irq-mux"; + reg = <0x7000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + iso_reset: reset-controller@7088 { compatible = "snps,dw-low-reset"; reg = <0x7088 0x4>; @@ -105,6 +113,8 @@ reg-io-width = <4>; clock-frequency = <27000000>; resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + interrupt-parent = <&iso_irq_mux>; + interrupts = <2>; status = "disabled"; }; @@ -115,6 +125,14 @@ <0x171d8 0x4>; }; + misc_irq_mux: interrupt-controller@1b000 { + compatible = "realtek,rtd1295-misc-irq-mux"; + reg = <0x1b000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + uart1: serial@1b200 { compatible = "snps,dw-apb-uart"; reg = <0x1b200 0x100>; @@ -122,6 +140,8 @@ reg-io-width = <4>; clock-frequency = <432000000>; resets = <&reset2 RTD1295_RSTN_UR1>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <3>; status = "disabled"; }; @@ -132,6 +152,8 @@ reg-io-width = <4>; clock-frequency = <432000000>; resets = <&reset2 RTD1295_RSTN_UR2>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <8>; status = "disabled"; }; }; From patchwork Thu Nov 21 05:02:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11255297 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9EB9514C0 for ; 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bh=4xV1llZ0xgNDvsciToHGsKbBEz0ce3uc37xVR5VywtI=; b=qnuZ7Atj4vlKJ+ xybUuGtzgSTZXGCbDtM5x5aEspyfx36IYUcFd4x5X7R8FPYzA4FUbXIa0V6T9NWOAXEKaYGQuFuC4 juzUPt00Hv33XCE6GUqbKW5q7u++HD5LuKYf7ZvdlVRVQVRVIfxkn1eyWM91QzK9kUlIzZHnV65Hv qJUAgDAi/Y29BIL0rOi8I6UkqfS8mCKV0pTE33nQMuQMbUW1NODguLviZ/5a3MNncs9lwHaw0HNAh CeNXw3fC27Hujmy3z+q6KU/wzdK4lGQg/lKjdN1Hh/81y9CsnV8IfZC7HdcxKBoqnH6Z5CwYMgoTs bZ8AznhQESJUlBSFg9hQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXedI-0005YG-DE; Thu, 21 Nov 2019 05:03:56 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebo-00046T-U8; Thu, 21 Nov 2019 05:02:27 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 13172B01C; Thu, 21 Nov 2019 05:02:20 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v5 5/9] irqchip: rtd1195-mux: Add RTD1195 definitions Date: Thu, 21 Nov 2019 06:02:04 +0100 Message-Id: <20191121050208.11324-6-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_210225_311230_EDD4B84F X-CRM114-Status: GOOD ( 10.99 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Thomas Gleixner , =?utf-8?q?Andreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add compatible strings and bit mappings for Realtek RTD1195 SoC. Signed-off-by: Andreas Färber --- v4 -> v5: * Mapped WDOG_NMI * Filled in irq_chip names v3 -> v4: * Use tabular formatting (Thomas) * Adopt different braces style (Thomas) * Updated with shortened isr_to_int_en_mask callback name (Thomas) * Renamed functions and variables from rtd119x_ to rtd1195_ * Renamed enum values from RTD119X_ to RTD1195_ v3: New drivers/irqchip/irq-rtd1195-mux.c | 104 +++++++++++++++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index 2f1bcfd9d5d6..e3e2e42d9df2 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Realtek RTD1295 IRQ mux + * Realtek RTD1195/RTD1295 IRQ mux * * Copyright (c) 2017-2019 Andreas Färber */ @@ -166,6 +166,82 @@ static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = { .map = rtd1195_mux_irq_domain_map, }; +enum rtd1195_iso_isr_bits { + RTD1195_ISO_ISR_TC3_SHIFT = 1, + RTD1195_ISO_ISR_UR0_SHIFT = 2, + RTD1195_ISO_ISR_IRDA_SHIFT = 5, + RTD1195_ISO_ISR_WDOG_NMI_SHIFT = 7, + RTD1195_ISO_ISR_I2C0_SHIFT = 8, + RTD1195_ISO_ISR_TC4_SHIFT = 9, + RTD1195_ISO_ISR_I2C6_SHIFT = 10, + RTD1195_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1195_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1195_ISO_ISR_VFD_WDONE_SHIFT = 14, + RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT = 15, + RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT = 16, + RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT = 17, + RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT = 18, + RTD1195_ISO_ISR_GPIOA_SHIFT = 19, + RTD1195_ISO_ISR_GPIODA_SHIFT = 20, + RTD1195_ISO_ISR_CEC_SHIFT = 22, +}; + +static const u32 rtd1195_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1195_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1195_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1195_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1195_ISO_ISR_I2C6_SHIFT] = BIT(10), + [RTD1195_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1195_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1195_ISO_ISR_VFD_WDONE_SHIFT] = BIT(14), + [RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT] = BIT(15), + [RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT] = BIT(16), + [RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT] = BIT(17), + [RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT] = BIT(18), + [RTD1195_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1195_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1195_ISO_ISR_CEC_SHIFT] = BIT(22), +}; + +enum rtd1195_misc_isr_bits { + RTD1195_MIS_ISR_WDOG_NMI_SHIFT = 2, + RTD1195_MIS_ISR_UR1_SHIFT = 3, + RTD1195_MIS_ISR_I2C1_SHIFT = 4, + RTD1195_MIS_ISR_UR1_TO_SHIFT = 5, + RTD1195_MIS_ISR_TC0_SHIFT = 6, + RTD1195_MIS_ISR_TC1_SHIFT = 7, + RTD1195_MIS_ISR_RTC_HSEC_SHIFT = 9, + RTD1195_MIS_ISR_RTC_MIN_SHIFT = 10, + RTD1195_MIS_ISR_RTC_HOUR_SHIFT = 11, + RTD1195_MIS_ISR_RTC_DATE_SHIFT = 12, + RTD1195_MIS_ISR_I2C5_SHIFT = 14, + RTD1195_MIS_ISR_I2C4_SHIFT = 15, + RTD1195_MIS_ISR_GPIOA_SHIFT = 19, + RTD1195_MIS_ISR_GPIODA_SHIFT = 20, + RTD1195_MIS_ISR_LSADC_SHIFT = 21, + RTD1195_MIS_ISR_I2C3_SHIFT = 23, + RTD1195_MIS_ISR_I2C2_SHIFT = 26, + RTD1195_MIS_ISR_GSPI_SHIFT = 27, +}; + +static const u32 rtd1195_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1195_MIS_ISR_UR1_SHIFT] = BIT(3), + [RTD1195_MIS_ISR_I2C1_SHIFT] = BIT(4), + [RTD1195_MIS_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1195_MIS_ISR_RTC_MIN_SHIFT] = BIT(10), + [RTD1195_MIS_ISR_RTC_HOUR_SHIFT] = BIT(11), + [RTD1195_MIS_ISR_RTC_DATE_SHIFT] = BIT(12), + [RTD1195_MIS_ISR_I2C5_SHIFT] = BIT(14), + [RTD1195_MIS_ISR_I2C4_SHIFT] = BIT(15), + [RTD1195_MIS_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1195_MIS_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1195_MIS_ISR_LSADC_SHIFT] = BIT(21), + [RTD1195_MIS_ISR_I2C2_SHIFT] = BIT(26), + [RTD1195_MIS_ISR_GSPI_SHIFT] = BIT(27), + [RTD1195_MIS_ISR_I2C3_SHIFT] = BIT(28), + [RTD1195_MIS_ISR_WDOG_NMI_SHIFT] = SCPU_INT_EN_NMI_MASK, +}; + enum rtd1295_iso_isr_bits { RTD1295_ISO_ISR_UR0_SHIFT = 2, RTD1295_ISO_ISR_IRDA_SHIFT = 5, @@ -238,6 +314,14 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { [RTD1295_MIS_ISR_WDOG_NMI_SHIFT] = SCPU_INT_EN_NMI_MASK, }; +static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = { + .name = "iso", + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1195_iso_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .name = "iso", .isr_offset = 0x0, @@ -246,6 +330,14 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = { + .name = "misc", + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1195_misc_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { .name = "misc", .umsk_isr_offset = 0x8, @@ -255,10 +347,18 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { }; static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { + { + .compatible = "realtek,rtd1195-iso-irq-mux", + .data = &rtd1195_iso_irq_mux_info, + }, { .compatible = "realtek,rtd1295-iso-irq-mux", .data = &rtd1295_iso_irq_mux_info, }, + { + .compatible = "realtek,rtd1195-misc-irq-mux", + .data = &rtd1195_misc_irq_mux_info, + }, { .compatible = "realtek,rtd1295-misc-irq-mux", .data = &rtd1295_misc_irq_mux_info, @@ -323,5 +423,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node, return 0; } +IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init); From patchwork Thu Nov 21 05:02:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11255301 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AED4614C0 for ; Thu, 21 Nov 2019 05:04:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7ACFD20672 for ; Thu, 21 Nov 2019 05:04:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ApSjaHuq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7ACFD20672 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8AxlqQQH+/Jzk1WgxhRzXPswBKaZP2JCjNqeCQFrKTg=; b=ApSjaHuqFhdJH/ Z9QRqUNFmS5nHf6H6tw3ybgw8+jBTjkKkWcncccF5AFv0YhlZt2UrWsUIM/dY8aSF//vWBQMVM6lw 43QEe6xLJnJ1yU69G62SJcHxa5terkuSD4491NhiGKjjJA+9P24fA42MW3sO6o7I1EfNwTM6NUoye Xp1jkSyn5ocTzBF4cKXYJqF9sgaLEo76Wb+oafCbhmWbTHhtiH8jzO+PxQn9Pglc51/cFVi0Ut91o kb6dJqoGQzRmu0JIOS+aKFhZfEbJwntKqcUQFNDRVGZFWHGOUuKNrdNKZ4HMUddZzNBvNWaOvi8GG puDRCb9Kwm6OACxtUW4g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXedi-00060r-3Z; Thu, 21 Nov 2019 05:04:22 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebp-00046S-3J; Thu, 21 Nov 2019 05:02:27 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 7B1F3B052; Thu, 21 Nov 2019 05:02:20 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v5 6/9] ARM: dts: rtd1195: Add irq muxes and UART interrupts Date: Thu, 21 Nov 2019 06:02:05 +0100 Message-Id: <20191121050208.11324-7-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_210225_314323_2AE6E0B1 X-CRM114-Status: UNSURE ( 9.74 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , =?utf-8?q?A?= =?utf-8?q?ndreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add iso and misc IRQ mux DT nodes for the Realtek RTD1195 SoC. Update the UART DT nodes with interrupts from those muxes, so that UART0 can be used without earlycon. Signed-off-by: Andreas Färber --- v4 -> v5: Unchanged v4: New arch/arm/boot/dts/rtd1195.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index db1171c5adfa..ee7761ae4ee0 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -118,6 +118,14 @@ #reset-cells = <1>; }; + iso_irq_mux: interrupt-controller@7000 { + compatible = "realtek,rtd1195-iso-irq-mux"; + reg = <0x7000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + iso_reset: reset-controller@7088 { compatible = "snps,dw-low-reset"; reg = <0x7088 0x4>; @@ -137,6 +145,8 @@ reg-io-width = <4>; resets = <&iso_reset RTD1195_ISO_RSTN_UR0>; clock-frequency = <27000000>; + interrupt-parent = <&iso_irq_mux>; + interrupts = <2>; status = "disabled"; }; @@ -145,6 +155,14 @@ reg = <0x1a200 0x8>; }; + misc_irq_mux: interrupt-controller@1b000 { + compatible = "realtek,rtd1195-misc-irq-mux"; + reg = <0x1b000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + uart1: serial@1b200 { compatible = "snps,dw-apb-uart"; reg = <0x1b200 0x100>; @@ -152,6 +170,8 @@ reg-io-width = <4>; resets = <&reset2 RTD1195_RSTN_UR1>; clock-frequency = <27000000>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <3>; status = "disabled"; }; }; From patchwork Thu Nov 21 05:02:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11255293 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2CB2138C for ; Thu, 21 Nov 2019 05:03:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BE6522084D for ; Thu, 21 Nov 2019 05:03:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="UoE5p6Bm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BE6522084D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yjcYEcLKykmri9owzD/QaXCG12pRg5EoumGP6vPVsT0=; b=UoE5p6Bm7JdUoq GtD4wSXwkmX3zCDqNwYTq29v060acWYC8q1Kwtx39TGg+nXIc8glHotMJpxtug1F6E8DRydpWOsE7 garuWcUq1AnrFMfSNBTHnpGTcpK2G67LjA2dpTICvsqkGnWM+zxTTX3zeUaA/tD4jNVVX75HYK0vU DY+kJoV+YMRFBGKlqvKSWWpYv9zMGwT+YxjWbOgMnM9lbxFzenGjAWXUhaaBDO4L2wwRGkHOCouCN 5vUkA+GoYAm/lREldPFmKKRJHTphhBvOeqlpAh6bUhptXj8gI4oIRWo17/GQBsucVySr6XzrJrRxP KUshvwcJkA9MhDJlfj6Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXect-000525-E0; Thu, 21 Nov 2019 05:03:31 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebp-00046a-A8; Thu, 21 Nov 2019 05:02:27 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id E6FE5B14A; Thu, 21 Nov 2019 05:02:20 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v5 7/9] dt-bindings: interrupt-controller: rtd1195-mux: Add RTD1395 Date: Thu, 21 Nov 2019 06:02:06 +0100 Message-Id: <20191121050208.11324-8-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_210225_536744_DF150E01 X-CRM114-Status: UNSURE ( 8.66 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Rob Herring , Thomas Gleixner , =?utf-8?q?Andreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add compatible strings for Realtek RTD1395 SoC. Signed-off-by: Andreas Färber Acked-by: Rob Herring --- v4 -> v5: Unchanged v4: New .../devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml index 5cf3a28cedba..7c2a31548d46 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtd1195-mux.yaml @@ -19,6 +19,8 @@ properties: - realtek,rtd1195-iso-irq-mux - realtek,rtd1295-misc-irq-mux - realtek,rtd1295-iso-irq-mux + - realtek,rtd1395-misc-irq-mux + - realtek,rtd1395-iso-irq-mux reg: maxItems: 1 From patchwork Thu Nov 21 05:02:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11255295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4AE1B14C0 for ; Thu, 21 Nov 2019 05:03:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C929E20672 for ; Thu, 21 Nov 2019 05:03:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="JTBe9fRJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C929E20672 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zsu2w1VN5HANjOJcMHWUyctbEn+TnojwabdJXyPhf9Q=; b=JTBe9fRJZgEt6N vRDJAUzfBkPFHaOCzKnpvPK+n+LqHqOZj0B7eTrLzy/34YHEICsC7f43XUA2JruyLGlXQGHjKCG1H R5PvxHevuGsbyLR2n2GPglGB0zhZwgWE0ig1zQRLybEoS3cQEHrh56Kt93v3LLJySjYtAsfB4iS0T 9lpGqArWPyLu/LDckp90j8aiwAH/gIqQaPq6zId/rZgNKZXuLLXPPo0ehbB6LO6AlG044h+Y2FEEK zDuJ7IkozHCAz67bhfxm9+qeTCOxQfaxpksHxFhb9zxZAiBVjmCYPi2EnPHojkFhRqy6ccoTuSAiT SX/h3GObSBfkSFHQa1bA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXed3-0005Eh-KS; Thu, 21 Nov 2019 05:03:41 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebp-00046Z-7c; Thu, 21 Nov 2019 05:02:28 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 5B27CB15E; Thu, 21 Nov 2019 05:02:21 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v5 8/9] irqchip: rtd1195-mux: Add RTD1395 definitions Date: Thu, 21 Nov 2019 06:02:07 +0100 Message-Id: <20191121050208.11324-9-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_210225_587563_452AD323 X-CRM114-Status: GOOD ( 10.85 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Thomas Gleixner , =?utf-8?q?Andreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add compatible strings and bit mappings for Realtek RTD1395 SoC. Based on BPI-M4-bsp linux-rtk/drivers/irqchip/irq-rtd139x.h. Signed-off-by: Andreas Färber --- @Realtek: Does RTD1395 still have the WDOG_NMI misc interrupt at bit 2? v4 -> v5: * Renamed misc bits from MISC_ to MIS_ for consistency * Filled in irq_chip names v4: New drivers/irqchip/irq-rtd1195-mux.c | 85 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index e3e2e42d9df2..e0264759c0a8 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Realtek RTD1195/RTD1295 IRQ mux + * Realtek RTD1195/RTD1295/RTD1395 IRQ mux * + * Copyright (C) 2017 Realtek Semiconductor Corporation * Copyright (c) 2017-2019 Andreas Färber */ @@ -314,6 +315,62 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { [RTD1295_MIS_ISR_WDOG_NMI_SHIFT] = SCPU_INT_EN_NMI_MASK, }; +enum rtd1395_iso_isr_bits { + RTD1395_ISO_ISR_UR0_SHIFT = 2, + RTD1395_ISO_ISR_IRDA_SHIFT = 5, + RTD1395_ISO_ISR_I2C0_SHIFT = 8, + RTD1395_ISO_ISR_I2C1_SHIFT = 11, + RTD1395_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1395_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1395_ISO_ISR_LSADC0_SHIFT = 16, + RTD1395_ISO_ISR_LSADC1_SHIFT = 17, + RTD1395_ISO_ISR_GPIOA_SHIFT = 19, + RTD1395_ISO_ISR_GPIODA_SHIFT = 20, + RTD1395_ISO_ISR_GPHY_HV_SHIFT = 28, + RTD1395_ISO_ISR_GPHY_DV_SHIFT = 29, + RTD1395_ISO_ISR_GPHY_AV_SHIFT = 30, + RTD1395_ISO_ISR_I2C1_REQ_SHIFT = 31, +}; + +static const u32 rtd1395_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1395_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1395_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1395_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1395_ISO_ISR_I2C1_SHIFT] = BIT(11), + [RTD1395_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1395_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1395_ISO_ISR_LSADC0_SHIFT] = BIT(16), + [RTD1395_ISO_ISR_LSADC1_SHIFT] = BIT(17), + [RTD1395_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1395_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1395_ISO_ISR_GPHY_HV_SHIFT] = BIT(28), + [RTD1395_ISO_ISR_GPHY_DV_SHIFT] = BIT(29), + [RTD1395_ISO_ISR_GPHY_AV_SHIFT] = BIT(30), + [RTD1395_ISO_ISR_I2C1_REQ_SHIFT] = BIT(31), +}; + +enum rtd1395_misc_isr_bits { + RTD1395_MIS_ISR_UR1_SHIFT = 3, + RTD1395_MIS_ISR_UR1_TO_SHIFT = 5, + RTD1395_MIS_ISR_UR2_SHIFT = 8, + RTD1395_MIS_ISR_UR2_TO_SHIFT = 13, + RTD1395_MIS_ISR_I2C5_SHIFT = 14, + RTD1395_MIS_ISR_SC0_SHIFT = 24, + RTD1395_MIS_ISR_SPI_SHIFT = 27, + RTD1395_MIS_ISR_FAN_SHIFT = 29, +}; + +static const u32 rtd1395_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1395_MIS_ISR_UR1_SHIFT] = BIT(3), + [RTD1395_MIS_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1395_MIS_ISR_UR2_TO_SHIFT] = BIT(6), + [RTD1395_MIS_ISR_UR2_SHIFT] = BIT(7), + [RTD1395_MIS_ISR_I2C5_SHIFT] = BIT(14), + [RTD1395_MIS_ISR_SC0_SHIFT] = BIT(24), + [RTD1395_MIS_ISR_SPI_SHIFT] = BIT(27), + [RTD1395_MIS_ISR_FAN_SHIFT] = BIT(29), +}; + static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = { .name = "iso", .isr_offset = 0x0, @@ -330,6 +387,14 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1395_iso_irq_mux_info = { + .name = "iso", + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1395_iso_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = { .name = "misc", .umsk_isr_offset = 0x8, @@ -346,6 +411,14 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { .isr_to_int_en_mask = rtd1295_misc_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1395_misc_irq_mux_info = { + .name = "misc", + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1395_misc_isr_to_scpu_int_en_mask, +}; + static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { { .compatible = "realtek,rtd1195-iso-irq-mux", @@ -355,6 +428,10 @@ static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { .compatible = "realtek,rtd1295-iso-irq-mux", .data = &rtd1295_iso_irq_mux_info, }, + { + .compatible = "realtek,rtd1395-iso-irq-mux", + .data = &rtd1395_iso_irq_mux_info, + }, { .compatible = "realtek,rtd1195-misc-irq-mux", .data = &rtd1195_misc_irq_mux_info, @@ -363,6 +440,10 @@ static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { .compatible = "realtek,rtd1295-misc-irq-mux", .data = &rtd1295_misc_irq_mux_info, }, + { + .compatible = "realtek,rtd1395-misc-irq-mux", + .data = &rtd1395_misc_irq_mux_info, + }, { } }; @@ -425,5 +506,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node, } IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1395_iso_mux, "realtek,rtd1395-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1395_misc_mux, "realtek,rtd1395-misc-irq-mux", rtd1195_irq_mux_init); From patchwork Thu Nov 21 05:02:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11255303 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CD4ED138C for ; Thu, 21 Nov 2019 05:04:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9511220672 for ; Thu, 21 Nov 2019 05:04:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="aMbI3AFy" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9511220672 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4ZeE0GVFEWGJsTZ5Fvj5XkQnZBcuFeFcoIt9K7zmjQ8=; b=aMbI3AFye1U/3n OjzFCedLEIAN+iCehtI/pgojvfY82jghaMebmD+/OLasm5WUp3n/Nscdxj3rCEXPVTV0Y4gS0hQaG OUzh1BStZ7Qwh3taSAGOVsBf7hdRImaip7hH0d5dsFy9qRIIvh9d5CYVBs9WKD7ZBEcNec+IC9bID LlEclCI/SLPmUSW0a0i5U+8nIGmLUf0Kc5vL3lOL7RcGK0dIy5Dht08t07ZBcK1ho4J0XgHkbqsBL Xn1jbg+BRSlLhuPRAKtkXehKVxLqjTElAQvyJcOP0ZyeEY3j5VajcwuArDSOrhFu4srm9Dk6ZRqR4 UpEE8+XExyqsBiMMmBlg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXedy-0006HU-T1; Thu, 21 Nov 2019 05:04:38 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iXebr-000486-6V; Thu, 21 Nov 2019 05:02:29 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id C0F52B183; Thu, 21 Nov 2019 05:02:21 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v5 9/9] arm64: dts: realtek: rtd139x: Add irq muxes and UART interrupts Date: Thu, 21 Nov 2019 06:02:08 +0100 Message-Id: <20191121050208.11324-10-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191121050208.11324-1-afaerber@suse.de> References: <20191121050208.11324-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_210227_419200_F4A78165 X-CRM114-Status: UNSURE ( 9.41 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , =?utf-8?q?A?= =?utf-8?q?ndreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add iso and misc IRQ mux DT nodes for Realtek RTD1395 SoC. Update the UART DT nodes with interrupts from these muxes, so that UART0 can be used without earlycon. Signed-off-by: Andreas Färber --- v4 -> v5: Unchanged v4: New arch/arm64/boot/dts/realtek/rtd139x.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi index 706da12f9ea3..f53cb8a5083b 100644 --- a/arch/arm64/boot/dts/realtek/rtd139x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi @@ -84,6 +84,14 @@ #reset-cells = <1>; }; + iso_irq_mux: interrupt-controller@7000 { + compatible = "realtek,rtd1395-iso-irq-mux"; + reg = <0x7000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + iso_reset: reset-controller@7088 { compatible = "snps,dw-low-reset"; reg = <0x7088 0x4>; @@ -103,6 +111,8 @@ reg-io-width = <4>; clock-frequency = <27000000>; resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + interrupt-parent = <&iso_irq_mux>; + interrupts = <2>; status = "disabled"; }; @@ -111,6 +121,14 @@ reg = <0x1a200 0x8>; }; + misc_irq_mux: interrupt-controller@1b000 { + compatible = "realtek,rtd1395-misc-irq-mux"; + reg = <0x1b000 0x100>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + uart1: serial@1b200 { compatible = "snps,dw-apb-uart"; reg = <0x1b200 0x100>; @@ -118,6 +136,8 @@ reg-io-width = <4>; clock-frequency = <432000000>; resets = <&reset2 RTD1295_RSTN_UR1>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <3>; status = "disabled"; }; @@ -128,6 +148,8 @@ reg-io-width = <4>; clock-frequency = <432000000>; resets = <&reset2 RTD1295_RSTN_UR2>; + interrupt-parent = <&misc_irq_mux>; + interrupts = <8>; status = "disabled"; }; };