From patchwork Fri Nov 22 06:55:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11257279 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C2AE614C0 for ; Fri, 22 Nov 2019 07:11:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AACD4205C9 for ; Fri, 22 Nov 2019 07:11:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726563AbfKVHLD (ORCPT ); Fri, 22 Nov 2019 02:11:03 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:61411 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726546AbfKVHLD (ORCPT ); Fri, 22 Nov 2019 02:11:03 -0500 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Fri, 22 Nov 2019 02:11:01 EST Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 22 Nov 2019 14:56:24 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Felipe Balbi , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH 1/6] dt-bindings: phy: Add Amlogic G12A USB2 PHY Bindings Date: Fri, 22 Nov 2019 14:55:52 +0800 Message-ID: <1574405757-76184-2-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> References: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add the Amlogic A1 Family USB2 PHY Bindings It supports Host mode only. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- .../bindings/phy/amlogic,meson-a1-usb2-phy.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml new file mode 100644 index 00000000..7a66e8a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Amlogic, Inc +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/amlogic,meson-a1-usb2-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic A1 USB2 PHY + +maintainers: + - Yue Wang + +properties: + compatible: + enum: + - amlogic,meson-a1-usb2-phy + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: phy + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 1 + description: + a phandle to respective power domain node as described by generic + PM domain bindings (see power/power_domain.txt for more information). + +required: + - compatible + - reg + - resets + - reset-names + - "#phy-cells" + - power-domains + +examples: + - | + usb2_phy0: phy@40000 { + status = "okay"; + compatible = "amlogic,a1-usb2-phy"; + reg = <0x0 0x40000 0x0 0x2000>; + resets = <&reset RESET_USBPHY>; + reset-names = "phy"; + #phy-cells = <0>; + power-domains = <&pwrc PWRC_USB_ID>; + }; From patchwork Fri Nov 22 06:55:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11257281 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05C4914C0 for ; Fri, 22 Nov 2019 07:11:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E44532071B for ; Fri, 22 Nov 2019 07:11:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726574AbfKVHLG (ORCPT ); Fri, 22 Nov 2019 02:11:06 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:61411 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726540AbfKVHLG (ORCPT ); Fri, 22 Nov 2019 02:11:06 -0500 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Fri, 22 Nov 2019 02:11:01 EST Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 22 Nov 2019 14:56:24 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Felipe Balbi , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH 2/6] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings Date: Fri, 22 Nov 2019 14:55:53 +0800 Message-ID: <1574405757-76184-3-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> References: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The Amlogic A1 SoC Family embeds 1 USB Controllers: - a DWC3 IP configured as Host for USB2 and USB3 A glue connects the controllers to the USB2 PHY of A1 SoC. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- .../devicetree/bindings/usb/amlogic,dwc3.txt | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt index 6ffb09b..63dc60b 100644 --- a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt +++ b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt @@ -128,3 +128,56 @@ Example device nodes: snps,quirk-frame-length-adjustment; }; }; + +Amlogic Meson A1 DWC3 USB SoC Controller Glue + +The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in +host-only mode. + +Required properties: +- compatible: Should be "amlogic,meson-a1-usb-ctrl" +- clocks: The clocks needed by the usb controller +- clock-names: Should contain the name of the clocks: "usb_ctrl", "usb_bus", + "xtal_usb_phy", "xtal_usb_ctrl" +- resets: a handle for the shared "USB" reset line +- reg: The base address and length of the registers +- phys: handle to used PHYs on the system + - a <0> phandle can be used if a PHY is not used +- phy-names: names of the used PHYs on the system : + - "usb2-phy0" for USB2 PHY if USBHOST port is used + +Required child nodes: + +A child node must exist to represent the core DWC3 IP block. The name of +the node is not important. The content of the node is defined in dwc3.txt. + +PHY documentation is provided in the following places: +- Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml + +Example device nodes: + usb: usb@ffe09000 { + status = "okay"; + compatible = "amlogic,meson-a1-usb-ctrl"; + reg = <0x0 0xffe09000 0x0 0xa0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc_periphs CLKID_USB_CTRL>, + <&clkc_periphs CLKID_USB_BUS>, + <&clkc_periphs CLKID_XTAL_USB_PHY>, + <&clkc_periphs CLKID_XTAL_USB_CTRL>; + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_phy", "xtal_usb_ctrl"; + resets = <&reset RESET_USBCTRL>; + phys = <&usb2_phy0>; + phy-names = "usb2-phy0"; + + dwc3: usb@ff400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff400000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + }; + }; From patchwork Fri Nov 22 06:55:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11257283 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9CEB714C0 for ; Fri, 22 Nov 2019 07:11:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7374D20714 for ; Fri, 22 Nov 2019 07:11:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726613AbfKVHLM (ORCPT ); Fri, 22 Nov 2019 02:11:12 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:61411 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726568AbfKVHLM (ORCPT ); Fri, 22 Nov 2019 02:11:12 -0500 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Fri, 22 Nov 2019 02:11:01 EST Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 22 Nov 2019 14:56:25 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Felipe Balbi , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver Date: Fri, 22 Nov 2019 14:55:54 +0800 Message-ID: <1574405757-76184-4-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> References: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org This adds support for the USB2 PHY found in the Amlogic A1 SoC Family. It supports host mode only. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- drivers/phy/amlogic/Kconfig | 13 ++ drivers/phy/amlogic/Makefile | 1 + drivers/phy/amlogic/phy-meson-a1-usb2.c | 327 ++++++++++++++++++++++++++++++++ 3 files changed, 341 insertions(+) create mode 100644 drivers/phy/amlogic/phy-meson-a1-usb2.c diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig index af774ac..5b5affb 100644 --- a/drivers/phy/amlogic/Kconfig +++ b/drivers/phy/amlogic/Kconfig @@ -38,6 +38,19 @@ config PHY_MESON_GXL_USB3 IP block found in Meson GXL and GXM SoCs. If unsure, say N. +config PHY_MESON_A1_USB2 + tristate "Meson A1 USB2 PHY driver" + default ARCH_MESON + depends on OF && (ARCH_MESON || COMPILE_TEST) + select GENERIC_PHY + select REGMAP_MMIO + help + Enable this to support the Meson USB2 PHY found in Meson + A1 SoCs. + The MESON A1 USB2 PHY support a DWC3 USB IP Core configured + for USB2 in host-only mode. + If unsure, say N. + config PHY_MESON_G12A_USB2 tristate "Meson G12A USB2 PHY driver" default ARCH_MESON diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile index 11d1c42..c9031c5 100644 --- a/drivers/phy/amlogic/Makefile +++ b/drivers/phy/amlogic/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o +obj-$(CONFIG_PHY_MESON_A1_USB2) += phy-meson-a1-usb2.o obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o diff --git a/drivers/phy/amlogic/phy-meson-a1-usb2.c b/drivers/phy/amlogic/phy-meson-a1-usb2.c new file mode 100644 index 00000000..28148b6 --- /dev/null +++ b/drivers/phy/amlogic/phy-meson-a1-usb2.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Meson A1 USB2 PHY driver + * + * Copyright (C) 2017 Martin Blumenstingl + * Copyright (C) 2019 Amlogic, Inc. All rights reserved + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY_CTRL_R0 0x0 +#define PHY_CTRL_R1 0x4 +#define PHY_CTRL_R2 0x8 +#define PHY_CTRL_R3 0xc + #define PHY_CTRL_R3_SQUELCH_REF GENMASK(1, 0) + #define PHY_CTRL_R3_HSDIC_REF GENMASK(3, 2) + #define PHY_CTRL_R3_DISC_THRESH GENMASK(7, 4) + +#define PHY_CTRL_R4 0x10 + #define PHY_CTRL_R4_CALIB_CODE_7_0 GENMASK(7, 0) + #define PHY_CTRL_R4_CALIB_CODE_15_8 GENMASK(15, 8) + #define PHY_CTRL_R4_CALIB_CODE_23_16 GENMASK(23, 16) + #define PHY_CTRL_R4_I_C2L_CAL_EN BIT(24) + #define PHY_CTRL_R4_I_C2L_CAL_RESET_N BIT(25) + #define PHY_CTRL_R4_I_C2L_CAL_DONE BIT(26) + #define PHY_CTRL_R4_TEST_BYPASS_MODE_EN BIT(27) + #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0 GENMASK(29, 28) + #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2 GENMASK(31, 30) + +#define PHY_CTRL_R5 0x14 +#define PHY_CTRL_R6 0x18 +#define PHY_CTRL_R7 0x1c +#define PHY_CTRL_R8 0x20 +#define PHY_CTRL_R9 0x24 +#define PHY_CTRL_R10 0x28 +#define PHY_CTRL_R11 0x2c +#define PHY_CTRL_R12 0x30 +#define PHY_CTRL_R13 0x34 + #define PHY_CTRL_R13_CUSTOM_PATTERN_19 GENMASK(7, 0) + #define PHY_CTRL_R13_LOAD_STAT BIT(14) + #define PHY_CTRL_R13_UPDATE_PMA_SIGNALS BIT(15) + #define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET GENMASK(20, 16) + #define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT BIT(21) + #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL BIT(22) + #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN BIT(23) + #define PHY_CTRL_R13_I_C2L_HS_EN BIT(24) + #define PHY_CTRL_R13_I_C2L_FS_EN BIT(25) + #define PHY_CTRL_R13_I_C2L_LS_EN BIT(26) + #define PHY_CTRL_R13_I_C2L_HS_OE BIT(27) + #define PHY_CTRL_R13_I_C2L_FS_OE BIT(28) + #define PHY_CTRL_R13_I_C2L_HS_RX_EN BIT(29) + #define PHY_CTRL_R13_I_C2L_FSLS_RX_EN BIT(30) + +#define PHY_CTRL_R14 0x38 + #define PHY_CTRL_R14_I_RDP_EN BIT(0) + #define PHY_CTRL_R14_I_RPU_SW1_EN BIT(1) + #define PHY_CTRL_R14_I_RPU_SW2_EN GENMASK(2, 3) + #define PHY_CTRL_R14_PG_RSTN BIT(4) + #define PHY_CTRL_R14_I_C2L_DATA_16_8 BIT(5) + #define PHY_CTRL_R14_I_C2L_ASSERT_SINGLE_EN_ZERO BIT(6) + #define PHY_CTRL_R14_BYPASS_CTRL_7_0 GENMASK(15, 8) + #define PHY_CTRL_R14_BYPASS_CTRL_15_8 GENMASK(23, 16) + +#define PHY_CTRL_R15 0x3c +#define PHY_CTRL_R16 0x40 + #define PHY_CTRL_R16_MPLL_M GENMASK(8, 0) + #define PHY_CTRL_R16_MPLL_N GENMASK(14, 10) + #define PHY_CTRL_R16_MPLL_TDC_MODE BIT(20) + #define PHY_CTRL_R16_MPLL_SDM_EN BIT(21) + #define PHY_CTRL_R16_MPLL_LOAD BIT(22) + #define PHY_CTRL_R16_MPLL_DCO_SDM_EN BIT(23) + #define PHY_CTRL_R16_MPLL_LOCK_LONG GENMASK(25, 24) + #define PHY_CTRL_R16_MPLL_LOCK_F BIT(26) + #define PHY_CTRL_R16_MPLL_FAST_LOCK BIT(27) + #define PHY_CTRL_R16_MPLL_EN BIT(28) + #define PHY_CTRL_R16_MPLL_RESET BIT(29) + #define PHY_CTRL_R16_MPLL_LOCK BIT(30) + #define PHY_CTRL_R16_MPLL_LOCK_DIG BIT(31) + +#define PHY_CTRL_R17 0x44 + #define PHY_CTRL_R17_MPLL_FRAC_IN GENMASK(13, 0) + #define PHY_CTRL_R17_MPLL_FIX_EN BIT(16) + #define PHY_CTRL_R17_MPLL_LAMBDA1 GENMASK(19, 17) + #define PHY_CTRL_R17_MPLL_LAMBDA0 GENMASK(22, 20) + #define PHY_CTRL_R17_MPLL_FILTER_MODE BIT(23) + #define PHY_CTRL_R17_MPLL_FILTER_PVT2 GENMASK(27, 24) + #define PHY_CTRL_R17_MPLL_FILTER_PVT1 GENMASK(31, 28) + +#define PHY_CTRL_R18 0x48 + #define PHY_CTRL_R18_MPLL_LKW_SEL GENMASK(1, 0) + #define PHY_CTRL_R18_MPLL_LK_W GENMASK(5, 2) + #define PHY_CTRL_R18_MPLL_LK_S GENMASK(11, 6) + #define PHY_CTRL_R18_MPLL_DCO_M_EN BIT(12) + #define PHY_CTRL_R18_MPLL_DCO_CLK_SEL BIT(13) + #define PHY_CTRL_R18_MPLL_PFD_GAIN GENMASK(15, 14) + #define PHY_CTRL_R18_MPLL_ROU GENMASK(18, 16) + #define PHY_CTRL_R18_MPLL_DATA_SEL GENMASK(21, 19) + #define PHY_CTRL_R18_MPLL_BIAS_ADJ GENMASK(23, 22) + #define PHY_CTRL_R18_MPLL_BB_MODE GENMASK(25, 24) + #define PHY_CTRL_R18_MPLL_ALPHA GENMASK(28, 26) + #define PHY_CTRL_R18_MPLL_ADJ_LDO GENMASK(30, 29) + #define PHY_CTRL_R18_MPLL_ACG_RANGE BIT(31) + +#define PHY_CTRL_R19 0x4c +#define PHY_CTRL_R20 0x50 + #define PHY_CTRL_R20_USB2_IDDET_EN BIT(0) + #define PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0 GENMASK(3, 1) + #define PHY_CTRL_R20_USB2_OTG_VBUSDET_EN BIT(4) + #define PHY_CTRL_R20_USB2_AMON_EN BIT(5) + #define PHY_CTRL_R20_USB2_CAL_CODE_R5 BIT(6) + #define PHY_CTRL_R20_BYPASS_OTG_DET BIT(7) + #define PHY_CTRL_R20_USB2_DMON_EN BIT(8) + #define PHY_CTRL_R20_USB2_DMON_SEL_3_0 GENMASK(12, 9) + #define PHY_CTRL_R20_USB2_EDGE_DRV_EN BIT(13) + #define PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0 GENMASK(15, 14) + #define PHY_CTRL_R20_USB2_BGR_ADJ_4_0 GENMASK(20, 16) + #define PHY_CTRL_R20_USB2_BGR_START BIT(21) + #define PHY_CTRL_R20_USB2_BGR_VREF_4_0 GENMASK(28, 24) + #define PHY_CTRL_R20_USB2_BGR_DBG_1_0 GENMASK(30, 29) + #define PHY_CTRL_R20_BYPASS_CAL_DONE_R5 BIT(31) + +#define PHY_CTRL_R21 0x54 + #define PHY_CTRL_R21_USB2_BGR_FORCE BIT(0) + #define PHY_CTRL_R21_USB2_CAL_ACK_EN BIT(1) + #define PHY_CTRL_R21_USB2_OTG_ACA_EN BIT(2) + #define PHY_CTRL_R21_USB2_TX_STRG_PD BIT(3) + #define PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0 GENMASK(5, 4) + #define PHY_CTRL_R21_BYPASS_UTMI_CNTR GENMASK(15, 6) + #define PHY_CTRL_R21_BYPASS_UTMI_REG GENMASK(25, 20) + +#define PHY_CTRL_R22 0x58 +#define PHY_CTRL_R23 0x5c + +#define RESET_COMPLETE_TIME 1000 +#define PLL_RESET_COMPLETE_TIME 100 + +struct phy_meson_a1_usb2_priv { + struct device *dev; + struct regmap *regmap; + struct reset_control *reset; +}; + +static const struct regmap_config phy_meson_a1_usb2_regmap_conf = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = PHY_CTRL_R23, +}; + +static int phy_meson_a1_usb2_init(struct phy *phy) +{ + struct phy_meson_a1_usb2_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = reset_control_reset(priv->reset); + if (ret) + return ret; + + udelay(RESET_COMPLETE_TIME); + + /* usb2_otg_aca_en == 0 */ + regmap_update_bits(priv->regmap, PHY_CTRL_R21, + PHY_CTRL_R21_USB2_OTG_ACA_EN, 0); + + /* PLL Setup : 24MHz * 20 / 1 = 480MHz */ + regmap_write(priv->regmap, PHY_CTRL_R16, + FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | + FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | + PHY_CTRL_R16_MPLL_LOAD | + FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) | + PHY_CTRL_R16_MPLL_FAST_LOCK | + PHY_CTRL_R16_MPLL_EN | + PHY_CTRL_R16_MPLL_RESET); + + regmap_write(priv->regmap, PHY_CTRL_R17, + FIELD_PREP(PHY_CTRL_R17_MPLL_FRAC_IN, 0) | + FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA1, 7) | + FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA0, 7) | + FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) | + FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9)); + + regmap_write(priv->regmap, PHY_CTRL_R18, + FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) | + FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) | + FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) | + FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) | + FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) | + FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) | + FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) | + FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) | + PHY_CTRL_R18_MPLL_ACG_RANGE | + PHY_CTRL_R18_MPLL_DCO_CLK_SEL); + + udelay(PLL_RESET_COMPLETE_TIME); + + /* UnReset PLL */ + regmap_write(priv->regmap, PHY_CTRL_R16, + FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | + FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | + PHY_CTRL_R16_MPLL_LOAD | + FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) | + PHY_CTRL_R16_MPLL_FAST_LOCK | + PHY_CTRL_R16_MPLL_EN); + + /* PHY Tuning */ + regmap_write(priv->regmap, PHY_CTRL_R20, + FIELD_PREP(PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0, 4) | + PHY_CTRL_R20_USB2_OTG_VBUSDET_EN | + FIELD_PREP(PHY_CTRL_R20_USB2_DMON_SEL_3_0, 15) | + PHY_CTRL_R20_USB2_EDGE_DRV_EN | + FIELD_PREP(PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0, 3) | + FIELD_PREP(PHY_CTRL_R20_USB2_BGR_ADJ_4_0, 0) | + FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) | + FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0)); + + regmap_write(priv->regmap, PHY_CTRL_R21, + PHY_CTRL_R21_USB2_CAL_ACK_EN | + PHY_CTRL_R21_USB2_TX_STRG_PD | + FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2)); + + /* Analog Settings */ + regmap_write(priv->regmap, PHY_CTRL_R13, + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7)); + + /* Tuning Disconnect Threshold */ + regmap_write(priv->regmap, PHY_CTRL_R3, + FIELD_PREP(PHY_CTRL_R3_SQUELCH_REF, 0) | + FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) | + FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3)); + + return 0; +} + +static int phy_meson_a1_usb2_exit(struct phy *phy) +{ + struct phy_meson_a1_usb2_priv *priv = phy_get_drvdata(phy); + + return reset_control_reset(priv->reset); +} + +/* set_mode is not needed, mode setting is handled via the UTMI bus */ +static const struct phy_ops phy_meson_a1_usb2_ops = { + .init = phy_meson_a1_usb2_init, + .exit = phy_meson_a1_usb2_exit, + .owner = THIS_MODULE, +}; + +static int phy_meson_a1_usb2_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *phy_provider; + struct phy_meson_a1_usb2_priv *priv; + struct phy *phy; + void __iomem *base; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + platform_set_drvdata(pdev, priv); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->regmap = devm_regmap_init_mmio(dev, base, + &phy_meson_a1_usb2_regmap_conf); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + priv->reset = devm_reset_control_get(dev, "phy"); + if (IS_ERR(priv->reset)) + return PTR_ERR(priv->reset); + + ret = reset_control_deassert(priv->reset); + if (ret) + return ret; + + phy = devm_phy_create(dev, NULL, &phy_meson_a1_usb2_ops); + if (IS_ERR(phy)) { + ret = PTR_ERR(phy); + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to create PHY\n"); + + return ret; + } + + phy_set_bus_width(phy, 8); + phy_set_drvdata(phy, priv); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id phy_meson_a1_usb2_of_match[] = { + { .compatible = "amlogic,a1-usb2-phy", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, phy_meson_a1_usb2_of_match); + +static struct platform_driver phy_meson_a1_usb2_driver = { + .probe = phy_meson_a1_usb2_probe, + .driver = { + .name = "phy-meson-a1-usb2", + .of_match_table = phy_meson_a1_usb2_of_match, + }, +}; +module_platform_driver(phy_meson_a1_usb2_driver); + +MODULE_AUTHOR("Yue Wang "); +MODULE_DESCRIPTION("Meson A1 USB2 PHY driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Nov 22 06:55:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11257285 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B43C8138C for ; Fri, 22 Nov 2019 07:11:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9518E20715 for ; Fri, 22 Nov 2019 07:11:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726638AbfKVHLO (ORCPT ); Fri, 22 Nov 2019 02:11:14 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:61411 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726620AbfKVHLO (ORCPT ); Fri, 22 Nov 2019 02:11:14 -0500 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Fri, 22 Nov 2019 02:11:01 EST Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 22 Nov 2019 14:56:25 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Felipe Balbi , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue Date: Fri, 22 Nov 2019 14:55:55 +0800 Message-ID: <1574405757-76184-5-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> References: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Adds support for Amlogic A1 USB Control Glue HW. The Amlogic A1 SoC Family embeds 1 USB Controllers: - a DWC3 IP configured as Host for USB2 and USB3 A glue connects the controllers to the USB2 PHY of A1 SoC. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- drivers/usb/dwc3/Kconfig | 11 ++ drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-meson-a1.c | 397 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 409 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-meson-a1.c diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 556a876..9bfb159 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -96,6 +96,17 @@ config USB_DWC3_KEYSTONE Support of USB2/3 functionality in TI Keystone2 and AM654 platforms. Say 'Y' or 'M' here if you have one such device +config USB_DWC3_MESON_A1 + tristate "Amlogic Meson A1 Platforms" + depends on OF && COMMON_CLK + depends on ARCH_MESON || COMPILE_TEST + default USB_DWC3 + help + Support USB2 functionality in MESON A1 platforms. + The MESON A1 USB2 support a DWC3 USB IP Core configured for USB2 in + host-only mode. + Say 'Y' or 'M' if you have one such device. + config USB_DWC3_MESON_G12A tristate "Amlogic Meson G12A Platforms" depends on OF && COMMON_CLK diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index ae86da0..a3fc655 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o obj-$(CONFIG_USB_DWC3_HAPS) += dwc3-haps.o obj-$(CONFIG_USB_DWC3_KEYSTONE) += dwc3-keystone.o +obj-$(CONFIG_USB_DWC3_MESON_A1) += dwc3-meson-a1.o obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o diff --git a/drivers/usb/dwc3/dwc3-meson-a1.c b/drivers/usb/dwc3/dwc3-meson-a1.c new file mode 100644 index 00000000..db2b99a --- /dev/null +++ b/drivers/usb/dwc3/dwc3-meson-a1.c @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * USB Glue for Amlogic A1 SoCs + * + * Copyright (c) 2019 Amlogic, Inc. All rights reserved + * Author: Yue Wang + */ + +/* + * The USB is organized with a glue around the DWC3 Controller IP as : + * - Control registers for each USB2 Ports + * - Control registers for the USB PHY layer + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* USB2 Ports Control Registers */ +#define U2P_R0 0x20 + #define U2P_R0_HOST_DEVICE BIT(0) + #define U2P_R0_POWER_OK BIT(1) + #define U2P_R0_HAST_MODE BIT(2) + #define U2P_R0_POWER_ON_RESET BIT(3) + #define U2P_R0_ID_PULLUP BIT(4) + #define U2P_R0_DRV_VBUS BIT(5) + +#define U2P_R1 0x24 + #define U2P_R1_PHY_READY BIT(0) + #define U2P_R1_ID_DIG BIT(1) + #define U2P_R1_OTG_SESSION_VALID BIT(2) + #define U2P_R1_VBUS_VALID BIT(3) + +/* USB Glue Control Registers */ + +#define USB_R0 0x80 + #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) + #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) + #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19) + #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29) + #define USB_R0_U2D_ACT BIT(31) + +#define USB_R1 0x84 + #define USB_R1_U3H_BIGENDIAN_GS BIT(0) + #define USB_R1_U3H_PME_ENABLE BIT(1) + #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2) + #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(9, 7) + #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(13, 12) + #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16) + #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17) + #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18) + #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19) + #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25) + +#define USB_R2 0x88 + #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20) + #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26) + +#define USB_R3 0x8c + #define USB_R3_P30_SSC_ENABLE BIT(0) + #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1) + #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4) + #define USB_R3_P30_REF_SSP_EN BIT(13) + +#define USB_R4 0x90 + #define USB_R4_P21_PORT_RESET_0 BIT(0) + #define USB_R4_P21_SLEEP_M0 BIT(1) + #define USB_R4_MEM_PD_MASK GENMASK(3, 2) + #define USB_R4_P21_ONLY BIT(4) + +#define USB_R5 0x94 + #define USB_R5_ID_DIG_SYNC BIT(0) + #define USB_R5_ID_DIG_REG BIT(1) + #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2) + #define USB_R5_ID_DIG_EN_0 BIT(4) + #define USB_R5_ID_DIG_EN_1 BIT(5) + #define USB_R5_ID_DIG_CURR BIT(6) + #define USB_R5_ID_DIG_IRQ BIT(7) + #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8) + #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16) + +static const char *phy_names = { + "usb2-phy0", +}; + +struct dwc3_meson_a1 { + struct device *dev; + struct regmap *regmap; + struct clk *clk_usb_ctrl; + struct clk *clk_usb_bus; + struct clk *clk_xtal_usb_phy; + struct clk *clk_xtal_usb_ctrl; + struct reset_control *reset; + struct phy *phys; + unsigned int usb2_ports; +}; + +static void dwc3_meson_a1_usb_init(struct dwc3_meson_a1 *priv) +{ + regmap_update_bits(priv->regmap, U2P_R0, + U2P_R0_POWER_ON_RESET, + U2P_R0_POWER_ON_RESET); + + regmap_update_bits(priv->regmap, U2P_R0, + U2P_R0_HOST_DEVICE, + U2P_R0_HOST_DEVICE); + + regmap_update_bits(priv->regmap, U2P_R0, + U2P_R0_POWER_ON_RESET, 0); + + regmap_update_bits(priv->regmap, USB_R1, + USB_R1_U3H_FLADJ_30MHZ_REG_MASK, + FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20)); + + regmap_update_bits(priv->regmap, USB_R0, + USB_R0_U2D_ACT, 0); + + regmap_update_bits(priv->regmap, USB_R4, + USB_R4_P21_SLEEP_M0, 0); +} + +static const struct regmap_config phy_meson_a1_usb_regmap_conf = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = USB_R5, +}; + +static int dwc3_meson_a1_get_phys(struct dwc3_meson_a1 *priv) +{ + priv->phys = devm_phy_optional_get(priv->dev, phy_names); + if (IS_ERR(priv->phys)) + return PTR_ERR(priv->phys); + + priv->usb2_ports++; + + dev_info(priv->dev, "USB2 ports: %d\n", priv->usb2_ports); + + return 0; +} + +static int dwc3_meson_a1_enable_clk(struct dwc3_meson_a1 *priv) +{ + int ret; + + ret = clk_prepare_enable(priv->clk_usb_ctrl); + if (ret < 0) { + dev_err(priv->dev, "can't enable usb_ctrl clock.\n"); + return ret; + } + + ret = clk_prepare_enable(priv->clk_usb_bus); + if (ret < 0) { + dev_err(priv->dev, "can't enable usb_bus clock.\n"); + goto disable_clk_usb_ctrl; + } + + ret = clk_prepare_enable(priv->clk_xtal_usb_phy); + if (ret < 0) { + dev_err(priv->dev, "can't enable xtal_usb_phy clock.\n"); + goto disable_clk_usb_bus; + } + + ret = clk_prepare_enable(priv->clk_xtal_usb_ctrl); + if (ret < 0) { + dev_err(priv->dev, "can't enable xtal_usb_ctrl clock.\n"); + goto disable_clk_xtal_usb_phy; + } + + return 0; + +disable_clk_xtal_usb_phy: + clk_disable_unprepare(priv->clk_xtal_usb_phy); +disable_clk_usb_bus: + clk_disable_unprepare(priv->clk_usb_bus); +disable_clk_usb_ctrl: + clk_disable_unprepare(priv->clk_usb_ctrl); + + return ret; +} + +static void dwc3_meson_a1_disable_clk(struct dwc3_meson_a1 *priv) +{ + clk_disable_unprepare(priv->clk_usb_ctrl); + clk_disable_unprepare(priv->clk_usb_bus); + clk_disable_unprepare(priv->clk_xtal_usb_phy); + clk_disable_unprepare(priv->clk_xtal_usb_ctrl); +} + +static int dwc3_meson_a1_setup_clk(struct dwc3_meson_a1 *priv) +{ + int ret; + + priv->clk_usb_ctrl = devm_clk_get(priv->dev, "usb_ctrl"); + if (IS_ERR(priv->clk_usb_ctrl)) { + dev_err(priv->dev, "can't get usb_ctrl clock.\n"); + return PTR_ERR(priv->clk_usb_ctrl); + } + + priv->clk_usb_bus = devm_clk_get(priv->dev, "usb_bus"); + if (IS_ERR(priv->clk_usb_bus)) { + dev_err(priv->dev, "can't get usb_bus clock.\n"); + return PTR_ERR(priv->clk_usb_bus); + } + + priv->clk_xtal_usb_phy = devm_clk_get(priv->dev, "xtal_usb_phy"); + if (IS_ERR(priv->clk_xtal_usb_phy)) { + dev_err(priv->dev, "can't get xtal_usb_phy clock.\n"); + return PTR_ERR(priv->clk_xtal_usb_phy); + } + + priv->clk_xtal_usb_ctrl = devm_clk_get(priv->dev, "xtal_usb_ctrl"); + if (IS_ERR(priv->clk_xtal_usb_ctrl)) { + dev_err(priv->dev, "can't get xtal_usb_ctrl clock.\n"); + return PTR_ERR(priv->clk_xtal_usb_ctrl); + } + + ret = dwc3_meson_a1_enable_clk(priv); + if (ret) + return ret; + + devm_add_action_or_reset(priv->dev, + (void(*)(void *))clk_disable_unprepare, + priv->clk_usb_ctrl); + devm_add_action_or_reset(priv->dev, + (void(*)(void *))clk_disable_unprepare, + priv->clk_usb_bus); + devm_add_action_or_reset(priv->dev, + (void(*)(void *))clk_disable_unprepare, + priv->clk_xtal_usb_phy); + devm_add_action_or_reset(priv->dev, + (void(*)(void *))clk_disable_unprepare, + priv->clk_xtal_usb_ctrl); + + return 0; +} + +static int dwc3_meson_a1_probe(struct platform_device *pdev) +{ + struct dwc3_meson_a1 *priv; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *base; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + priv->dev = dev; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->regmap = devm_regmap_init_mmio(dev, base, + &phy_meson_a1_usb_regmap_conf); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + ret = dwc3_meson_a1_setup_clk(priv); + if (ret) + return ret; + + priv->reset = devm_reset_control_get(dev, NULL); + if (IS_ERR(priv->reset)) { + ret = PTR_ERR(priv->reset); + dev_err(dev, "failed to get device reset, err=%d\n", ret); + return ret; + } + + ret = reset_control_reset(priv->reset); + if (ret) + return ret; + + ret = dwc3_meson_a1_get_phys(priv); + if (ret) + return ret; + + dwc3_meson_a1_usb_init(priv); + + /* Init PHYs */ + ret = phy_init(priv->phys); + if (ret) + return ret; + + /* Set PHY Power */ + ret = phy_power_on(priv->phys); + if (ret) + goto err_phys_exit; + + ret = of_platform_populate(np, NULL, NULL, dev); + if (ret) + goto err_phys_power; + + return 0; + +err_phys_power: + phy_power_off(priv->phys); + +err_phys_exit: + phy_exit(priv->phys); + + return ret; +} + +static int dwc3_meson_a1_remove(struct platform_device *pdev) +{ + struct dwc3_meson_a1 *priv = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + + of_platform_depopulate(dev); + + phy_power_off(priv->phys); + phy_exit(priv->phys); + + return 0; +} + +static int __maybe_unused dwc3_meson_a1_suspend(struct device *dev) +{ + struct dwc3_meson_a1 *priv = dev_get_drvdata(dev); + + phy_power_off(priv->phys); + phy_exit(priv->phys); + + reset_control_assert(priv->reset); + + dwc3_meson_a1_disable_clk(priv); + + return 0; +} + +static int __maybe_unused dwc3_meson_a1_resume(struct device *dev) +{ + struct dwc3_meson_a1 *priv = dev_get_drvdata(dev); + int ret; + + ret = dwc3_meson_a1_enable_clk(priv); + if (ret) + return ret; + + reset_control_deassert(priv->reset); + + dwc3_meson_a1_usb_init(priv); + + /* Init PHYs */ + ret = phy_init(priv->phys); + if (ret) + return ret; + + /* Set PHY Power */ + ret = phy_power_on(priv->phys); + if (ret) + return ret; + + return 0; +} + +static const struct dev_pm_ops dwc3_meson_a1_dev_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(dwc3_meson_a1_suspend, dwc3_meson_a1_resume) +}; + +static const struct of_device_id dwc3_meson_a1_match[] = { + { .compatible = "amlogic,meson-a1-usb-ctrl" }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, dwc3_meson_a1_match); + +static struct platform_driver dwc3_meson_a1_driver = { + .probe = dwc3_meson_a1_probe, + .remove = dwc3_meson_a1_remove, + .driver = { + .name = "dwc3-meson-a1", + .of_match_table = dwc3_meson_a1_match, + .pm = &dwc3_meson_a1_dev_pm_ops, + }, +}; + +module_platform_driver(dwc3_meson_a1_driver); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Amlogic Meson A1 USB Glue Layer"); +MODULE_AUTHOR("Yue Wang "); From patchwork Fri Nov 22 06:55:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11257287 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 14D65138C for ; Fri, 22 Nov 2019 07:11:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E978F2071C for ; Fri, 22 Nov 2019 07:11:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726686AbfKVHLQ (ORCPT ); Fri, 22 Nov 2019 02:11:16 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:61411 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726634AbfKVHLP (ORCPT ); Fri, 22 Nov 2019 02:11:15 -0500 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Fri, 22 Nov 2019 02:11:01 EST Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 22 Nov 2019 14:56:25 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Felipe Balbi , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH 5/6] arm64: dts: meson: a1: Enable USB2 PHY Date: Fri, 22 Nov 2019 14:55:56 +0800 Message-ID: <1574405757-76184-6-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> References: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Enable USB2 PHY for Meson A1 SoC. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index eaeae80..3b61717 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -106,6 +106,16 @@ #power-domain-cells = <1>; status = "okay"; }; + + usb2_phy0: phy@40000 { + status = "okay"; + compatible = "amlogic,a1-usb2-phy"; + reg = <0x0 0x40000 0x0 0x2000>; + resets = <&reset RESET_USBPHY>; + reset-names = "phy"; + #phy-cells = <0>; + power-domains = <&pwrc PWRC_USB_ID>; + }; }; gic: interrupt-controller@ff901000 { From patchwork Fri Nov 22 06:55:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11257289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A13C14C0 for ; Fri, 22 Nov 2019 07:11:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2477C2070A for ; Fri, 22 Nov 2019 07:11:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726634AbfKVHLS (ORCPT ); Fri, 22 Nov 2019 02:11:18 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:61411 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726676AbfKVHLS (ORCPT ); Fri, 22 Nov 2019 02:11:18 -0500 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Fri, 22 Nov 2019 02:11:01 EST Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 22 Nov 2019 14:56:25 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Felipe Balbi , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH 6/6] arm64: dts: meson: a1: Enable DWC3 controller Date: Fri, 22 Nov 2019 14:55:57 +0800 Message-ID: <1574405757-76184-7-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> References: <1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Enable DWC3 controller for Meson A1 SoC. Change-Id: Ibbbfb44fc211f926adf91a548776bc6bca6fa35c Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 3b61717..f3d93cd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -6,6 +6,9 @@ #include #include #include +#include +#include +#include / { compatible = "amlogic,a1"; @@ -130,6 +133,34 @@ #interrupt-cells = <3>; #address-cells = <0>; }; + + usb: usb@ffe09000 { + status = "okay"; + compatible = "amlogic,meson-a1-usb-ctrl"; + reg = <0x0 0xffe09000 0x0 0xa0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc_periphs CLKID_USB_CTRL>, + <&clkc_periphs CLKID_USB_BUS>, + <&clkc_periphs CLKID_XTAL_USB_PHY>, + <&clkc_periphs CLKID_XTAL_USB_CTRL>; + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_phy", + "xtal_usb_ctrl"; + resets = <&reset RESET_USBCTRL>; + phys = <&usb2_phy0>; + phy-names = "usb2-phy0"; + + dwc3: usb@ff400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff400000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + }; + }; }; timer {