From patchwork Mon Nov 25 14:25:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 11260477 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EFB7317F0 for ; Mon, 25 Nov 2019 14:25:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D097F20863 for ; Mon, 25 Nov 2019 14:25:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="e9zr5cFE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728036AbfKYOZR (ORCPT ); Mon, 25 Nov 2019 09:25:17 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:37699 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728037AbfKYOZR (ORCPT ); Mon, 25 Nov 2019 09:25:17 -0500 Received: by mail-lj1-f193.google.com with SMTP id d5so16096493ljl.4 for ; Mon, 25 Nov 2019 06:25:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sLculURoH3BCV7hyS93RpcUM9UKZHxxj8yiEZMlzgFI=; b=e9zr5cFEFsYtz8NXh6wk3vUJiorgv8HQAamT1XM5/Vk90Irw61nDfa5wPaYmVwMzqk Zud3SpzpmI0iGzF04+2AZv60HTwH4SR1gjdxeDGc2B2BL7ONVj8HgsFJJ85xFeB9Uy3i SIBriFaViu/kJ2n5cvhCuu3GnC5cV+Mss1EtXmX2wP1ByKUha9tTCHOmwTiaqs0xZ7EX WBRkPnnC6nOtQPYt9OgxSA+DTh1WIcWpotuxit2u6jM2bWGnof3coMDEVy1+ose+1age Brx4DclEo7Umjh4JU8Ave451L3cOgdaZr4yTZaZ+PwZ9WyWBaVj9bRresnpboJmK0NTT Z7Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sLculURoH3BCV7hyS93RpcUM9UKZHxxj8yiEZMlzgFI=; b=km60K7XHjCFJrR40HphEpE3HXJLc4fyVIiUJHIOxjsBt6n4l29o5fTBKFUritvKgIM QPiIuYRkNA1z/HJHhSp0Bh2lU9wvPqusd7zlzolrpWx8kvSuaRD1L/Nx9kp9yrFvx7LN l4ygnVsE3IGxMjG82NckG7e7UloOr4XyXb3NWdmMMuCx6ZEXv5Kl3m6watl7e6sUCARS 1tXtefG6NVQiDkYApwm2608FripLpejwRiVtNd5/79g+r3b8Dqg4eG0Rs6qBRNTDCWU6 B8DuAk5K541LyshRwGonypM7ab3rqr4e/ZfXlSN8mlQWgUNOgr/ssWiQABKStbgs8l6j yPGA== X-Gm-Message-State: APjAAAWH7SHpwk+VQdIrwP25jfcDP8fUxvuHeTtIThkoXEsDSq8p6OUF LsQyXyugH5Uth1vpTTl7hF0F9g== X-Google-Smtp-Source: APXvYqxzruuMyNSCsHenp3VVyLy99hYliqQex3TauCdVPMev/vQosO5w0vBVcQdHh1R5S2l9zyaGPw== X-Received: by 2002:a2e:8e27:: with SMTP id r7mr23143728ljk.101.1574691914559; Mon, 25 Nov 2019 06:25:14 -0800 (PST) Received: from centauri.lan (ua-84-217-220-205.bbcust.telenor.se. [84.217.220.205]) by smtp.gmail.com with ESMTPSA id b28sm4595260ljp.9.2019.11.25.06.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 06:25:14 -0800 (PST) From: Niklas Cassel To: Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, Jorge Ramirez-Ortiz , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider Date: Mon, 25 Nov 2019 15:25:06 +0100 Message-Id: <20191125142511.681149-2-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191125142511.681149-1-niklas.cassel@linaro.org> References: <20191125142511.681149-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. The driver still supports the previous bindings; however with this update it we allow the msm8916 to access the parent clock names required by the driver operation using the device tree node. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- Changes since v1: -Swapped order of "pll" and "aux" clocks, in order to not break DT backwards compatibility. (In case no clock-names are given, "pll" still has to be the first clock). arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8686e101905c..9ec41b24a51f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -429,7 +429,8 @@ compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; reg = <0xb011000 0x1000>; #mbox-cells = <1>; - clocks = <&a53pll>; + clocks = <&a53pll>, <&gcc GPLL0_VOTE>; + clock-names = "pll", "aux"; #clock-cells = <0>; }; From patchwork Mon Nov 25 14:25:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 11260475 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C405109A for ; Mon, 25 Nov 2019 14:25:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5D6A42084D for ; Mon, 25 Nov 2019 14:25:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AkAOL4O/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728057AbfKYOZT (ORCPT ); Mon, 25 Nov 2019 09:25:19 -0500 Received: from mail-lf1-f65.google.com ([209.85.167.65]:43702 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728045AbfKYOZT (ORCPT ); Mon, 25 Nov 2019 09:25:19 -0500 Received: by mail-lf1-f65.google.com with SMTP id l14so11163639lfh.10 for ; Mon, 25 Nov 2019 06:25:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EuFRcfNq3LsLJUbGBe/N0k0kxrqgC13hX5+2ejknKGs=; b=AkAOL4O//f/RtBY5VC03PxSWYUE6xfXln26RyI5bNloyd5gy7kJqQlMwwu91Oaz0ZO RHeLXkrD8E+/HVxzKXXpZ8Yg2m71+hIudIPVy9nlwgbwLaDUxhYOHoFMHeL5J/QYKI+O +1ko2kO8OHLBdd3Gn0NpIelexXRaE8FTXlGhEPWeqn7t3vTY0ogWRFyfyKBWX+P9Hunu /9y5p1pGDHOxWiwD0sklo209ARyQY1OjPi+FKaoCmMhR+SEa45qMXH9n2Ds335kHj/MU ioWhRFXJAjRiDvxzofqr3KDMrkX7UBPNRwXI7KnRUYWSK8Ypzqj38UNhhIIvXLnAHQfc 2vzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EuFRcfNq3LsLJUbGBe/N0k0kxrqgC13hX5+2ejknKGs=; b=kMYgoy3o9O7lsZ7lzk5TjyIF1/Z3jbSS4ApbdMelZfAu9BNRhxexN+++BzL1QAQbsT sPijOXrHbzQniy2If1sHC+czfhp2islvesA7hosnOVSzfy5Lgr6dc61V/UG6s6cAF3Zd ccIVGP2K3DSgGMMOHu/dLuOZPwMO+utuhJmFJO+5u9+iGxBgKzha9FwOKcnJpPrv/flV a0f0M8sbCSEYeffFaztY3roiFuHWEEqRQ0vV8WHupfKYkBBPd5sNgXblHfxWrHwJAuFR siaxhO4CEFpEHsuwKwyCsFGu+XvvPbM4G97f4I8VC7VeYLY6jleAW8UEg6+bRTzVd8On VWLw== X-Gm-Message-State: APjAAAWHBgAml4TU+O1uyujwgzRYdNF1Dz0q5iusuIJ6ZyhveSumtZW6 o2GV7Be6sb2OdfIxZVSJi77AvA== X-Google-Smtp-Source: APXvYqzuq/eLmUxMrkGzcX3pUkJ6NfSsIbuDwa4XqpO40lHVmtRNc4qkwNjG1guC3iEzcehjjqVnkA== X-Received: by 2002:ac2:5b0f:: with SMTP id v15mr10082682lfn.99.1574691916018; Mon, 25 Nov 2019 06:25:16 -0800 (PST) Received: from centauri.lan (ua-84-217-220-205.bbcust.telenor.se. [84.217.220.205]) by smtp.gmail.com with ESMTPSA id b28sm4595260ljp.9.2019.11.25.06.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 06:25:15 -0800 (PST) From: Niklas Cassel To: Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, Jorge Ramirez-Ortiz , Niklas Cassel , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] arm64: dts: qcom: qcs404: Add HFPLL node Date: Mon, 25 Nov 2019 15:25:07 +0100 Message-Id: <20191125142511.681149-3-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191125142511.681149-1-niklas.cassel@linaro.org> References: <20191125142511.681149-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz The high frequency pll functionality is required to enable CPU frequency scaling operation. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- Changes since v1: -None arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index f5f0c4c9cb16..78065fbb3626 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -904,6 +904,15 @@ #mbox-cells = <1>; }; + apcs_hfpll: clock-controller@b016000 { + compatible = "qcom,hfpll"; + reg = <0x0b016000 0x30>; + #clock-cells = <0>; + clock-output-names = "apcs_hfpll"; + clocks = <&xo_board>; + clock-names = "xo"; + }; + watchdog@b017000 { compatible = "qcom,kpss-wdt"; reg = <0x0b017000 0x1000>; From patchwork Mon Nov 25 14:25:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 11260479 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3248514DB for ; Mon, 25 Nov 2019 14:25:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1347320866 for ; Mon, 25 Nov 2019 14:25:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="aRSvRXMy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728069AbfKYOZe (ORCPT ); Mon, 25 Nov 2019 09:25:34 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:39342 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728023AbfKYOZe (ORCPT ); Mon, 25 Nov 2019 09:25:34 -0500 Received: by mail-lj1-f193.google.com with SMTP id e10so6937000ljj.6 for ; Mon, 25 Nov 2019 06:25:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hIpnG6FWTeAa0vcijPGznoB/xSYwTutFCgvay272V/4=; b=aRSvRXMyf1ali3uyoFd85ct/hWNmON6aS2t4ePy7ewCLikYo6GSFj4eqgh3k3YWQyD +Z+v/7aGti2ReaQkAwIQtqy5cHn+lkyDcFSn6nNGn2mpLin7BBspQXp6wUZz01gqBI4r sJUcBwUBfdQnSDBoyjuLz0fbCOWoPdqGCp2UIEKQHlL2rNvs8YuE8BoWaipzUtTUfXRn yAAfWnkkUcz2QKzazCpqUBwuGofue+tky0yylv3DVX9ZO6uTnCRGs4gpVNJyZOmE1xPH +dgDGEHA8P1aOtRyDa3TMn8cz8gwHpBvQhbDT5jgNscpuVxKt6hbGpUolQuxg9fW6voc ml0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hIpnG6FWTeAa0vcijPGznoB/xSYwTutFCgvay272V/4=; b=c0HranwQ7++vS8Xq4SXfZNW84kIei15gKRYkylTAGeq9EApVm1oNNTBIlA8RJZo2zp PZoXKUV+kmhx17Eo4kxQi7nzGSz10mtYo1hqVogZIINwqMXykngV77s320iAi1azxpkT Kx69+wN08GG9bH15XtDq7lG01i/MOQAxnwSb+mGoTCteeZaOpKXYWklEUHOqujErmiJz LTI4KFy5uXj76/H3LZU+iq/sd8PAz0nHD0tKt5P5tt3KJxxnopwLBCyvY6w5spU/telH /DNQgvROKKhx1CCLx1YtlN9quDIeXzjEplH5LeuekDBYWsxrmoV8gO52Ax4Y4KeFpwDI /k6Q== X-Gm-Message-State: APjAAAWGgHkHFyOzdpdCqRoB2iFVxqWBgA0DPpR46FN2rj+wOw4LmkG8 xx6fF8iDqyQxBshdywuyj6f212bchnk8og== X-Google-Smtp-Source: APXvYqwa2KM4Dz+pKU7jcg7FzJdbHl2V1ER/pVfnPAE1CfaZFiYc92nFeRawfD1vx0nZUw2ZO66dqA== X-Received: by 2002:a2e:b537:: with SMTP id z23mr22760453ljm.129.1574691932342; Mon, 25 Nov 2019 06:25:32 -0800 (PST) Received: from centauri.lan (ua-84-217-220-205.bbcust.telenor.se. [84.217.220.205]) by smtp.gmail.com with ESMTPSA id 15sm4016640ljq.62.2019.11.25.06.25.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 06:25:31 -0800 (PST) From: Niklas Cassel To: Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, Jorge Ramirez-Ortiz , Niklas Cassel , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider Date: Mon, 25 Nov 2019 15:25:08 +0100 Message-Id: <20191125142511.681149-4-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191125142511.681149-1-niklas.cassel@linaro.org> References: <20191125142511.681149-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- Changes since v1: -Swapped order of "pll" and "aux" clocks, in order to not break DT backwards compatibility. (In case no clock-names are given, "pll" still has to be the first clock). arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 78065fbb3626..ee5ecf413664 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -902,6 +902,9 @@ compatible = "qcom,qcs404-apcs-apps-global", "syscon"; reg = <0x0b011000 0x1000>; #mbox-cells = <1>; + clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; + clock-names = "pll", "aux"; + #clock-cells = <0>; }; apcs_hfpll: clock-controller@b016000 { From patchwork Mon Nov 25 14:25:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 11260485 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3BCD214DB for ; Mon, 25 Nov 2019 14:25:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1C6CE20862 for ; Mon, 25 Nov 2019 14:25:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ba7qmsft" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728104AbfKYOZo (ORCPT ); Mon, 25 Nov 2019 09:25:44 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:37749 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728068AbfKYOZh (ORCPT ); Mon, 25 Nov 2019 09:25:37 -0500 Received: by mail-lj1-f195.google.com with SMTP id d5so16097941ljl.4 for ; Mon, 25 Nov 2019 06:25:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tGGMdMAZ+2UKR5jWaE6SPzu4SHFqOnBiMLG+eD+sTeM=; b=ba7qmsftTBZ210RBrcuF9OufjGwHudDAhyeTULabinMb46u7NPBdRE/UR0a4e5t011 DjwM4yVXqlpbSyxhgN1KpjHVhVzZ6FuEeFYtTMkNbHj3VeQVZYQvX+w/3D/qeTmMiCfi obIMRuYTj9lEw0DK7spiL6D4ug3fvvVZKVPIxGmhprwz2JFjzCJJdo+oHyP5k2q7eyCg /frAdotCY62B1BU14VQmRiyQDoTv4fxRegESPxE4VcbZmukHrnjNGttpieYlyzo06+jX gkJgSjNEv9KhfUn376i3qzTVb8lJ/mTyFQdjtihgi89xHO33N8pNP4DY/3h19BmwV4mW bMSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tGGMdMAZ+2UKR5jWaE6SPzu4SHFqOnBiMLG+eD+sTeM=; b=c/XCT/h122IeXA6tvqNDf1GFdXo+klHNmR+GpuC9AvPn17nPNjvpWCMwGuTC0wlwjk 1DII5P5v8NyYPKjegiuKH1LNp3L9GqVcv9tWv5uDKhv6k+eK0oPaucdOa8XiCLs6g+57 +xbOdvgYNN7riFLzJBJGRsYXbljdatvD42Jn3p67ygyz0P2b/ShM2vcJNsDwtp+cYqpQ ghEkMNz/mnTZO2eFSny5aPUvkCU0ZjwMgtyqLGy52k9k0L15q+/3ePOJM94CcfBtSuTs B0/8OqwusK0GGueAOUeTwaWu89iimV/ATQ0/g8XFYTWczHOY3KFOuogaXl3VSUye/opn GUAg== X-Gm-Message-State: APjAAAUxHbugErGzvOR/D8qIabWtqMNk3vqR9xqW20lt64RjfBdnF7OY TJ/jPhHUGNxGaxofOM5aBn4Dng== X-Google-Smtp-Source: APXvYqyGtWRbBy6a2xjbGTzIU68+1R5oObGLLfsEfvSZGCj/WM8ZCF7WiKHbwCGYFMQM87oZ7tMzHQ== X-Received: by 2002:a2e:6c0c:: with SMTP id h12mr23194224ljc.24.1574691933856; Mon, 25 Nov 2019 06:25:33 -0800 (PST) Received: from centauri.lan (ua-84-217-220-205.bbcust.telenor.se. [84.217.220.205]) by smtp.gmail.com with ESMTPSA id 15sm4016640ljq.62.2019.11.25.06.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 06:25:33 -0800 (PST) From: Niklas Cassel To: Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, Jorge Ramirez-Ortiz , Niklas Cassel , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] arm64: dts: qcom: qcs404: Add DVFS support Date: Mon, 25 Nov 2019 15:25:09 +0100 Message-Id: <20191125142511.681149-5-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191125142511.681149-1-niklas.cassel@linaro.org> References: <20191125142511.681149-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz Support dynamic voltage and frequency scaling on qcs404. CPUFreq will soon be superseded by Core Power Reduction (CPR, a form of Adaptive Voltage Scaling found on some Qualcomm SoCs like the qcs404). Due to the CPR upstreaming already being in progress - and some commits already merged - the following commit will need to be reverted to enable CPUFreq support Author: Jorge Ramirez-Ortiz Date: Thu Jul 25 12:41:36 2019 +0200 cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- Changes since v1: -Removed incorrect newline in the middle of the cpu0 DT node. (This extra newline must have been added by mistake, since no other cpuX node in the same cluster had this extra newline added.) arch/arm64/boot/dts/qcom/qcs404.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ee5ecf413664..03aa80f2814a 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -42,6 +42,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU1: cpu@101 { @@ -52,6 +55,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU2: cpu@102 { @@ -62,6 +68,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; CPU3: cpu@103 { @@ -72,6 +81,9 @@ cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&pms405_s3>; }; L2_0: l2-cache { @@ -94,6 +106,24 @@ }; }; + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-microvolt = <1224000 1224000 1224000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <1288000 1288000 1288000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-microvolt = <1384000 1384000 1384000>; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-qcs404", "qcom,scm"; From patchwork Mon Nov 25 14:25:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 11260483 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4A88114DB for ; Mon, 25 Nov 2019 14:25:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2AC3920862 for ; Mon, 25 Nov 2019 14:25:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zchG2SUm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728081AbfKYOZm (ORCPT ); Mon, 25 Nov 2019 09:25:42 -0500 Received: from mail-lf1-f65.google.com ([209.85.167.65]:36735 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728088AbfKYOZi (ORCPT ); Mon, 25 Nov 2019 09:25:38 -0500 Received: by mail-lf1-f65.google.com with SMTP id f16so11197694lfm.3 for ; Mon, 25 Nov 2019 06:25:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lk8SRgnsKjAXBRx1hwjdc4Ni4aIadkTu9BDcS7y9BzI=; b=zchG2SUm1v9d74lK7/a2Ov/76astU1osx0T1E+xZK0+7tbypt2wEIrGbCIGTV3fYLl Qrr/vm3uT1sQaljCinz5Mgcpia9mxh+xjWu1/o1DaUbLJPz2lsjywcvEzeV9OOcHFFXw wwb43RuNNbilDJHZe1txdK+kp9I789BbjlWlIoc5O2kjNcXsCNmVIEjI2pTkl2Zgr16S 9wFS6rTOIN4Gq8aNErHoCVr8SiXT5GzeZqhbdGAx4PJBZVRLKf4k0ueXsbhHHwtAvpJW iSEd9iur/qi7eAw07BQkKObFUYbW5j3hSr4gmF2pWAMnAGDNw/8lUlzSCrMNKGQUFBUX +teQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lk8SRgnsKjAXBRx1hwjdc4Ni4aIadkTu9BDcS7y9BzI=; b=BCS+HlH3mtt4vA19NWlIq6zXfEA2oXaA0xe6Bl3H/OJb9TLDabsRmgYrKcBI681lQ8 jKycvOR1dQcmrtMK/LRf9qM0NvpdkDb6v1hj3auMRIurhcuFqDXM9F0nAS6uoBaDUGAy 60XnVj0nLLGlIOXaf/fFFbETExbBFfx1OwMljInKGpnYpuEInD4X9v93C6BaslkOBhMe ZyGsoBEVrczr8QwZlOx9gm4BRxAbw3a2d3HGZcfAMettmDwwBOH441eJsWkIPKpIjx3l 06FFXNh/qmFOcuXhEVxJ5DCbD0cz+gJTB8LgK/nem3UR7Dx0v06x8boMYpQqu/m8D4v9 R0/Q== X-Gm-Message-State: APjAAAW5jxVHqbE1mCPXlYpMG8JzR5n9G7wkgDl7iyXyQkW7C6pe7/Hr KzlG79OyeVOqs5GGHM6mFfl7zg== X-Google-Smtp-Source: APXvYqyE+jBtA6fW2pog7AMXr9bL2gLyOpR90A0sgyb4hzg762aBGAjB5B+6dLqfNRt+VohCnld2CQ== X-Received: by 2002:a19:751a:: with SMTP id y26mr21685422lfe.78.1574691935705; Mon, 25 Nov 2019 06:25:35 -0800 (PST) Received: from centauri.lan (ua-84-217-220-205.bbcust.telenor.se. [84.217.220.205]) by smtp.gmail.com with ESMTPSA id 15sm4016640ljq.62.2019.11.25.06.25.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 06:25:35 -0800 (PST) From: Niklas Cassel To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, amit.kucheria@linaro.org, bjorn.andersson@linaro.org, Jorge Ramirez-Ortiz , Niklas Cassel , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/5] arm64: defconfig: Enable HFPLL Date: Mon, 25 Nov 2019 15:25:10 +0100 Message-Id: <20191125142511.681149-6-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191125142511.681149-1-niklas.cassel@linaro.org> References: <20191125142511.681149-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz The high frequency pll is required on compatible Qualcomm SoCs to support the CPU frequency scaling feature. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- Changes since v1: -None arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7fa92defb964..e76b42b25dd6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -727,6 +727,7 @@ CONFIG_MSM_GCC_8998=y CONFIG_QCS_GCC_404=y CONFIG_SDM_GCC_845=y CONFIG_SM_GCC_8150=y +CONFIG_QCOM_HFPLL=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_ARM_MHU=y