From patchwork Wed Nov 27 03:32:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11263367 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4785B15AB for ; Wed, 27 Nov 2019 03:34:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 153F720862 for ; Wed, 27 Nov 2019 03:34:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="R9/w4klA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726729AbfK0DeH (ORCPT ); Tue, 26 Nov 2019 22:34:07 -0500 Received: from sender4-pp-o98.zoho.com ([136.143.188.98]:25895 "EHLO sender4-pp-o98.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbfK0DeH (ORCPT ); Tue, 26 Nov 2019 22:34:07 -0500 ARC-Seal: i=1; a=rsa-sha256; t=1574825622; cv=none; d=zohomail.com; s=zohoarc; b=d2pQ32r98WmvTqMxDs76cFGwuQX161v8Wy8ijW75aT5Lyz2QgRxvpwSq25r5/Su7U+OWQEwEeCVmA4WVpESAKuVGjxHorPS+y2v389OXXPU0k8BTgl+wnJ3XYaRKyIw+rdrQ5aPnA2Eu0SMuQHnXyQNNxjr7zoPdXPAR3ZEqy1k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574825622; h=Cc:Date:From:In-Reply-To:Message-ID:References:Subject:To; bh=+doOzuXa3LtRkn7hXvpxk2eD3ZYd0To77WwPb86Dr24=; b=Qmk19PtbC+eeUv2jdMgF9vGr9PR1l/FGS+Ay6egYMYH6cvEGDMJYOu+La1/nXNKbaFVHRBRC7BZSzSp7rEXv1CLz6DyFkqiYcMEqhvgtYQwl/FnVr4UjCDGP2EYi7XQx/+4avIkyb4b72OcLnUbM0qjSjxohsJCJ2oetIw9u63o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=zoho.com; spf=pass smtp.mailfrom=zhouyanjie@zoho.com; dmarc=pass header.from= header.from= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=zapps768; d=zoho.com; h=from:to:cc:subject:date:message-id:in-reply-to:references; b=A+ntKLG11CvDl51ARsyy40bQeZSS4daaEtsxvo5RO3JwcTFslhb9gbNWGTXFsaX+kfQNRPFqneeZ mfyPbUlPQ+jNcJQIlxhcaZaCcNctxX4yKH8G5B8fxGigDHF4oz8Z DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1574825622; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; bh=+doOzuXa3LtRkn7hXvpxk2eD3ZYd0To77WwPb86Dr24=; b=R9/w4klAMDlSOKSdjGzzxoeGT77UosloGP7PT7VVLUxppG4v/BMrJoFoYa43Hclz Vm3guXP6Y08a4Qh0X6Bh47OEwAAF/FOR1RBBja0QT598KMveZDykOcvS3/PcuSvGUxM FrPBOJHLOGeAUpbJPq4NNpmjF2QAfnrhpJx0PLQA= Received: from zhouyanjie-virtual-machine.localdomain (139.207.174.158 [139.207.174.158]) by mx.zohomail.com with SMTPS id 1574825620350562.281348884933; Tue, 26 Nov 2019 19:33:40 -0800 (PST) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, mark.rutland@arm.com, syq@debian.org, paul@crapouillou.net, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 1/5] clk: Ingenic: Adjust code to make it compatible with X1830. Date: Wed, 27 Nov 2019 11:32:52 +0800 Message-Id: <1574825576-91028-2-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574825576-91028-1-git-send-email-zhouyanjie@zoho.com> References: <1574825576-91028-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org 1.Adjust the PLL related code in "cgu.c" and "cgu.h" to make it compatible with the X1830 Soc from Ingenic. 2.Adjust the code in "jz4740-cgu.c" to be compatible with the new cgu code. 3.Adjust the code in "jz4725b-cgu.c" to be compatible with the new cgu code. 4.Adjust the code in "jz4770-cgu.c" to be compatible with the new cgu code. 5.Adjust the code in "jz4780-cgu.c" to be compatible with the new cgu code. 6.Adjust the code in "x1000-cgu.c" to be compatible with the new cgu code. Signed-off-by: Zhou Yanjie --- drivers/clk/ingenic/cgu.c | 55 +++++++++++++++++++++++++++++---------- drivers/clk/ingenic/cgu.h | 12 ++++++++- drivers/clk/ingenic/jz4725b-cgu.c | 3 ++- drivers/clk/ingenic/jz4740-cgu.c | 3 ++- drivers/clk/ingenic/jz4770-cgu.c | 6 +++-- drivers/clk/ingenic/jz4780-cgu.c | 3 ++- drivers/clk/ingenic/x1000-cgu.c | 6 +++-- 7 files changed, 66 insertions(+), 22 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 6e96303..c3c69a8 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -84,7 +84,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) pll_info = &clk_info->pll; spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->reg[1]); spin_unlock_irqrestore(&cgu->lock, flags); m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); @@ -93,8 +93,17 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) n += pll_info->n_offset; od_enc = ctl >> pll_info->od_shift; od_enc &= GENMASK(pll_info->od_bits - 1, 0); - bypass = !pll_info->no_bypass_bit && - !!(ctl & BIT(pll_info->bypass_bit)); + + if (pll_info->version >= CGU_X1830) { + spin_lock_irqsave(&cgu->lock, flags); + ctl = readl(cgu->base + pll_info->reg[0]); + spin_unlock_irqrestore(&cgu->lock, flags); + + bypass = !pll_info->no_bypass_bit && + !!(ctl & BIT(pll_info->bypass_bit)); + } else + bypass = !pll_info->no_bypass_bit && + !!(ctl & BIT(pll_info->bypass_bit)); if (bypass) return parent_rate; @@ -106,7 +115,10 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) BUG_ON(od == pll_info->od_max); od++; - return div_u64((u64)parent_rate * m, n * od); + if (pll_info->version >= CGU_X1830) + return div_u64((u64)parent_rate * m * 2, n * od); + else + return div_u64((u64)parent_rate * m, n * od); } static unsigned long @@ -139,7 +151,10 @@ ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, if (pod) *pod = od; - return div_u64((u64)parent_rate * m, n * od); + if (pll_info->version >= CGU_X1830) + return div_u64((u64)parent_rate * m * 2, n * od); + else + return div_u64((u64)parent_rate * m, n * od); } static inline const struct ingenic_cgu_clk_info *to_clk_info( @@ -183,7 +198,7 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, clk_info->name, req_rate, rate); spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->reg[1]); ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); ctl |= (m - pll_info->m_offset) << pll_info->m_shift; @@ -194,7 +209,7 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; - writel(ctl, cgu->base + pll_info->reg); + writel(ctl, cgu->base + pll_info->reg[1]); spin_unlock_irqrestore(&cgu->lock, flags); return 0; @@ -212,16 +227,28 @@ static int ingenic_pll_enable(struct clk_hw *hw) u32 ctl; spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->reg); - ctl &= ~BIT(pll_info->bypass_bit); + if (pll_info->version >= CGU_X1830) { + ctl = readl(cgu->base + pll_info->reg[0]); + + ctl &= ~BIT(pll_info->bypass_bit); + + writel(ctl, cgu->base + pll_info->reg[0]); + + ctl = readl(cgu->base + pll_info->reg[1]); + } else { + ctl = readl(cgu->base + pll_info->reg[1]); + + ctl &= ~BIT(pll_info->bypass_bit); + } + ctl |= BIT(pll_info->enable_bit); - writel(ctl, cgu->base + pll_info->reg); + writel(ctl, cgu->base + pll_info->reg[1]); /* wait for the PLL to stabilise */ for (i = 0; i < timeout; i++) { - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->reg[1]); if (ctl & BIT(pll_info->stable_bit)) break; mdelay(1); @@ -245,11 +272,11 @@ static void ingenic_pll_disable(struct clk_hw *hw) u32 ctl; spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->reg[1]); ctl &= ~BIT(pll_info->enable_bit); - writel(ctl, cgu->base + pll_info->reg); + writel(ctl, cgu->base + pll_info->reg[1]); spin_unlock_irqrestore(&cgu->lock, flags); } @@ -263,7 +290,7 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw) u32 ctl; spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->reg); + ctl = readl(cgu->base + pll_info->reg[1]); spin_unlock_irqrestore(&cgu->lock, flags); return !!(ctl & BIT(pll_info->enable_bit)); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 0dc8004..5f87be4 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -42,8 +42,18 @@ * @stable_bit: the index of the stable bit in the PLL control register * @no_bypass_bit: if set, the PLL has no bypass functionality */ +enum ingenic_cgu_version { + CGU_JZ4740, + CGU_JZ4725B, + CGU_JZ4770, + CGU_JZ4780, + CGU_X1000, + CGU_X1830, +}; + struct ingenic_cgu_pll_info { - unsigned reg; + enum ingenic_cgu_version version; + unsigned reg[2]; const s8 *od_encoding; u8 m_shift, m_bits, m_offset; u8 n_shift, n_bits, n_offset; diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c index a3b4635..6da7b41 100644 --- a/drivers/clk/ingenic/jz4725b-cgu.c +++ b/drivers/clk/ingenic/jz4725b-cgu.c @@ -53,7 +53,8 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { "pll", CGU_CLK_PLL, .parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, .pll = { - .reg = CGU_REG_CPPCR, + .version = CGU_JZ4725B, + .reg = { -1, CGU_REG_CPPCR }, .m_shift = 23, .m_bits = 9, .m_offset = 2, diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index 4f0e92c..3cf800d 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -68,7 +68,8 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "pll", CGU_CLK_PLL, .parents = { JZ4740_CLK_EXT, -1, -1, -1 }, .pll = { - .reg = CGU_REG_CPPCR, + .version = CGU_JZ4740, + .reg = { -1, CGU_REG_CPPCR }, .m_shift = 23, .m_bits = 9, .m_offset = 2, diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 956dd65..a62dfb1 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -101,7 +101,8 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "pll0", CGU_CLK_PLL, .parents = { JZ4770_CLK_EXT }, .pll = { - .reg = CGU_REG_CPPCR0, + .version = CGU_JZ4770, + .reg = { -1, CGU_REG_CPPCR0 }, .m_shift = 24, .m_bits = 7, .m_offset = 1, @@ -123,7 +124,8 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "pll1", CGU_CLK_PLL, .parents = { JZ4770_CLK_EXT }, .pll = { - .reg = CGU_REG_CPPCR1, + .version = CGU_JZ4770, + .reg = { -1, CGU_REG_CPPCR1 }, .m_shift = 24, .m_bits = 7, .m_offset = 1, diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index ea905ff..59356d1b 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -220,7 +220,8 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { /* PLLs */ #define DEF_PLL(name) { \ - .reg = CGU_REG_ ## name, \ + .version = CGU_JZ4780, \ + .reg = { -1, CGU_REG_ ## name }, \ .m_shift = 19, \ .m_bits = 13, \ .m_offset = 1, \ diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index b22d87b..7179b9f 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -57,7 +57,8 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { "apll", CGU_CLK_PLL, .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, .pll = { - .reg = CGU_REG_APLL, + .version = CGU_X1000, + .reg = { -1, CGU_REG_APLL }, .m_shift = 24, .m_bits = 7, .m_offset = 1, @@ -78,7 +79,8 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { "mpll", CGU_CLK_PLL, .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, .pll = { - .reg = CGU_REG_MPLL, + .version = CGU_X1000, + .reg = { -1, CGU_REG_MPLL }, .m_shift = 24, .m_bits = 7, .m_offset = 1, From patchwork Wed Nov 27 03:32:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11263369 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ACF5A1390 for ; Wed, 27 Nov 2019 03:34:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8BBA22075C for ; Wed, 27 Nov 2019 03:34:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="lDeI+uJ3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726346AbfK0De0 (ORCPT ); Tue, 26 Nov 2019 22:34:26 -0500 Received: from sender4-pp-o98.zoho.com ([136.143.188.98]:25805 "EHLO sender4-pp-o98.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726304AbfK0De0 (ORCPT ); Tue, 26 Nov 2019 22:34:26 -0500 ARC-Seal: i=1; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1574825632; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; bh=RgmfTfKwoYXw8kf5jEJ7b6HWPMYg4f37CM1yKIrzA2g=; b=lDeI+uJ34GT2H/XNNumsLzS6MgPRQ+joEJ112rdoW511dx3ZH0UoMO2LEoxECxCp dl+wGoQ0IDmo6aI3QX7qOR3DyUuxKG1hf0Ez91C1hUkfcdI09f6eIHmWsN3L8OXQl6h ochf7MZ1vviJaD3ZXow8uYhXwhbNEFln8Ejku4fI= Received: from zhouyanjie-virtual-machine.localdomain (139.207.174.158 [139.207.174.158]) by mx.zohomail.com with SMTPS id 1574825630972581.4125167303802; Tue, 26 Nov 2019 19:33:50 -0800 (PST) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, mark.rutland@arm.com, syq@debian.org, paul@crapouillou.net, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 2/5] dt-bindings: clock: Add X1830 bindings. Date: Wed, 27 Nov 2019 11:32:53 +0800 Message-Id: <1574825576-91028-3-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574825576-91028-1-git-send-email-zhouyanjie@zoho.com> References: <1574825576-91028-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add the clock bindings for the X1830 Soc from Ingenic. Signed-off-by: Zhou Yanjie Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/ingenic,cgu.txt | 1 + include/dt-bindings/clock/x1830-cgu.h | 46 ++++++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 include/dt-bindings/clock/x1830-cgu.h diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt index 75598e6..74bfc57 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt @@ -12,6 +12,7 @@ Required properties: * ingenic,jz4770-cgu * ingenic,jz4780-cgu * ingenic,x1000-cgu + * ingenic,x1830-cgu - reg : The address & length of the CGU registers. - clocks : List of phandle & clock specifiers for clocks external to the CGU. Two such external clocks should be specified - first the external crystal diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h new file mode 100644 index 00000000..6499170 --- /dev/null +++ b/include/dt-bindings/clock/x1830-cgu.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1830-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1830 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1830_CGU_H__ + +#define X1830_CLK_EXCLK 0 +#define X1830_CLK_RTCLK 1 +#define X1830_CLK_APLL 2 +#define X1830_CLK_MPLL 3 +#define X1830_CLK_EPLL 4 +#define X1830_CLK_VPLL 5 +#define X1830_CLK_SCLKA 6 +#define X1830_CLK_CPUMUX 7 +#define X1830_CLK_CPU 8 +#define X1830_CLK_L2CACHE 9 +#define X1830_CLK_AHB0 10 +#define X1830_CLK_AHB2PMUX 11 +#define X1830_CLK_AHB2 12 +#define X1830_CLK_PCLK 13 +#define X1830_CLK_DDR 14 +#define X1830_CLK_MAC 15 +#define X1830_CLK_MSCMUX 16 +#define X1830_CLK_MSC0 17 +#define X1830_CLK_MSC1 18 +#define X1830_CLK_SSIPLL 19 +#define X1830_CLK_SSIMUX 20 +#define X1830_CLK_SSI0 21 +#define X1830_CLK_SMB0 22 +#define X1830_CLK_SMB1 23 +#define X1830_CLK_SMB2 24 +#define X1830_CLK_UART0 25 +#define X1830_CLK_UART1 26 +#define X1830_CLK_SSI1 27 +#define X1830_CLK_SFC 28 +#define X1830_CLK_PDMA 29 + +#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ From patchwork Wed Nov 27 03:32:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11263373 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C5531390 for ; Wed, 27 Nov 2019 03:34:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0A10F207DD for ; Wed, 27 Nov 2019 03:34:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="fmYqT5ym" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727040AbfK0Deo (ORCPT ); Tue, 26 Nov 2019 22:34:44 -0500 Received: from sender4-pp-o98.zoho.com ([136.143.188.98]:25814 "EHLO sender4-pp-o98.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726747AbfK0Deo (ORCPT ); Tue, 26 Nov 2019 22:34:44 -0500 ARC-Seal: i=1; a=rsa-sha256; t=1574825644; cv=none; d=zohomail.com; s=zohoarc; b=DMowNLLrISvH4fcGxCWaJchvRMOJFeAjujIq8AUrpgiuBeSqU2LafStZ3m2vWSqCJqCyArOXnNBVYTVIdO6pdKLaGRQ9iCIcASKP/MLyU/mNjdbt8nnpyd0+CMBWtcXZpEcrqMCTevH6tPv/7yERRRK7P1IZ1qSKjkjqiJYRi4w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574825644; h=Cc:Date:From:In-Reply-To:Message-ID:References:Subject:To; bh=l9RHxM+V8yMIWYUYxKS8n8Zb95+g5cppcIGHhKGrdPo=; b=bRRAnwMzsgKbtqjTm1qxs+BLnfBGRK5nIMpRJtG2o9dwBB8RAN41kpZTD+9CK6RKtvgVy+dQ1F3sIyZwgTQteBib4qaPj2mbj2F2liDVOlN6nMVrU7mtAs9jgaSjWYwuLKdwvwSxaX9q3TxM7Ajs9Pk8eTN3RT5Chs+d0p/Mlk4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=zoho.com; spf=pass smtp.mailfrom=zhouyanjie@zoho.com; dmarc=pass header.from= header.from= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=zapps768; d=zoho.com; h=from:to:cc:subject:date:message-id:in-reply-to:references; b=TacvTK7eOUQ3E+FDPAKrMY9hjUYmWs2z5M3kL59oglahbeVe1Ypu3k7FvR2oQxi7aAvDAJKSNSXk RFVq6zSpuoFG0TNHkj+u9rP4sYOvq3vwBqp/QDnubBYtScchd+Ln DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1574825644; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; bh=l9RHxM+V8yMIWYUYxKS8n8Zb95+g5cppcIGHhKGrdPo=; b=fmYqT5ymMjZoja5Vr1MRxVLtMIgXOWAUcQP/h3pk9Rp2TICbo8+pJh/bWlRSWDA/ hYa5LF9epDV55loRREbI4LQdfu7eD/beds6fKk7ZZcTbfVkHIuGe6d3OyAqiBWOEPjS NNjiwZ4lRBWxsA4G/rXsL3A4OpkrRPgRbTcFeItQ= Received: from zhouyanjie-virtual-machine.localdomain (139.207.174.158 [139.207.174.158]) by mx.zohomail.com with SMTPS id 1574825643667795.2885544068819; Tue, 26 Nov 2019 19:34:03 -0800 (PST) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, mark.rutland@arm.com, syq@debian.org, paul@crapouillou.net, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 3/5] clk: Ingenic: Add CGU driver for X1830. Date: Wed, 27 Nov 2019 11:32:54 +0800 Message-Id: <1574825576-91028-4-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574825576-91028-1-git-send-email-zhouyanjie@zoho.com> References: <1574825576-91028-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add support for the clocks provided by the CGU in the Ingenic X1830 SoC, making use of the cgu code to do the heavy lifting. Signed-off-by: Zhou Yanjie --- drivers/clk/ingenic/Kconfig | 10 ++ drivers/clk/ingenic/Makefile | 1 + drivers/clk/ingenic/x1830-cgu.c | 336 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 347 insertions(+) create mode 100644 drivers/clk/ingenic/x1830-cgu.c diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index fb7b399..59c6c2c 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -55,6 +55,16 @@ config INGENIC_CGU_X1000 If building for a X1000 SoC, you want to say Y here. +config INGENIC_CGU_X1830 + bool "Ingenic X1830 CGU driver" + default MACH_X1830 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic X1830 + and compatible SoCs. + + If building for a X1830 SoC, you want to say Y here. + config INGENIC_TCU_CLK bool "Ingenic JZ47xx TCU clocks driver" default MACH_INGENIC diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index 8b1dad9..aaa4bff 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o +obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c new file mode 100644 index 00000000..946af6f --- /dev/null +++ b/drivers/clk/ingenic/x1830-cgu.c @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * X1830 SoC CGU driver + * Copyright (c) 2019 Zhou Yanjie + */ + +#include +#include +#include +#include +#include "cgu.h" +#include "pm.h" + +/* CGU register offsets */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_CPPCR 0x0c +#define CGU_REG_APLL 0x10 +#define CGU_REG_MPLL 0x14 +#define CGU_REG_EPLL 0x58 +#define CGU_REG_VPLL 0xe0 +#define CGU_REG_CLKGR0 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_CLKGR1 0x28 +#define CGU_REG_DDRCDR 0x2c +#define CGU_REG_USBPCR 0x3c +#define CGU_REG_USBRDT 0x40 +#define CGU_REG_USBVBFIL 0x44 +#define CGU_REG_USBPCR1 0x48 +#define CGU_REG_MACCDR 0x54 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSC0CDR 0x68 +#define CGU_REG_I2SCDR1 0x70 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7c +#define CGU_REG_MSC1CDR 0xa4 +#define CGU_REG_CMP_INTR 0xb0 +#define CGU_REG_CMP_INTRE 0xb4 +#define CGU_REG_DRCG 0xd0 +#define CGU_REG_CPCSR 0xd4 +#define CGU_REG_MACPHYC 0xe8 + +/* bits within the OPCR register */ +#define OPCR_SPENDN0 BIT(7) +#define OPCR_SPENDN1 BIT(6) + +static struct ingenic_cgu *cgu; + +static const s8 pll_od_encoding[64] = { + 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, + -1, -1, -1, -1, -1, -1, -1, 0x4, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 0x5, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 0x6, +}; + +static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { + + /* External clocks */ + + [X1830_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, + [X1830_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, + + /* PLLs */ + + [X1830_CLK_APLL] = { + "apll", CGU_CLK_PLL, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .version = CGU_X1830, + .reg = { CGU_REG_CPPCR, CGU_REG_APLL }, + .m_shift = 20, + .m_bits = 9, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_bit = 30, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + [X1830_CLK_MPLL] = { + "mpll", CGU_CLK_PLL, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .version = CGU_X1830, + .reg = { CGU_REG_CPPCR, CGU_REG_MPLL }, + .m_shift = 20, + .m_bits = 9, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_bit = 28, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + [X1830_CLK_EPLL] = { + "epll", CGU_CLK_PLL, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .version = CGU_X1830, + .reg = { CGU_REG_CPPCR, CGU_REG_EPLL }, + .m_shift = 20, + .m_bits = 9, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_bit = 24, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + [X1830_CLK_VPLL] = { + "vpll", CGU_CLK_PLL, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .pll = { + .version = CGU_X1830, + .reg = { CGU_REG_CPPCR, CGU_REG_VPLL }, + .m_shift = 20, + .m_bits = 9, + .m_offset = 1, + .n_shift = 14, + .n_bits = 6, + .n_offset = 1, + .od_shift = 11, + .od_bits = 3, + .od_max = 64, + .od_encoding = pll_od_encoding, + .bypass_bit = 26, + .enable_bit = 0, + .stable_bit = 3, + }, + }, + + /* Muxes & dividers */ + + [X1830_CLK_SCLKA] = { + "sclk_a", CGU_CLK_MUX, + .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 }, + .mux = { CGU_REG_CPCCR, 30, 2 }, + }, + + [X1830_CLK_CPUMUX] = { + "cpu_mux", CGU_CLK_MUX, + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 28, 2 }, + }, + + [X1830_CLK_CPU] = { + "cpu", CGU_CLK_DIV, + .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, + }, + + [X1830_CLK_L2CACHE] = { + "l2cache", CGU_CLK_DIV, + .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, + }, + + [X1830_CLK_AHB0] = { + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 26, 2 }, + .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 }, + }, + + [X1830_CLK_AHB2PMUX] = { + "ahb2_apb_mux", CGU_CLK_MUX, + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, + .mux = { CGU_REG_CPCCR, 24, 2 }, + }, + + [X1830_CLK_AHB2] = { + "ahb2", CGU_CLK_DIV, + .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 }, + }, + + [X1830_CLK_PCLK] = { + "pclk", CGU_CLK_DIV, + .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 }, + }, + + [X1830_CLK_DDR] = { + "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, + .mux = { CGU_REG_DDRCDR, 30, 2 }, + .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 31 }, + }, + + [X1830_CLK_MAC] = { + "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .mux = { CGU_REG_MACCDR, 30, 2 }, + .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR1, 4 }, + }, + + [X1830_CLK_MSCMUX] = { + "msc_mux", CGU_CLK_MUX, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .mux = { CGU_REG_MSC0CDR, 30, 2 }, + }, + + [X1830_CLK_MSC0] = { + "msc0", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, + .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 4 }, + }, + + [X1830_CLK_MSC1] = { + "msc1", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { X1830_CLK_MSCMUX, -1, -1, -1 }, + .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR0, 5 }, + }, + + [X1830_CLK_SSIPLL] = { + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL, + X1830_CLK_VPLL, X1830_CLK_EPLL }, + .mux = { CGU_REG_SSICDR, 30, 2 }, + .div = { CGU_REG_SSICDR, 0, 1, 8, 28, 27, 26 }, + }, + + [X1830_CLK_SSIMUX] = { + "ssi_mux", CGU_CLK_MUX, + .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL, -1, -1 }, + .mux = { CGU_REG_SSICDR, 29, 1 }, + }, + + /* Gate-only clocks */ + + [X1830_CLK_SSI0] = { + "ssi0", CGU_CLK_GATE, + .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 6 }, + }, + + [X1830_CLK_SMB0] = { + "smb0", CGU_CLK_GATE, + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 7 }, + }, + + [X1830_CLK_SMB1] = { + "smb1", CGU_CLK_GATE, + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 8 }, + }, + + [X1830_CLK_SMB2] = { + "smb2", CGU_CLK_GATE, + .parents = { X1830_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 9 }, + }, + + [X1830_CLK_UART0] = { + "uart0", CGU_CLK_GATE, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 14 }, + }, + + [X1830_CLK_UART1] = { + "uart1", CGU_CLK_GATE, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 15 }, + }, + + [X1830_CLK_SSI1] = { + "ssi1", CGU_CLK_GATE, + .parents = { X1830_CLK_SSIMUX, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 19 }, + }, + + [X1830_CLK_SFC] = { + "sfc", CGU_CLK_GATE, + .parents = { X1830_CLK_SSIPLL, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 20 }, + }, + + [X1830_CLK_PDMA] = { + "pdma", CGU_CLK_GATE, + .parents = { X1830_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR0, 21 }, + }, +}; + +static void __init x1830_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(x1830_cgu_clocks, + ARRAY_SIZE(x1830_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) { + pr_err("%s: failed to register CGU Clocks\n", __func__); + return; + } + + ingenic_cgu_register_syscore_ops(cgu); +} +CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", x1830_cgu_init); From patchwork Wed Nov 27 03:32:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11263377 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4440C6C1 for ; Wed, 27 Nov 2019 03:35:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) 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bh=R/+7jdDa0EFrpAUyp2tl61s/1DciqRZ9DpBBE4CUXeg=; b=gwh0RTnr+q4LQt4p6Z7qenqcrt6XDO0FNpQ/P+EEvzSbiznkytugD1rihp6mIW7gMj6Gi1JiWKWawIWG44FIKic8yBVC+mQ5OqQCRkHjLuyMOno7whRYlGvDo3jvRW2jfEJKpIw4rFglL1wtfHKcDwM6jeDEmYmywoeMcSi8zP8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=zoho.com; spf=pass smtp.mailfrom=zhouyanjie@zoho.com; dmarc=pass header.from= header.from= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=zapps768; d=zoho.com; h=from:to:cc:subject:date:message-id:in-reply-to:references; b=GSUO1SC8PNrIwrBllGq7JPrFA1kdLpX912JnK3ImA3wcWIErrUSsRF6DhaaV8g4v25M+wJtcOmd/ NhgyfSCg/iGcQ6fSY7GeooUqSlG5XUvx9KklAHUKmVZFaDm3REa9 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1574825656; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; bh=R/+7jdDa0EFrpAUyp2tl61s/1DciqRZ9DpBBE4CUXeg=; b=Ba+p7pRo8gHWYXAPAK42FI+XngKfH8iTtczEpAXtGF7MWZpoqELEwwEM4CG0TtBY Uh5mgZAkdwP7ANFuw3L8e3OAftkvaZPbCbDcFk+4XoqKpwE0vglbqHRm6gL9Cath/gb ShYiGq40ZCKRDxWrsmZuYLPiaXY2L1NqOsjEYsHI= Received: from zhouyanjie-virtual-machine.localdomain (139.207.174.158 [139.207.174.158]) by mx.zohomail.com with SMTPS id 1574825655180599.1227371290488; Tue, 26 Nov 2019 19:34:15 -0800 (PST) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, mark.rutland@arm.com, syq@debian.org, paul@crapouillou.net, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 4/5] dt-bindings: clock: Add USB OTG clock for X1000. Date: Wed, 27 Nov 2019 11:32:55 +0800 Message-Id: <1574825576-91028-5-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574825576-91028-1-git-send-email-zhouyanjie@zoho.com> References: <1574825576-91028-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add the USB OTC clock bindings for the X1000 Soc from Ingenic. Signed-off-by: Zhou Yanjie --- include/dt-bindings/clock/x1000-cgu.h | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h index bbaebaf..c401fce 100644 --- a/include/dt-bindings/clock/x1000-cgu.h +++ b/include/dt-bindings/clock/x1000-cgu.h @@ -29,16 +29,17 @@ #define X1000_CLK_MSCMUX 14 #define X1000_CLK_MSC0 15 #define X1000_CLK_MSC1 16 -#define X1000_CLK_SSIPLL 17 -#define X1000_CLK_SSIMUX 18 -#define X1000_CLK_SFC 19 -#define X1000_CLK_I2C0 20 -#define X1000_CLK_I2C1 21 -#define X1000_CLK_I2C2 22 -#define X1000_CLK_UART0 23 -#define X1000_CLK_UART1 24 -#define X1000_CLK_UART2 25 -#define X1000_CLK_SSI 26 -#define X1000_CLK_PDMA 27 +#define X1000_CLK_OTG 17 +#define X1000_CLK_SSIPLL 18 +#define X1000_CLK_SSIMUX 19 +#define X1000_CLK_SFC 20 +#define X1000_CLK_I2C0 21 +#define X1000_CLK_I2C1 22 +#define X1000_CLK_I2C2 23 +#define X1000_CLK_UART0 24 +#define X1000_CLK_UART1 25 +#define X1000_CLK_UART2 26 +#define X1000_CLK_SSI 27 +#define X1000_CLK_PDMA 28 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ From patchwork Wed Nov 27 03:32:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11263381 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3F53E1390 for ; Wed, 27 Nov 2019 03:35:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1C94D2075C for ; Wed, 27 Nov 2019 03:35:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="IClZZjit" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726729AbfK0DfU (ORCPT ); Tue, 26 Nov 2019 22:35:20 -0500 Received: from sender4-pp-o98.zoho.com ([136.143.188.98]:25832 "EHLO sender4-pp-o98.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726346AbfK0DfT (ORCPT ); Tue, 26 Nov 2019 22:35:19 -0500 ARC-Seal: i=1; a=rsa-sha256; t=1574825666; cv=none; d=zohomail.com; s=zohoarc; b=c723msFTwwst+/jaUbMyDXYSuJYXxa9G+8m3uqFqr96I6twi5wOskMXLg3AvEFOrWPSp3+aZ/DR0dkXoJxCCIiEJy8bi/khozU21DJKae1NSiy/ZRa//SAPRLneGoP7WJCaVxli/XdTdCY0EvzgvWwGuuOXMZ1tZOnYy0ge6gck= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574825666; h=Cc:Date:From:In-Reply-To:Message-ID:References:Subject:To; bh=ZhfHT3Yd767Vb+SIOILoB057P7hth83ChUL4Ha7Q7oY=; b=I6Hjx2zvXCD5+Z8812104++IB2JTz1oWqcNiP8rdJDK2RPX9saWDk0IBcmuwKJ/6+GYqsyJyWkRsg2GaYGxZbKnoFNP5V1+D0COR4b+Gul/6Cg8oKUTPY1UvICrtseLO5JkAQX5bfLYDbTTK3izYI6Xu2iNqSRvXNJF3jzdG2Fg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=zoho.com; spf=pass smtp.mailfrom=zhouyanjie@zoho.com; dmarc=pass header.from= header.from= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=zapps768; d=zoho.com; h=from:to:cc:subject:date:message-id:in-reply-to:references; b=mX8UXWeeHW7W8IlEdGOBz49zep1b+WTjhoKO46Z0aZlIW9lx7J4FD1Y+S4nUPTkFX2xpPlX/bpqY YKaJuqS4exl5UD7Zx4LQsOUb32KLwWXCIyxIul8NhOy1glNZ7FWX DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1574825666; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; bh=ZhfHT3Yd767Vb+SIOILoB057P7hth83ChUL4Ha7Q7oY=; b=IClZZjitK/mFLBH+sTP+pke8e5GeCUyDxonqT8Z9D7BSo73/j6ee3NUA58ggZYYd qhaM8M1nZX5qndU6rPRRp/nqtiM5xMfVJM8lgUYoojsZqLzK0y7pzd2bqMwzBJYVSfb O0kvjzP107gQLVPUYWl/yv1CT7exvhviiMw6RkbY= Received: from zhouyanjie-virtual-machine.localdomain (139.207.174.158 [139.207.174.158]) by mx.zohomail.com with SMTPS id 1574825665180493.9393258207798; Tue, 26 Nov 2019 19:34:25 -0800 (PST) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, mark.rutland@arm.com, syq@debian.org, paul@crapouillou.net, sernia.zhou@foxmail.com, zhenwenjin@gmail.com Subject: [PATCH 5/5] clk: Ingenic: Add USB OTG clock for X1000. Date: Wed, 27 Nov 2019 11:32:56 +0800 Message-Id: <1574825576-91028-6-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574825576-91028-1-git-send-email-zhouyanjie@zoho.com> References: <1574825576-91028-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org 1.Add the USB OTC clock driver for the X1000 Soc from Ingenic. 2.Use the "CLK_OF_DECLARE_DRIVER" instead "CLK_OF_DECLARE" like the other CGU drivers. Signed-off-by: Zhou Yanjie --- drivers/clk/ingenic/x1000-cgu.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index 7179b9f..7da7c69 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -18,6 +18,11 @@ #define CGU_REG_CLKGR 0x20 #define CGU_REG_OPCR 0x24 #define CGU_REG_DDRCDR 0x2c +#define CGU_REG_USBPCR 0x3c +#define CGU_REG_USBRDT 0x40 +#define CGU_REG_USBVBFIL 0x44 +#define CGU_REG_USBPCR1 0x48 +#define CGU_REG_USBCDR 0x50 #define CGU_REG_MACCDR 0x54 #define CGU_REG_I2SCDR 0x60 #define CGU_REG_LPCDR 0x64 @@ -184,6 +189,15 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 5 }, }, + [X1000_CLK_OTG] = { + "otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, + .parents = { X1000_CLK_EXCLK, -1, + X1000_CLK_APLL, X1000_CLK_MPLL }, + .mux = { CGU_REG_USBCDR, 30, 2 }, + .div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 }, + .gate = { CGU_REG_CLKGR, 3 }, + }, + [X1000_CLK_SSIPLL] = { "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, @@ -273,4 +287,4 @@ static void __init x1000_cgu_init(struct device_node *np) ingenic_cgu_register_syscore_ops(cgu); } -CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init); +CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);