From patchwork Wed Nov 27 06:24:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Sun X-Patchwork-Id: 11263495 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E0D26C1 for ; Wed, 27 Nov 2019 06:30:31 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5AF92080F for ; Wed, 27 Nov 2019 06:30:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E5AF92080F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iZqpG-00014e-Hz; Wed, 27 Nov 2019 06:29:22 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iZqpF-00014Z-Kh for xen-devel@lists.xenproject.org; Wed, 27 Nov 2019 06:29:21 +0000 X-Inumbo-ID: 3e56fe5e-10df-11ea-b155-bc764e2007e4 Received: from mga03.intel.com (unknown [134.134.136.65]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 3e56fe5e-10df-11ea-b155-bc764e2007e4; Wed, 27 Nov 2019 06:29:20 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Nov 2019 22:29:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,248,1571727600"; d="scan'208";a="220875231" Received: from yisun1-ubuntu2.bj.intel.com ([10.238.144.121]) by orsmga002.jf.intel.com with ESMTP; 26 Nov 2019 22:29:17 -0800 From: Yi Sun To: xen-devel@lists.xenproject.org Date: Wed, 27 Nov 2019 14:24:31 +0800 Message-Id: <1574835871-5005-1-git-send-email-yi.y.sun@linux.intel.com> X-Mailer: git-send-email 1.9.1 Subject: [Xen-devel] [PATCH v1] psr: fix bug which may cause crash X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: andrew.cooper3@citrix.com, Yi Sun , jbeulich@suse.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" During test, we found a crash on Xen with below trace. (XEN) Xen call trace: (XEN) [] R psr.c#l3_cdp_write_msr+0x1e/0x22 (XEN) [] F psr.c#do_write_psr_msrs+0x6d/0x109 (XEN) [] F smp_call_function_interrupt+0x5a/0xac (XEN) [] F call_function_interrupt+0x20/0x34 (XEN) [] F do_IRQ+0x175/0x6ae (XEN) [] F common_interrupt+0x10a/0x120 (XEN) [] F cpu_idle.c#acpi_idle_do_entry+0x9d/0xb1 (XEN) [] F cpu_idle.c#acpi_processor_idle+0x41d/0x626 (XEN) [] F domain.c#idle_loop+0xa5/0xa7 (XEN) (XEN) (XEN) **************************************** (XEN) Panic on CPU 20: (XEN) GENERAL PROTECTION FAULT (XEN) [error_code=0000] (XEN) **************************************** Root cause is that the cache of COS registers are not initialized for CAT/CDP which have non-zero default value. That causes invalid write to MSR when COS id has exceeded the max number.. So fix it by initializing the cache. Signed-off-by: Yi Sun --- xen/arch/x86/psr.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 5866a26..d3e7467 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -316,6 +316,7 @@ static bool cat_init_feature(const struct cpuid_leaf *regs, [FEAT_TYPE_L3_CDP] = "L3 CDP", [FEAT_TYPE_L2_CAT] = "L2 CAT", }; + unsigned int i = 0; /* No valid value so do not enable feature. */ if ( !regs->a || !regs->d ) @@ -332,7 +333,8 @@ static bool cat_init_feature(const struct cpuid_leaf *regs, return false; /* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */ - feat->cos_reg_val[0] = cat_default_val(feat->cat.cbm_len); + for(i = 0; i < MAX_COS_REG_CNT; i++) + feat->cos_reg_val[i] = cat_default_val(feat->cat.cbm_len); wrmsrl((type == FEAT_TYPE_L3_CAT ? MSR_IA32_PSR_L3_MASK(0) : @@ -352,8 +354,11 @@ static bool cat_init_feature(const struct cpuid_leaf *regs, feat->cos_max = (feat->cos_max - 1) >> 1; /* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */ - get_cdp_code(feat, 0) = cat_default_val(feat->cat.cbm_len); - get_cdp_data(feat, 0) = cat_default_val(feat->cat.cbm_len); + for(i = 0; i < MAX_COS_REG_CNT/2; i++) + { + get_cdp_code(feat, i) = cat_default_val(feat->cat.cbm_len); + get_cdp_data(feat, i) = cat_default_val(feat->cat.cbm_len); + } wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cat.cbm_len)); wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->cat.cbm_len));