From patchwork Wed Nov 27 22:06:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11265015 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF4C7112B for ; Wed, 27 Nov 2019 22:11:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A4433216F4 for ; Wed, 27 Nov 2019 22:11:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hjWONevP" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A4433216F4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:43678 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ia5Wd-0000fV-JX for patchwork-qemu-devel@patchwork.kernel.org; Wed, 27 Nov 2019 17:11:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33794) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ia5SD-0005dK-Ta for qemu-devel@nongnu.org; Wed, 27 Nov 2019 17:06:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ia5SB-0002LF-TR for qemu-devel@nongnu.org; Wed, 27 Nov 2019 17:06:33 -0500 Received: from mail-lj1-x244.google.com ([2a00:1450:4864:20::244]:34109) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ia5S9-0002IA-SI for qemu-devel@nongnu.org; Wed, 27 Nov 2019 17:06:31 -0500 Received: by mail-lj1-x244.google.com with SMTP id m6so18788918ljc.1 for ; Wed, 27 Nov 2019 14:06:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Qc4fhvPidiFroBnj333xYm85MsYpPPDW+ASOMqwu3Z0=; b=hjWONevPmqr9P1/CJKMb5zNbQDTcZUL9RIaDEIj3ZieeKU+/yQ1Biae4yJ9YkpjR9p so+EXmmmVRFKxJ1T85Xh77aQyncWBVkP5cEGR8YMpionVvxViV1mP+Otm8mW5KKw6jVk 0YjUnsoCFVkBB58a+5NQbtY8tcQkBz55fE9KlnzdxCFCBhMYbwX+zWl5Y3RII3PT7iRC e4CsBitaIHKEgoZ+bio/0Ksl1a6hRAFupex6/aiulfq3Sc7Vha7B70n2vHoXU/TDDKOk 9XtE4sHjggmxEWqSo+v+7HRTCa51j7iY9bMYxEHvgJ/teoO+XqQ0qPeUR5XgrUmkaczq dILg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qc4fhvPidiFroBnj333xYm85MsYpPPDW+ASOMqwu3Z0=; b=fX6HZuudsgrpUE1BxNGv9oRnkpoVCegXEz9PZ5IY1XBp76cOsQWPbIvksrbul8qhye rgt0TglVJAitXDMavKjiFEVOQLVLiC5dIyRJwBcvoSCbbpM2DmWoa4EpcIlDc2d1sgFH qIxyP7vQdsGHUnF4Oa1ulfYF2c1hGTAQfm3WppMsErOP7rU3Mm1bBUlQws18DlVvksCK xF2vuDnpRyrzUB3VNlqp/IRuiPhOH9hyM4rHlL+eDq9gerqgs5fioLyeh4KgW5Ube9JK 5pnk0Ohumx0w8vUYCp4N7SQkWHv7XoJr+4UHkTRBX9gObrZqGxQ0PdEAvsiVXDoY4NWf u1ww== X-Gm-Message-State: APjAAAVHuTh5AgUcd4tnADNj/oxpM54wQcnnpJi81apx8yimGiV495rV ZUqjsbjSrHZdc5Bd+6d0+1goL3BV+mk= X-Google-Smtp-Source: APXvYqwrGIwLftk3VwmkyoE+XhsV58yTxHWQ1KqG2ZvSF83+fvJgtxwbbyXI0hQUsPdWni5MXx40mA== X-Received: by 2002:a2e:898a:: with SMTP id c10mr31965170lji.177.1574892386973; Wed, 27 Nov 2019 14:06:26 -0800 (PST) Received: from octofox.cadence.com (jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id r7sm7655611ljc.74.2019.11.27.14.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Nov 2019 14:06:26 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 1/2] exec: flush CPU TB cache in breakpoint_invalidate Date: Wed, 27 Nov 2019 14:06:01 -0800 Message-Id: <20191127220602.10827-2-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191127220602.10827-1-jcmvbkbc@gmail.com> References: <20191127220602.10827-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::244 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" When a breakpoint is inserted at location for which there's currently no virtual to physical translation no action is taken on CPU TB cache. If a TB for that virtual address already exists but is not visible ATM the breakpoint won't be hit next time an instruction at that address will be executed. Flush entire CPU TB cache in breakpoint_invalidate to force re-translation of all TBs for the breakpoint address. This change fixes the following scenario: - linux user application is running - a breakpoint is inserted from QEMU gdbstub for a user address that is not currently present in the target CPU TLB - an instruction at that address is executed, but the external debugger doesn't get control. Signed-off-by: Max Filippov --- Changes RFC->v1: - do tb_flush in breakpoint_invalidate unconditionally exec.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/exec.c b/exec.c index ffdb5185353b..1709b760edc1 100644 --- a/exec.c +++ b/exec.c @@ -1017,14 +1017,13 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) { - MemTxAttrs attrs; - hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs); - int asidx = cpu_asidx_from_attrs(cpu, attrs); - if (phys != -1) { - /* Locks grabbed by tb_invalidate_phys_addr */ - tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, - phys | (pc & ~TARGET_PAGE_MASK), attrs); - } + /* + * There may not be a virtual to physical translation for the pc + * right now, but there may exist cached TB for this pc. + * Flush the whole TB cache to force re-translation of such TBs. + * This is heavyweight, but we're debugging anyway. + */ + tb_flush(cpu); } #endif From patchwork Wed Nov 27 22:06:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11265013 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8420F6C1 for ; Wed, 27 Nov 2019 22:08:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 59819215F1 for ; Wed, 27 Nov 2019 22:08:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sIgkBB01" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 59819215F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:43650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ia5Tk-000703-Gd for patchwork-qemu-devel@patchwork.kernel.org; Wed, 27 Nov 2019 17:08:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33830) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ia5SF-0005dV-Uw for qemu-devel@nongnu.org; Wed, 27 Nov 2019 17:06:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ia5SD-0002MQ-Tb for qemu-devel@nongnu.org; Wed, 27 Nov 2019 17:06:35 -0500 Received: from mail-lj1-x241.google.com ([2a00:1450:4864:20::241]:38806) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ia5SB-0002KJ-UN for qemu-devel@nongnu.org; Wed, 27 Nov 2019 17:06:33 -0500 Received: by mail-lj1-x241.google.com with SMTP id k8so15618931ljh.5 for ; Wed, 27 Nov 2019 14:06:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xnSkwpgBsxk4jxzjerZiTGLcBtPdpU9VVVnBMPqJBW8=; b=sIgkBB01vtWNOOD10+zcIbaRjScBNIdBDjObLz7Fi19jARCO+J2hrf1+Z/CbaWDH93 InhhoWOOrgTLC0OA4Ec1q1KEaOOYMce5Ih5b+jJopWuXBGglBAQJdfDxRSjzYhIHr78r CwrEMF0tlLHAhO91FE6oa+7MHcvyNODwosHwJqCu6xK/LkiHjqhQwhqsZiuqaQUoGrsE Xwi5Fdfq91XhODGJJgN/Fukqd0c+JCRpF9Q2bB6Y1reKcrpU7AZRENI0t9YgcTHVGZZx VZ6RbPS25GfyvrfgUMcJ0Bi1gipNjZwVW8m/+B94veTguJCVwJRfZXP8r8ReybdMld8D /Y1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xnSkwpgBsxk4jxzjerZiTGLcBtPdpU9VVVnBMPqJBW8=; b=O1IJWDL/yYIgyx0YxJfuoc9rfhRsEus1MVv1VXnMsG2/FrzCHKBGZdD4sKYHxq7f0k d/YAI6t90AH0xgOJyHfwYXBsvR3KnCzTcGSOiBNK+Dc/1/ZcCz8zsUylaz7E2UAneMqc 6ejR5wy2drbfO8dBhJV4ZvYmNLvCRRiKARJeRrPcGDoxc0m2JRX7iNVRyU31Api06pbN sc/IwM9dgF/8kNu3tXpcJ8Ei4ShfeyXO181pw1wLNOpuzphV2D9imh+5B+m2A2avF9EQ ydVnNLfNkR3O9R1xMwtSbomqhEvsZGqf3q4Q0xH9kN7qYwvsMw6j1XvKm8JFfCHztNav 5TwQ== X-Gm-Message-State: APjAAAXANRZiNOEil9Vb8Zidc8G4UfuyAav2v2uWtMAVeDfsr0ti/LED l4zcZQg7MbkmY6c4DAZgyNmatdbaRck= X-Google-Smtp-Source: APXvYqxoCzVX7jH5dENPn+kPXdm6Pp+bD0haV1CZEsvxpW+0Ub+R2NZyss+0P/hMvDEEeZpw8BLoQA== X-Received: by 2002:a2e:9607:: with SMTP id v7mr4317897ljh.72.1574892389690; Wed, 27 Nov 2019 14:06:29 -0800 (PST) Received: from octofox.cadence.com (jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id r7sm7655611ljc.74.2019.11.27.14.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Nov 2019 14:06:29 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 2/2] exec: drop tb_invalidate_phys_addr Date: Wed, 27 Nov 2019 14:06:02 -0800 Message-Id: <20191127220602.10827-3-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191127220602.10827-1-jcmvbkbc@gmail.com> References: <20191127220602.10827-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::241 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The only remaining user of tb_invalidate_phys_addr is target/xtensa instruction breakpoint code and it is better to use tb_flush there. Drop tb_invalidate_phys_addr implementations and declarations. Use tb_flush in xtensa IBREAK helpers. Signed-off-by: Max Filippov Reviewed-by: Richard Henderson --- exec.c | 29 ++--------------------------- include/exec/exec-all.h | 3 --- target/xtensa/dbg_helper.c | 19 +++---------------- 3 files changed, 5 insertions(+), 46 deletions(-) diff --git a/exec.c b/exec.c index 1709b760edc1..4d20fc005520 100644 --- a/exec.c +++ b/exec.c @@ -983,38 +983,13 @@ const char *parse_cpu_option(const char *cpu_option) } #if defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(target_ulong addr) +static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) { mmap_lock(); - tb_invalidate_phys_page_range(addr, addr + 1); + tb_invalidate_phys_page_range(pc, pc + 1); mmap_unlock(); } - -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) -{ - tb_invalidate_phys_addr(pc); -} #else -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) -{ - ram_addr_t ram_addr; - MemoryRegion *mr; - hwaddr l = 1; - - if (!tcg_enabled()) { - return; - } - - RCU_READ_LOCK_GUARD(); - mr = address_space_translate(as, addr, &addr, &l, false, attrs); - if (!(memory_region_is_ram(mr) - || memory_region_is_romd(mr))) { - return; - } - ram_addr = memory_region_get_ram_addr(mr) + addr; - tb_invalidate_phys_page_range(ram_addr, ram_addr + 1); -} - static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) { /* diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d85e610e85b9..585fe7ff430c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -449,10 +449,7 @@ static inline uint32_t curr_cflags(void) /* TranslationBlock invalidate API */ #if defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(target_ulong addr); void tb_invalidate_phys_range(target_ulong start, target_ulong end); -#else -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); #endif void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index be1f81107b43..2481dc326fba 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -33,19 +33,6 @@ #include "exec/exec-all.h" #include "exec/address-spaces.h" -static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) -{ - uint32_t paddr; - uint32_t page_size; - unsigned access; - int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, - &paddr, &page_size, &access); - if (ret == 0) { - tb_invalidate_phys_addr(&address_space_memory, paddr, - MEMTXATTRS_UNSPECIFIED); - } -} - void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) { uint32_t change = v ^ env->sregs[IBREAKENABLE]; @@ -53,7 +40,8 @@ void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) for (i = 0; i < env->config->nibreak; ++i) { if (change & (1 << i)) { - tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); + tb_flush(env_cpu(env)); + break; } } env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1); @@ -62,8 +50,7 @@ void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) { if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) { - tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); - tb_invalidate_virtual_addr(env, v); + tb_flush(env_cpu(env)); } env->sregs[IBREAKA + i] = v; }