From patchwork Sun Dec 15 20:04:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11293145 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 24777109A for ; Sun, 15 Dec 2019 20:05:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 01B342467A for ; Sun, 15 Dec 2019 20:05:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="o2wysAte" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726267AbfLOUFD (ORCPT ); Sun, 15 Dec 2019 15:05:03 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:40680 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726146AbfLOUFD (ORCPT ); Sun, 15 Dec 2019 15:05:03 -0500 Received: by mail-pg1-f196.google.com with SMTP id k25so2426547pgt.7; Sun, 15 Dec 2019 12:05:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xIgln2CTeNUTcohT4yCRcrSFMvesnt3sC8dwNxQQtUM=; b=o2wysAteIijZ8tWGZKG3kD7OLB1HVQ98F+1acPL7apqrId+6bkSJZp4bfeQPcLTcCD W5zJdE9b8FfrrxIQq6rg5wWqgxa1Slp9K5vgMHjhOYD3g/FiPj97CRVs4giFDnmA5GRG nBEw8JDPILEc6VehgT3fCDIidNQYVDmkTwwKIVhcVWY7GfxqNhk7VtPAsAqJDk5GjSU7 nHvQB+momWt3yrCoLOHZ1qraHWRt5BDUr3d6ZW5R2GvkYBczxl6ZuBY5Yat4RqDPCm+3 VbSoSGG2PgXYDLxJj38VD3pwr/8x8Wx1sjMpswhQCx3Dhr0L6y3Y0xiyXOOTOC+fYNSu 91dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xIgln2CTeNUTcohT4yCRcrSFMvesnt3sC8dwNxQQtUM=; b=HWp+512Fgjulh3mWvohdB2i1ce+bQvJ1gRDf0Ez+YZt1JJZxoPLFY2j6VSi6PporSK qrBNJZzjBLhOZVfUdURydsnVxWrzGXR4f6KClea8pvj/1YB8m+fJv32pBox7YZEiJdT7 suahpivOIeOpfJAY1BwF1QoYMNShCqx79kSfSfWqPlZsnCRI6IwX0DINUx7sq6SsU7P7 MwECH9zsVhUdI27RCF8yy2ZxwPr7l1n4LwpsyDhGWd3fVAD/HwTRoF0rFb6XWwKB4rcl JB5sYB/niIXsUkGosVG2YnAE5DwkXwVtRFWIYj25dJvKm5sgUJNxNkfWD+J321E9AYfh 996g== X-Gm-Message-State: APjAAAWZ+0Z7eMWvWnmZNncADf8fLbSqvJX2IsEz7XNzICJ5HXRnbKyK DYllA7yGiwL1taFslDsWSyhflwVv X-Google-Smtp-Source: APXvYqwhMYzq9LVfNRlgXR0Z/3qbGzkkpOo79arI9v4XBwf4PSol4vSxiffMt0IkLYIKZtwLVmBK6g== X-Received: by 2002:a63:4f64:: with SMTP id p36mr14378616pgl.271.1576440302589; Sun, 15 Dec 2019 12:05:02 -0800 (PST) Received: from localhost (c-73-25-156-94.hsd1.or.comcast.net. [73.25.156.94]) by smtp.gmail.com with ESMTPSA id c8sm18881075pfj.106.2019.12.15.12.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Dec 2019 12:05:01 -0800 (PST) From: Rob Clark To: Douglas Anderson Cc: Andrzej Hajda , Neil Armstrong , Rob Clark , Jernej Skrabec , Jonas Karlman , David Airlie , linux-arm-msm , dri-devel , Bjorn Andersson , Sean Paul , Laurent Pinchart , Linux Kernel Mailing List , Daniel Vetter Subject: [PATCH 1/2] fixup! drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail Date: Sun, 15 Dec 2019 12:04:59 -0800 Message-Id: <20191215200459.1018893-1-robdclark@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191213154448.8.I251add713bc5c97225200894ab110ea9183434fd@changeid> References: <20191213154448.8.I251add713bc5c97225200894ab110ea9183434fd@changeid> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Fixes: In file included from ../drivers/gpu/drm/bridge/ti-sn65dsi86.c:25: ../drivers/gpu/drm/bridge/ti-sn65dsi86.c: In function ‘ti_sn_bridge_enable’: ../include/drm/drm_print.h:339:2: warning: ‘last_err_str’ may be used uninitialized in this function [-Wmaybe-uninitialized] 339 | drm_dev_printk(dev, KERN_ERR, "*ERROR* " fmt, ##__VA_ARGS__) | ^~~~~~~~~~~~~~ ../drivers/gpu/drm/bridge/ti-sn65dsi86.c:650:14: note: ‘last_err_str’ was declared here 650 | const char *last_err_str; | ^~~~~~~~~~~~ In file included from ../drivers/gpu/drm/bridge/ti-sn65dsi86.c:25: ../include/drm/drm_print.h:339:2: warning: ‘ret’ may be used uninitialized in this function [-Wmaybe-uninitialized] 339 | drm_dev_printk(dev, KERN_ERR, "*ERROR* " fmt, ##__VA_ARGS__) | ^~~~~~~~~~~~~~ ../drivers/gpu/drm/bridge/ti-sn65dsi86.c:654:6: note: ‘ret’ was declared here 654 | int ret; | ^~~ Building modules, stage 2. --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index cb774ee536cd..976f98991b3d 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -618,11 +618,11 @@ static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx, static void ti_sn_bridge_enable(struct drm_bridge *bridge) { struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); - const char *last_err_str; + const char *last_err_str = "No supported DP rate"; int dp_rate_idx; int max_dp_rate_idx; unsigned int val; - int ret; + int ret = -EINVAL; /* * Run with the maximum number of lanes that the DP sink supports. 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[73.25.156.94]) by smtp.gmail.com with ESMTPSA id l66sm18645744pga.30.2019.12.15.12.06.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Dec 2019 12:06:33 -0800 (PST) From: Rob Clark To: Douglas Anderson Cc: Andrzej Hajda , Neil Armstrong , Rob Clark , Jernej Skrabec , Jonas Karlman , David Airlie , linux-arm-msm , dri-devel , Bjorn Andersson , Sean Paul , Laurent Pinchart , Linux Kernel Mailing List , Daniel Vetter Subject: [PATCH 2/2] fixup! drm/bridge: ti-sn65dsi86: Skip non-standard DP rates Date: Sun, 15 Dec 2019 12:06:32 -0800 Message-Id: <20191215200632.1019065-1-robdclark@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191213154448.9.I1791f91dd22894da04f86699a7507d101d4385bc@changeid> References: <20191213154448.9.I1791f91dd22894da04f86699a7507d101d4385bc@changeid> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark --- Note however, the panel I have on the yoga c630 is not eDP 1.4+, so I cannot test that path. But I think it looks correct. drivers/gpu/drm/bridge/ti-sn65dsi86.c | 110 +++++++++++++++++++++----- 1 file changed, 89 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 976f98991b3d..1cb53be7c9e9 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -102,6 +102,9 @@ struct ti_sn_bridge { struct gpio_desc *enable_gpio; struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; int dp_lanes; + u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; + int num_sink_rates; + int sink_rate_idxs[DP_MAX_SUPPORTED_RATES]; }; static const struct regmap_range ti_sn_bridge_volatile_ranges[] = { @@ -454,15 +457,6 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 }; -/** - * A table indicating which of the rates in ti_sn_bridge_dp_rate_lut - * is as per the DP spec (AKA a standard) as opposed to an intermediate - * rate. - */ -static const bool ti_sn_bridge_dp_rate_standard[] = { - false, true, false, false, true, false, false, true -}; - static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata) { unsigned int bit_rate_khz, dp_rate_mhz; @@ -573,11 +567,95 @@ static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) return data & DP_LANE_COUNT_MASK; } +/* TODO possibly fold ti_sn_get_max_lanes() into this? */ +static void ti_sn_read_sink_config(struct ti_sn_bridge *pdata) +{ + memset(pdata->edp_dpcd, 0, sizeof(pdata->edp_dpcd)); + + /* + * Read the eDP display control registers. + * + * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in + * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it + * set, but require eDP 1.4+ detection (e.g. for supported link rates + * method). The display control registers should read zero if they're + * not supported anyway. + */ + if (drm_dp_dpcd_read(&pdata->aux, DP_EDP_DPCD_REV, + pdata->edp_dpcd, sizeof(pdata->edp_dpcd)) == + sizeof(pdata->edp_dpcd)) + DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(pdata->edp_dpcd), + pdata->edp_dpcd); + + /* Read the eDP 1.4+ supported link rates. */ + if (pdata->edp_dpcd[0] >= DP_EDP_14) { + __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; + int i, j; + + drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, + sink_rates, sizeof(sink_rates)); + + for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { + int val = le16_to_cpu(sink_rates[i]); + int rate_mhz; + + if (val == 0) + break; + + /* Value read multiplied by 200kHz gives the per-lane + * link rate in kHz. The source rates are, however, + * stored in MHz + */ + rate_mhz = DIV_ROUND_UP(val * 200, 1000); + + /* If the rate is also supported by the bridge, add it + * to the table of supported rates: + */ + for (j = 1; j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); j++) { + if (rate_mhz == ti_sn_bridge_dp_rate_lut[j]) { + pdata->sink_rate_idxs[pdata->num_sink_rates++] = j; + break; + } + } + } + pdata->num_sink_rates = i; + } else { + int i; + + /** + * A table indicating which of the rates in ti_sn_bridge_dp_rate_lut + * is as per the DP spec (AKA a standard) as opposed to an intermediate + * rate. + */ + static const bool ti_sn_bridge_dp_rate_standard[] = { + false, true, false, false, true, false, false, true + }; + + /* if prior to eDP 1.4, then just use the supported standard rates: */ + for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { + if (!ti_sn_bridge_dp_rate_standard[i]) + continue; + pdata->sink_rate_idxs[pdata->num_sink_rates++] = i; + } + } +} + static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx, const char **last_err_str) { unsigned int val; int ret; + int i; + + /* check for supported rate: */ + for (i = 0; i < pdata->num_sink_rates; i++) + if (pdata->sink_rate_idxs[i] == dp_rate_idx) + break; + + if (i == pdata->num_sink_rates) { + *last_err_str = "Unsupported rate"; + return -EINVAL; + } /* set dp clk frequency value */ regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, @@ -624,6 +702,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) unsigned int val; int ret = -EINVAL; + ti_sn_read_sink_config(pdata); + /* * Run with the maximum number of lanes that the DP sink supports. * @@ -669,18 +749,6 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata); dp_rate_idx <= max_dp_rate_idx; dp_rate_idx++) { - /* - * To be on the safe side, we'll skip all non-standard - * rates and move up to the next standard one. This is - * because some panels will pass link training with a non- - * standard rate but just show garbage. If the non-standard - * rates are useful we should figure out how to enable them - * through querying the panel, having a per-panel whitelist, - * or adding a DT property. - */ - if (!ti_sn_bridge_dp_rate_standard[dp_rate_idx]) - continue; - ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); if (!ret) break;