From patchwork Wed Dec 18 19:48:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11301827 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 91041197C for ; Wed, 18 Dec 2019 19:48:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6F6BD24672 for ; Wed, 18 Dec 2019 19:48:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726984AbfLRTsT (ORCPT ); Wed, 18 Dec 2019 14:48:19 -0500 Received: from andre.telenet-ops.be ([195.130.132.53]:32984 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727548AbfLRTsS (ORCPT ); Wed, 18 Dec 2019 14:48:18 -0500 Received: from ramsan ([84.195.182.253]) by andre.telenet-ops.be with bizsmtp id fXoF2100T5USYZQ01XoFkV; Wed, 18 Dec 2019 20:48:16 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfIt-0007xl-EK; Wed, 18 Dec 2019 20:48:15 +0100 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1ihfIt-0003KM-DH; Wed, 18 Dec 2019 20:48:15 +0100 From: Geert Uytterhoeven To: Linus Walleij , Yoshinori Sato , Rich Felker Cc: linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 1/6] pinctrl: sh-pfc: r8a7778: Fix duplicate SDSELF_B and SD1_CLK_B Date: Wed, 18 Dec 2019 20:48:07 +0100 Message-Id: <20191218194812.12741-2-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191218194812.12741-1-geert+renesas@glider.be> References: <20191218194812.12741-1-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org The FN_SDSELF_B and FN_SD1_CLK_B enum IDs are used twice, which means one set of users must be wrong. Replace them by the correct enum IDs. Fixes: 87f8c988636db0d4 ("sh-pfc: Add r8a7778 pinmux support") Signed-off-by: Geert Uytterhoeven --- The runtime-check under development reports: r8a7778_pfc: config reg 0xfffc002c/54 enum_id 613 conflict r8a7778_pfc: config reg 0xfffc002c/70 enum_id 607 conflict --- drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index 24866a5958aee512..a9875038ed9b664e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -2305,7 +2305,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ATAG0_A, 0, FN_REMOCON_B, 0, /* IP0_11_8 [4] */ FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS, - FN_ATADIR0_A, 0, FN_SDSELF_B, 0, + FN_ATADIR0_A, 0, FN_SDSELF_A, 0, FN_PWM4_B, 0, 0, 0, 0, 0, 0, 0, /* IP0_7_5 [3] */ @@ -2349,7 +2349,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_TS_SDAT0_A, 0, 0, 0, 0, 0, 0, 0, /* IP1_10_8 [3] */ - FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24, + FN_SD1_CD_A, FN_MMC_D6, 0, FN_A24, FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A, /* IP1_7_5 [3] */ FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, From patchwork Wed Dec 18 19:48:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11301817 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC6F714B7 for ; Wed, 18 Dec 2019 19:48:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 932B621582 for ; Wed, 18 Dec 2019 19:48:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727587AbfLRTsS (ORCPT ); Wed, 18 Dec 2019 14:48:18 -0500 Received: from laurent.telenet-ops.be ([195.130.137.89]:48022 "EHLO laurent.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727386AbfLRTsS (ORCPT ); Wed, 18 Dec 2019 14:48:18 -0500 Received: from ramsan ([84.195.182.253]) by laurent.telenet-ops.be with bizsmtp id fXoF2100E5USYZQ01XoFXL; Wed, 18 Dec 2019 20:48:16 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfIt-0007xm-Em; Wed, 18 Dec 2019 20:48:15 +0100 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1ihfIt-0003KO-Du; Wed, 18 Dec 2019 20:48:15 +0100 From: Geert Uytterhoeven To: Linus Walleij , Yoshinori Sato , Rich Felker Cc: linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 2/6] pinctrl: sh-pfc: sh7264: Fix Port K I/O Register 0 definition Date: Wed, 18 Dec 2019 20:48:08 +0100 Message-Id: <20191218194812.12741-3-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191218194812.12741-1-geert+renesas@glider.be> References: <20191218194812.12741-1-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org The register definition for the Port K I/O Register is accidentally using the defines for Port J. Replace them by the proper Port K defines. Signed-off-by: Geert Uytterhoeven --- The runtime-check under development reports: sh7264_pfc: config reg 0xfffe3932/8 enum_id 234 conflict sh7264_pfc: config reg 0xfffe3932/9 enum_id 360 conflict sh7264_pfc: config reg 0xfffe3932/10 enum_id 235 conflict sh7264_pfc: config reg 0xfffe3932/11 enum_id 361 conflict sh7264_pfc: config reg 0xfffe3932/12 enum_id 236 conflict sh7264_pfc: config reg 0xfffe3932/13 enum_id 362 conflict sh7264_pfc: config reg 0xfffe3932/14 enum_id 237 conflict sh7264_pfc: config reg 0xfffe3932/15 enum_id 363 conflict --- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 4a95867deb8af42a..4117bd8c0f413f99 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -2020,18 +2020,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1, GROUP( 0, 0, 0, 0, 0, 0, 0, 0, - PJ11_IN, PJ11_OUT, - PJ10_IN, PJ10_OUT, - PJ9_IN, PJ9_OUT, - PJ8_IN, PJ8_OUT, - PJ7_IN, PJ7_OUT, - PJ6_IN, PJ6_OUT, - PJ5_IN, PJ5_OUT, - PJ4_IN, PJ4_OUT, - PJ3_IN, PJ3_OUT, - PJ2_IN, PJ2_OUT, - PJ1_IN, PJ1_OUT, - PJ0_IN, PJ0_OUT )) + PK11_IN, PK11_OUT, + PK10_IN, PK10_OUT, + PK9_IN, PK9_OUT, + PK8_IN, PK8_OUT, + PK7_IN, PK7_OUT, + PK6_IN, PK6_OUT, + PK5_IN, PK5_OUT, + PK4_IN, PK4_OUT, + PK3_IN, PK3_OUT, + PK2_IN, PK2_OUT, + PK1_IN, PK1_OUT, + PK0_IN, PK0_OUT )) }, {} }; From patchwork Wed Dec 18 19:48:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11301833 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 089511593 for ; Wed, 18 Dec 2019 19:48:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E4DEA2082E for ; Wed, 18 Dec 2019 19:48:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727553AbfLRTsT (ORCPT ); Wed, 18 Dec 2019 14:48:19 -0500 Received: from baptiste.telenet-ops.be ([195.130.132.51]:56572 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727549AbfLRTsS (ORCPT ); Wed, 18 Dec 2019 14:48:18 -0500 Received: from ramsan ([84.195.182.253]) by baptiste.telenet-ops.be with bizsmtp id fXoF2100N5USYZQ01XoFDL; Wed, 18 Dec 2019 20:48:16 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfIt-0007xq-GK; Wed, 18 Dec 2019 20:48:15 +0100 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1ihfIt-0003KS-Ec; Wed, 18 Dec 2019 20:48:15 +0100 From: Geert Uytterhoeven To: Linus Walleij , Yoshinori Sato , Rich Felker Cc: linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 3/6] pinctrl: sh-pfc: sh7264: Fix CAN function GPIOs Date: Wed, 18 Dec 2019 20:48:09 +0100 Message-Id: <20191218194812.12741-4-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191218194812.12741-1-geert+renesas@glider.be> References: <20191218194812.12741-1-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org pinmux_func_gpios[] contains a hole due to the missing function GPIO definition for the "CTX0&CTX1" signal, which is the logical "AND" of the two CAN outputs. Fix this by: - Renaming CRX0_CRX1_MARK to CTX0_CTX1_MARK, as PJ2MD[2:0]=010 configures the combined "CTX0&CTX1" output signal, - Renaming CRX0X1_MARK to CRX0_CRX1_MARK, as PJ3MD[1:0]=10 configures the shared "CRX0/CRX1" input signal, which is fed to both CAN inputs, - Adding the missing function GPIO definition for "CTX0&CTX1" to pinmux_func_gpios[], - Moving all CAN enums next to each other. See SH7262 Group, SH7264 Group User's Manual: Hardware, Rev. 4.00: [1] Figure 1.2 (3) (Pin Assignment for the SH7264 Group (1-Mbyte Version), [2] Figure 1.2 (4) Pin Assignment for the SH7264 Group (640-Kbyte Version, [3] Table 1.4 List of Pins, [4] Figure 20.29 Connection Example when Using This Module as 1-Channel Module (64 Mailboxes x 1 Channel), [5] Table 32.10 Multiplexed Pins (Port J), [6] Section 32.2.30 (3) Port J Control Register 0 (PJCR0). Note that the last 2 disagree about PJ2MD[2:0], which is probably the root cause of this bug. But considering [4], "CTx0&CTx1" in [5] must be correct, and "CRx0&CRx1" in [6] must be wrong. Signed-off-by: Geert Uytterhoeven --- The runtime-check under development reports: sh7264_pfc: empty function gpio 23 --- drivers/pinctrl/sh-pfc/pfc-sh7264.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c index 4117bd8c0f413f99..908837ea487bdcb9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c @@ -497,17 +497,15 @@ enum { SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK, CRX0_MARK, CRX1_MARK, CTX0_MARK, CTX1_MARK, + CRX0_CRX1_MARK, CTX0_CTX1_MARK, PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK, PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK, PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK, PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK, IERXD_MARK, IETXD_MARK, - CRX0_CRX1_MARK, WDTOVF_MARK, - CRX0X1_MARK, - /* DMAC */ TEND0_MARK, DACK0_MARK, DREQ0_MARK, TEND1_MARK, DACK1_MARK, DREQ1_MARK, @@ -995,12 +993,12 @@ static const u16 pinmux_data[] = { PINMUX_DATA(PJ3_DATA, PJ3MD_00), PINMUX_DATA(CRX1_MARK, PJ3MD_01), - PINMUX_DATA(CRX0X1_MARK, PJ3MD_10), + PINMUX_DATA(CRX0_CRX1_MARK, PJ3MD_10), PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11), PINMUX_DATA(PJ2_DATA, PJ2MD_000), PINMUX_DATA(CTX1_MARK, PJ2MD_001), - PINMUX_DATA(CRX0_CRX1_MARK, PJ2MD_010), + PINMUX_DATA(CTX0_CTX1_MARK, PJ2MD_010), PINMUX_DATA(CS2_MARK, PJ2MD_011), PINMUX_DATA(SCK0_MARK, PJ2MD_100), PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101), @@ -1245,6 +1243,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(CTX1), GPIO_FN(CRX1), GPIO_FN(CTX0), + GPIO_FN(CTX0_CTX1), GPIO_FN(CRX0), GPIO_FN(CRX0_CRX1), From patchwork Wed Dec 18 19:48:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11301829 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B175F19A2 for ; Wed, 18 Dec 2019 19:48:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 99D692082E for ; Wed, 18 Dec 2019 19:48:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727548AbfLRTsT (ORCPT ); Wed, 18 Dec 2019 14:48:19 -0500 Received: from laurent.telenet-ops.be ([195.130.137.89]:48036 "EHLO laurent.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727577AbfLRTsS (ORCPT ); Wed, 18 Dec 2019 14:48:18 -0500 Received: from ramsan ([84.195.182.253]) by laurent.telenet-ops.be with bizsmtp id fXoF2100N5USYZQ01XoFXN; Wed, 18 Dec 2019 20:48:16 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfIt-0007xs-HK; Wed, 18 Dec 2019 20:48:15 +0100 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1ihfIt-0003KV-GB; Wed, 18 Dec 2019 20:48:15 +0100 From: Geert Uytterhoeven To: Linus Walleij , Yoshinori Sato , Rich Felker Cc: linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 4/6] pinctrl: sh-pfc: sh7269: Fix CAN function GPIOs Date: Wed, 18 Dec 2019 20:48:10 +0100 Message-Id: <20191218194812.12741-5-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191218194812.12741-1-geert+renesas@glider.be> References: <20191218194812.12741-1-geert+renesas@glider.be> MIME-Version: 1.0 Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org pinmux_func_gpios[] contains a hole due to the missing function GPIO definition for the "CTX0&CTX1" signal, which is the logical "AND" of the first two CAN outputs. A closer look reveals other issues: - Some functionality is available on alternative pins, but the PINMUX_DATA() entries is using the wrong marks, - Several configurations are missing. Fix this by: - Renaming CTX0CTX1CTX2_MARK, CRX0CRX1_PJ22_MARK, and CRX0CRX1CRX2_PJ20_MARK to CTX0_CTX1_CTX2_MARK, CRX0_CRX1_PJ22_MARK, resp. CRX0_CRX1_CRX2_PJ20_MARK for consistency with the corresponding enum IDs, - Adding all missing enum IDs and marks, - Use the right (*_PJ2x) variants for alternative pins, - Adding all missing configurations to pinmux_data[], - Adding all missing function GPIO definitions to pinmux_func_gpios[]. See SH7268 Group, SH7269 Group User’s Manual: Hardware, Rev. 2.00: [1] Table 1.4 List of Pins [2] Figure 23.29 Connection Example when Using Channels 0 and 1 as One Channel (64 Mailboxes × 1 Channel) and Channel 2 as One Channel (32 Mailboxes × 1 Channel), [3] Figure 23.30 Connection Example when Using Channels 0, 1, and 2 as One Channel (96 Mailboxes × 1 Channel), [4] Table 48.3 Multiplexed Pins (Port B), [5] Table 48.4 Multiplexed Pins (Port C), [6] Table 48.10 Multiplexed Pins (Port J), [7] Section 48.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5). Signed-off-by: Geert Uytterhoeven --- The runtime-check under development reports: sh7269_pfc: empty function gpio 46 --- arch/sh/include/cpu-sh2a/cpu/sh7269.h | 11 ++++++-- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 39 ++++++++++++++++++--------- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7269.h b/arch/sh/include/cpu-sh2a/cpu/sh7269.h index d516e5d488180db7..b887cc402b712557 100644 --- a/arch/sh/include/cpu-sh2a/cpu/sh7269.h +++ b/arch/sh/include/cpu-sh2a/cpu/sh7269.h @@ -78,8 +78,15 @@ enum { GPIO_FN_WDTOVF, /* CAN */ - GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1, - GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2, + GPIO_FN_CTX2, GPIO_FN_CRX2, + GPIO_FN_CTX1, GPIO_FN_CRX1, + GPIO_FN_CTX0, GPIO_FN_CRX0, + GPIO_FN_CTX0_CTX1, GPIO_FN_CRX0_CRX1, + GPIO_FN_CTX0_CTX1_CTX2, GPIO_FN_CRX0_CRX1_CRX2, + GPIO_FN_CTX2_PJ21, GPIO_FN_CRX2_PJ20, + GPIO_FN_CTX1_PJ23, GPIO_FN_CRX1_PJ22, + GPIO_FN_CTX0_CTX1_PJ23, GPIO_FN_CRX0_CRX1_PJ22, + GPIO_FN_CTX0_CTX1_CTX2_PJ21, GPIO_FN_CRX0_CRX1_CRX2_PJ20, /* DMAC */ GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0, diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index 6cbb18ef77dc04ae..d20974a55d93add1 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -737,13 +737,12 @@ enum { CRX0_MARK, CTX0_MARK, CRX1_MARK, CTX1_MARK, CRX2_MARK, CTX2_MARK, - CRX0_CRX1_MARK, - CRX0_CRX1_CRX2_MARK, - CTX0CTX1CTX2_MARK, + CRX0_CRX1_MARK, CTX0_CTX1_MARK, + CRX0_CRX1_CRX2_MARK, CTX0_CTX1_CTX2_MARK, CRX1_PJ22_MARK, CTX1_PJ23_MARK, CRX2_PJ20_MARK, CTX2_PJ21_MARK, - CRX0CRX1_PJ22_MARK, - CRX0CRX1CRX2_PJ20_MARK, + CRX0_CRX1_PJ22_MARK, CTX0_CTX1_PJ23_MARK, + CRX0_CRX1_CRX2_PJ20_MARK, CTX0_CTX1_CTX2_PJ21_MARK, /* VDC */ DV_CLK_MARK, @@ -821,6 +820,7 @@ static const u16 pinmux_data[] = { PINMUX_DATA(CS3_MARK, PC8MD_001), PINMUX_DATA(TXD7_MARK, PC8MD_010), PINMUX_DATA(CTX1_MARK, PC8MD_011), + PINMUX_DATA(CTX0_CTX1_MARK, PC8MD_100), PINMUX_DATA(PC7_DATA, PC7MD_000), PINMUX_DATA(CKE_MARK, PC7MD_001), @@ -833,11 +833,12 @@ static const u16 pinmux_data[] = { PINMUX_DATA(CAS_MARK, PC6MD_001), PINMUX_DATA(SCK7_MARK, PC6MD_010), PINMUX_DATA(CTX0_MARK, PC6MD_011), + PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC6MD_100), PINMUX_DATA(PC5_DATA, PC5MD_000), PINMUX_DATA(RAS_MARK, PC5MD_001), PINMUX_DATA(CRX0_MARK, PC5MD_011), - PINMUX_DATA(CTX0CTX1CTX2_MARK, PC5MD_100), + PINMUX_DATA(CTX0_CTX1_CTX2_MARK, PC5MD_100), PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101), PINMUX_DATA(PC4_DATA, PC4MD_00), @@ -1289,30 +1290,32 @@ static const u16 pinmux_data[] = { PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010), PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011), PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100), - PINMUX_DATA(CTX1_MARK, PJ23MD_101), + PINMUX_DATA(CTX1_PJ23_MARK, PJ23MD_101), + PINMUX_DATA(CTX0_CTX1_PJ23_MARK, PJ23MD_110), PINMUX_DATA(PJ22_DATA, PJ22MD_000), PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001), PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010), PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011), PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100), - PINMUX_DATA(CRX1_MARK, PJ22MD_101), - PINMUX_DATA(CRX0_CRX1_MARK, PJ22MD_110), + PINMUX_DATA(CRX1_PJ22_MARK, PJ22MD_101), + PINMUX_DATA(CRX0_CRX1_PJ22_MARK, PJ22MD_110), PINMUX_DATA(PJ21_DATA, PJ21MD_000), PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001), PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010), PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011), PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100), - PINMUX_DATA(CTX2_MARK, PJ21MD_101), + PINMUX_DATA(CTX2_PJ21_MARK, PJ21MD_101), + PINMUX_DATA(CTX0_CTX1_CTX2_PJ21_MARK, PJ21MD_110), PINMUX_DATA(PJ20_DATA, PJ20MD_000), PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001), PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010), PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011), PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100), - PINMUX_DATA(CRX2_MARK, PJ20MD_101), - PINMUX_DATA(CRX0CRX1CRX2_PJ20_MARK, PJ20MD_110), + PINMUX_DATA(CRX2_PJ20_MARK, PJ20MD_101), + PINMUX_DATA(CRX0_CRX1_CRX2_PJ20_MARK, PJ20MD_110), PINMUX_DATA(PJ19_DATA, PJ19MD_000), PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001), @@ -1663,12 +1666,24 @@ static const struct pinmux_func pinmux_func_gpios[] = { GPIO_FN(WDTOVF), /* CAN */ + GPIO_FN(CTX2), + GPIO_FN(CRX2), GPIO_FN(CTX1), GPIO_FN(CRX1), GPIO_FN(CTX0), GPIO_FN(CRX0), + GPIO_FN(CTX0_CTX1), GPIO_FN(CRX0_CRX1), + GPIO_FN(CTX0_CTX1_CTX2), GPIO_FN(CRX0_CRX1_CRX2), + GPIO_FN(CTX2_PJ21), + GPIO_FN(CRX2_PJ20), + GPIO_FN(CTX1_PJ23), + GPIO_FN(CRX1_PJ22), + GPIO_FN(CTX0_CTX1_PJ23), + GPIO_FN(CRX0_CRX1_PJ22), + GPIO_FN(CTX0_CTX1_CTX2_PJ21), + GPIO_FN(CRX0_CRX1_CRX2_PJ20), /* DMAC */ GPIO_FN(TEND0), From patchwork Wed Dec 18 19:48:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11301837 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5D84C14B7 for ; Wed, 18 Dec 2019 19:48:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3C1EB227BF for ; Wed, 18 Dec 2019 19:48:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727549AbfLRTsT (ORCPT ); Wed, 18 Dec 2019 14:48:19 -0500 Received: from xavier.telenet-ops.be ([195.130.132.52]:60670 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727576AbfLRTsT (ORCPT ); Wed, 18 Dec 2019 14:48:19 -0500 Received: from ramsan ([84.195.182.253]) by xavier.telenet-ops.be with bizsmtp id fXoF2100a5USYZQ01XoFrg; Wed, 18 Dec 2019 20:48:16 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfIt-0007xy-II; Wed, 18 Dec 2019 20:48:15 +0100 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1ihfIt-0003KY-H5; Wed, 18 Dec 2019 20:48:15 +0100 From: Geert Uytterhoeven To: Linus Walleij , Yoshinori Sato , Rich Felker Cc: linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 5/6] sh: sh7264: Remove bogus SSU GPIO function definitions Date: Wed, 18 Dec 2019 20:48:11 +0100 Message-Id: <20191218194812.12741-6-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191218194812.12741-1-geert+renesas@glider.be> References: <20191218194812.12741-1-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org SH7264 has no Synchronous Serial Communication Unit (SSU). Remove the bogus enum IDs, which caused holes in pinmux_func_gpios[]. Signed-off-by: Geert Uytterhoeven --- Presumably this has been copied from sh7203. The runtime-check under development reports: sh7264_pfc: empty function gpio 118 sh7264_pfc: empty function gpio 119 sh7264_pfc: empty function gpio 120 sh7264_pfc: empty function gpio 121 sh7264_pfc: empty function gpio 122 sh7264_pfc: empty function gpio 123 sh7264_pfc: empty function gpio 124 sh7264_pfc: empty function gpio 125 sh7264_pfc: empty function gpio 126 sh7264_pfc: empty function gpio 127 sh7264_pfc: empty function gpio 128 sh7264_pfc: empty function gpio 129 sh7264_pfc: empty function gpio 130 sh7264_pfc: empty function gpio 131 sh7264_pfc: empty function gpio 132 sh7264_pfc: empty function gpio 133 --- arch/sh/include/cpu-sh2a/cpu/sh7264.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7264.h b/arch/sh/include/cpu-sh2a/cpu/sh7264.h index d12c1918684518b3..8a1338aaf10a5c41 100644 --- a/arch/sh/include/cpu-sh2a/cpu/sh7264.h +++ b/arch/sh/include/cpu-sh2a/cpu/sh7264.h @@ -112,12 +112,6 @@ enum { GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A, GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA, - /* SSU */ - GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD, - GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF, - GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD, - GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF, - /* SCIF */ GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3, GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3, From patchwork Wed Dec 18 19:48:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11301825 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67CFD1892 for ; Wed, 18 Dec 2019 19:48:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4550224676 for ; Wed, 18 Dec 2019 19:48:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727472AbfLRTsS (ORCPT ); Wed, 18 Dec 2019 14:48:18 -0500 Received: from michel.telenet-ops.be ([195.130.137.88]:43462 "EHLO michel.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727531AbfLRTsS (ORCPT ); Wed, 18 Dec 2019 14:48:18 -0500 Received: from ramsan ([84.195.182.253]) by michel.telenet-ops.be with bizsmtp id fXoF2100C5USYZQ06XoFVq; Wed, 18 Dec 2019 20:48:16 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1ihfIt-0007y1-JB; Wed, 18 Dec 2019 20:48:15 +0100 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1ihfIt-0003Kb-I4; Wed, 18 Dec 2019 20:48:15 +0100 From: Geert Uytterhoeven To: Linus Walleij , Yoshinori Sato , Rich Felker Cc: linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 6/6] sh: sh7269: Remove bogus SSU GPIO function definitions Date: Wed, 18 Dec 2019 20:48:12 +0100 Message-Id: <20191218194812.12741-7-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191218194812.12741-1-geert+renesas@glider.be> References: <20191218194812.12741-1-geert+renesas@glider.be> Sender: linux-sh-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org SH7269 has no Synchronous Serial Communication Unit (SSU). Remove the bogus enum IDs, which caused holes in pinmux_func_gpios[]. Signed-off-by: Geert Uytterhoeven --- Presumably this has been copied from sh7203. The runtime-check under development reports: sh7269_pfc: empty function gpio 141 sh7269_pfc: empty function gpio 142 sh7269_pfc: empty function gpio 143 sh7269_pfc: empty function gpio 144 sh7269_pfc: empty function gpio 145 sh7269_pfc: empty function gpio 146 sh7269_pfc: empty function gpio 147 sh7269_pfc: empty function gpio 148 sh7269_pfc: empty function gpio 149 sh7269_pfc: empty function gpio 150 sh7269_pfc: empty function gpio 151 sh7269_pfc: empty function gpio 152 sh7269_pfc: empty function gpio 153 sh7269_pfc: empty function gpio 154 sh7269_pfc: empty function gpio 155 sh7269_pfc: empty function gpio 156 --- arch/sh/include/cpu-sh2a/cpu/sh7269.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7269.h b/arch/sh/include/cpu-sh2a/cpu/sh7269.h index b887cc402b712557..fece521c74b30d4d 100644 --- a/arch/sh/include/cpu-sh2a/cpu/sh7269.h +++ b/arch/sh/include/cpu-sh2a/cpu/sh7269.h @@ -126,12 +126,6 @@ enum { GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A, GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA, - /* SSU */ - GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD, - GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF, - GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD, - GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF, - /* SCIF */ GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0, GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1,