From patchwork Fri Dec 20 14:30:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305671 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D85D7109A for ; Fri, 20 Dec 2019 14:34:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B6CAA206CB for ; Fri, 20 Dec 2019 14:34:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727768AbfLTOaf (ORCPT ); Fri, 20 Dec 2019 09:30:35 -0500 Received: from foss.arm.com ([217.140.110.172]:51180 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727754AbfLTOaf (ORCPT ); Fri, 20 Dec 2019 09:30:35 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8CAC431B; Fri, 20 Dec 2019 06:30:34 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B39603F718; Fri, 20 Dec 2019 06:30:32 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 01/18] dt-bindings: ARM SPE: highlight the need for PPI partitions on heterogeneous systems Date: Fri, 20 Dec 2019 14:30:08 +0000 Message-Id: <20191220143025.33853-2-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla It's not entirely clear for the binding document that the only way to express ARM SPE affined to a subset of CPUs on a heterogeneous systems is through the use of PPI partitions available in the interrupt controller bindings. Let's make it clear. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- Documentation/devicetree/bindings/arm/spe-pmu.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt b/Documentation/devicetree/bindings/arm/spe-pmu.txt index 93372f2a7df9..4f4815800f6e 100644 --- a/Documentation/devicetree/bindings/arm/spe-pmu.txt +++ b/Documentation/devicetree/bindings/arm/spe-pmu.txt @@ -9,8 +9,9 @@ performance sample data using an in-memory trace buffer. "arm,statistical-profiling-extension-v1" - interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where - SPE is only supported on a subset of the CPUs, please consult - the arm,gic-v3 binding for details on describing a PPI partition. + SPE is only supported on a subset of the CPUs, a PPI partition + described in the arm,gic-v3 binding must be used to describe + the set of CPUs this interrupt is affine to. ** Example: From patchwork Fri Dec 20 14:30:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305669 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BCEEB109A for ; Fri, 20 Dec 2019 14:33:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B739206CB for ; Fri, 20 Dec 2019 14:33:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727972AbfLTOdl (ORCPT ); Fri, 20 Dec 2019 09:33:41 -0500 Received: from foss.arm.com ([217.140.110.172]:51188 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727783AbfLTOah (ORCPT ); Fri, 20 Dec 2019 09:30:37 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B569D106F; Fri, 20 Dec 2019 06:30:36 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DC14E3F718; Fri, 20 Dec 2019 06:30:34 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 02/18] arm64: KVM: reset E2PB correctly in MDCR_EL2 when exiting the guest(VHE) Date: Fri, 20 Dec 2019 14:30:09 +0000 Message-Id: <20191220143025.33853-3-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla On VHE systems, the reset value for MDCR_EL2.E2PB=b00 which defaults to profiling buffer using the EL2 stage 1 translations. However if the guest are allowed to use profiling buffers changing E2PB settings, we need to ensure we resume back MDCR_EL2.E2PB=b00. Currently we just do bitwise '&' with MDCR_EL2_E2PB_MASK which will retain the value. So fix it by clearing all the bits in E2PB. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- arch/arm64/kvm/hyp/switch.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 72fbbd86eb5e..250f13910882 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -228,9 +228,7 @@ void deactivate_traps_vhe_put(void) { u64 mdcr_el2 = read_sysreg(mdcr_el2); - mdcr_el2 &= MDCR_EL2_HPMN_MASK | - MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT | - MDCR_EL2_TPMS; + mdcr_el2 &= MDCR_EL2_HPMN_MASK | MDCR_EL2_TPMS; write_sysreg(mdcr_el2, mdcr_el2); From patchwork Fri Dec 20 14:30:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305659 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1CAE13B6 for ; Fri, 20 Dec 2019 14:33:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CAA20222C2 for ; Fri, 20 Dec 2019 14:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727831AbfLTOam (ORCPT ); Fri, 20 Dec 2019 09:30:42 -0500 Received: from foss.arm.com ([217.140.110.172]:51198 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727809AbfLTOaj (ORCPT ); Fri, 20 Dec 2019 09:30:39 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DF45611D4; Fri, 20 Dec 2019 06:30:38 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1120D3F718; Fri, 20 Dec 2019 06:30:36 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 03/18] arm64: KVM: define SPE data structure for each vcpu Date: Fri, 20 Dec 2019 14:30:10 +0000 Message-Id: <20191220143025.33853-4-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla In order to support virtual SPE for guest, so define some basic structs. This features depends on host having hardware with SPE support. Since we can support this only on ARM64, add a separate config symbol for the same. Signed-off-by: Sudeep Holla [ Add irq_level, rename irq to irq_num for kvm_spe ] Signed-off-by: Andrew Murray --- arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/kvm/Kconfig | 7 +++++++ include/kvm/arm_spe.h | 19 +++++++++++++++++++ 3 files changed, 28 insertions(+) create mode 100644 include/kvm/arm_spe.h diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index c61260cf63c5..f5dcff912645 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -35,6 +35,7 @@ #include #include #include +#include #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS @@ -302,6 +303,7 @@ struct kvm_vcpu_arch { struct vgic_cpu vgic_cpu; struct arch_timer_cpu timer_cpu; struct kvm_pmu pmu; + struct kvm_spe spe; /* * Anything that is not used directly from assembly code goes diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig index a475c68cbfec..af5be2c57dcb 100644 --- a/arch/arm64/kvm/Kconfig +++ b/arch/arm64/kvm/Kconfig @@ -35,6 +35,7 @@ config KVM select HAVE_KVM_EVENTFD select HAVE_KVM_IRQFD select KVM_ARM_PMU if HW_PERF_EVENTS + select KVM_ARM_SPE if (HW_PERF_EVENTS && ARM_SPE_PMU) select HAVE_KVM_MSI select HAVE_KVM_IRQCHIP select HAVE_KVM_IRQ_ROUTING @@ -61,6 +62,12 @@ config KVM_ARM_PMU Adds support for a virtual Performance Monitoring Unit (PMU) in virtual machines. +config KVM_ARM_SPE + bool + ---help--- + Adds support for a virtual Statistical Profiling Extension(SPE) in + virtual machines. + config KVM_INDIRECT_VECTORS def_bool KVM && (HARDEN_BRANCH_PREDICTOR || HARDEN_EL2_VECTORS) diff --git a/include/kvm/arm_spe.h b/include/kvm/arm_spe.h new file mode 100644 index 000000000000..48d118fdb174 --- /dev/null +++ b/include/kvm/arm_spe.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 ARM Ltd. + */ + +#ifndef __ASM_ARM_KVM_SPE_H +#define __ASM_ARM_KVM_SPE_H + +#include +#include + +struct kvm_spe { + int irq_num; + bool ready; /* indicates that SPE KVM instance is ready for use */ + bool created; /* SPE KVM instance is created, may not be ready yet */ + bool irq_level; +}; + +#endif /* __ASM_ARM_KVM_SPE_H */ From patchwork Fri Dec 20 14:30:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305661 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 582156C1 for ; Fri, 20 Dec 2019 14:33:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 40BD9222C2 for ; Fri, 20 Dec 2019 14:33:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727869AbfLTOdS (ORCPT ); Fri, 20 Dec 2019 09:33:18 -0500 Received: from foss.arm.com ([217.140.110.172]:51206 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727815AbfLTOal (ORCPT ); Fri, 20 Dec 2019 09:30:41 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1304311FB; Fri, 20 Dec 2019 06:30:41 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 39E3A3F718; Fri, 20 Dec 2019 06:30:39 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 04/18] arm64: KVM: add SPE system registers to sys_reg_descs Date: Fri, 20 Dec 2019 14:30:11 +0000 Message-Id: <20191220143025.33853-5-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla Add the Statistical Profiling Extension(SPE) Profiling Buffer controls registers such that we can provide initial register values and use the sys_regs structure as a store for our SPE context. Signed-off-by: Sudeep Holla [ Reword commit, remove access/reset handlers, defer kvm_arm_support_spe_v1 ] Signed-off-by: Andrew Murray --- arch/arm64/include/asm/kvm_host.h | 12 ++++++++++++ arch/arm64/kvm/sys_regs.c | 11 +++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index f5dcff912645..9eb85f14df90 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -145,6 +145,18 @@ enum vcpu_sysreg { MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ DISR_EL1, /* Deferred Interrupt Status Register */ + /* Statistical Profiling Extension Registers */ + PMSCR_EL1, + PMSICR_EL1, + PMSIRR_EL1, + PMSFCR_EL1, + PMSEVFR_EL1, + PMSLATFR_EL1, + PMSIDR_EL1, + PMBLIMITR_EL1, + PMBPTR_EL1, + PMBSR_EL1, + /* Performance Monitors Registers */ PMCR_EL0, /* Control Register */ PMSELR_EL0, /* Event Counter Selection Register */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 46822afc57e0..955b157f9cc5 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1506,6 +1506,17 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, + { SYS_DESC(SYS_PMSCR_EL1), NULL, reset_val, PMSCR_EL1, 0 }, + { SYS_DESC(SYS_PMSICR_EL1), NULL, reset_val, PMSICR_EL1, 0 }, + { SYS_DESC(SYS_PMSIRR_EL1), NULL, reset_val, PMSIRR_EL1, 0 }, + { SYS_DESC(SYS_PMSFCR_EL1), NULL, reset_val, PMSFCR_EL1, 0 }, + { SYS_DESC(SYS_PMSEVFR_EL1), NULL, reset_val, PMSEVFR_EL1, 0 }, + { SYS_DESC(SYS_PMSLATFR_EL1), NULL, reset_val, PMSLATFR_EL1, 0 }, + { SYS_DESC(SYS_PMSIDR_EL1), NULL, reset_val, PMSIDR_EL1, 0 }, + { SYS_DESC(SYS_PMBLIMITR_EL1), NULL, reset_val, PMBLIMITR_EL1, 0 }, + { SYS_DESC(SYS_PMBPTR_EL1), NULL, reset_val, PMBPTR_EL1, 0 }, + { SYS_DESC(SYS_PMBSR_EL1), NULL, reset_val, PMBSR_EL1, 0 }, + { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 }, From patchwork Fri Dec 20 14:30:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305609 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7FF0913B6 for ; Fri, 20 Dec 2019 14:30:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 68ABB24689 for ; Fri, 20 Dec 2019 14:30:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727859AbfLTOao (ORCPT ); Fri, 20 Dec 2019 09:30:44 -0500 Received: from foss.arm.com ([217.140.110.172]:51218 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727790AbfLTOan (ORCPT ); Fri, 20 Dec 2019 09:30:43 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C03411B3; Fri, 20 Dec 2019 06:30:43 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6302E3F718; Fri, 20 Dec 2019 06:30:41 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 05/18] arm64: KVM/VHE: enable the use PMSCR_EL12 on VHE systems Date: Fri, 20 Dec 2019 14:30:12 +0000 Message-Id: <20191220143025.33853-6-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla Currently, we are just using PMSCR_EL1 in the host for non VHE systems. We already have the {read,write}_sysreg_el*() accessors for accessing particular ELs' sysregs in the presence of VHE. Lets just define PMSCR_EL12 and start making use of it here which will access the right register on both VHE and non VHE systems. This change is required to add SPE guest support on VHE systems. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kvm/hyp/debug-sr.c | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 6e919fafb43d..6c0b0ad97688 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -468,6 +468,7 @@ #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) +#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0) #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index 0fc9872a1467..98be2f11c16c 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -108,8 +108,8 @@ static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) return; /* Yes; save the control register and disable data generation */ - *pmscr_el1 = read_sysreg_s(SYS_PMSCR_EL1); - write_sysreg_s(0, SYS_PMSCR_EL1); + *pmscr_el1 = read_sysreg_el1(SYS_PMSCR); + write_sysreg_el1(0, SYS_PMSCR); isb(); /* Now drain all buffered data to memory */ @@ -126,7 +126,7 @@ static void __hyp_text __debug_restore_spe_nvhe(u64 pmscr_el1) isb(); /* Re-enable data generation */ - write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1); + write_sysreg_el1(pmscr_el1, SYS_PMSCR); } static void __hyp_text __debug_save_state(struct kvm_vcpu *vcpu, From patchwork Fri Dec 20 14:30:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305613 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 79F69109A for ; Fri, 20 Dec 2019 14:30:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 58CF324693 for ; Fri, 20 Dec 2019 14:30:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727880AbfLTOas (ORCPT ); Fri, 20 Dec 2019 09:30:48 -0500 Received: from foss.arm.com ([217.140.110.172]:51232 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727864AbfLTOaq (ORCPT ); Fri, 20 Dec 2019 09:30:46 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8CFB930E; Fri, 20 Dec 2019 06:30:45 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8C12B3F718; Fri, 20 Dec 2019 06:30:43 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 06/18] arm64: KVM: split debug save restore across vm/traps activation Date: Fri, 20 Dec 2019 14:30:13 +0000 Message-Id: <20191220143025.33853-7-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla If we enable profiling buffer controls at EL1 generate a trap exception to EL2, it also changes profiling buffer to use EL1&0 stage 1 translation regime in case of VHE. To support SPE both in the guest and host, we need to first stop profiling and flush the profiling buffers before we activate/switch vm or enable/disable the traps. In prepartion to do that, lets split the debug save restore functionality into 4 steps: 1. debug_save_host_context - saves the host context 2. debug_restore_guest_context - restore the guest context 3. debug_save_guest_context - saves the guest context 4. debug_restore_host_context - restores the host context Lets rename existing __debug_switch_to_{host,guest} to make sure it's aligned to the above and just add the place holders for new ones getting added here as we need them to support SPE in guests. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- arch/arm64/include/asm/kvm_hyp.h | 6 ++++-- arch/arm64/kvm/hyp/debug-sr.c | 25 ++++++++++++++++--------- arch/arm64/kvm/hyp/switch.c | 12 ++++++++---- 3 files changed, 28 insertions(+), 15 deletions(-) diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h index 97f21cc66657..011e7963f772 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -69,8 +69,10 @@ void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt); void __sysreg32_save_state(struct kvm_vcpu *vcpu); void __sysreg32_restore_state(struct kvm_vcpu *vcpu); -void __debug_switch_to_guest(struct kvm_vcpu *vcpu); -void __debug_switch_to_host(struct kvm_vcpu *vcpu); +void __debug_save_host_context(struct kvm_vcpu *vcpu); +void __debug_restore_guest_context(struct kvm_vcpu *vcpu); +void __debug_save_guest_context(struct kvm_vcpu *vcpu); +void __debug_restore_host_context(struct kvm_vcpu *vcpu); void __fpsimd_save_state(struct user_fpsimd_state *fp_regs); void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs); diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index 98be2f11c16c..c803daebd596 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -168,20 +168,13 @@ static void __hyp_text __debug_restore_state(struct kvm_vcpu *vcpu, write_sysreg(ctxt->sys_regs[MDCCINT_EL1], mdccint_el1); } -void __hyp_text __debug_switch_to_guest(struct kvm_vcpu *vcpu) +void __hyp_text __debug_restore_guest_context(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *host_ctxt; struct kvm_cpu_context *guest_ctxt; struct kvm_guest_debug_arch *host_dbg; struct kvm_guest_debug_arch *guest_dbg; - /* - * Non-VHE: Disable and flush SPE data generation - * VHE: The vcpu can run, but it can't hide. - */ - if (!has_vhe()) - __debug_save_spe_nvhe(&vcpu->arch.host_debug_state.pmscr_el1); - if (!(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) return; @@ -194,7 +187,7 @@ void __hyp_text __debug_switch_to_guest(struct kvm_vcpu *vcpu) __debug_restore_state(vcpu, guest_dbg, guest_ctxt); } -void __hyp_text __debug_switch_to_host(struct kvm_vcpu *vcpu) +void __hyp_text __debug_restore_host_context(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *host_ctxt; struct kvm_cpu_context *guest_ctxt; @@ -218,6 +211,20 @@ void __hyp_text __debug_switch_to_host(struct kvm_vcpu *vcpu) vcpu->arch.flags &= ~KVM_ARM64_DEBUG_DIRTY; } +void __hyp_text __debug_save_host_context(struct kvm_vcpu *vcpu) +{ + /* + * Non-VHE: Disable and flush SPE data generation + * VHE: The vcpu can run, but it can't hide. + */ + if (!has_vhe()) + __debug_save_spe_nvhe(&vcpu->arch.host_debug_state.pmscr_el1); +} + +void __hyp_text __debug_save_guest_context(struct kvm_vcpu *vcpu) +{ +} + u32 __hyp_text __kvm_get_mdcr_el2(void) { return read_sysreg(mdcr_el2); diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 250f13910882..67b7c160f65b 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -626,6 +626,7 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) guest_ctxt = &vcpu->arch.ctxt; sysreg_save_host_state_vhe(host_ctxt); + __debug_save_host_context(vcpu); /* * ARM erratum 1165522 requires us to configure both stage 1 and @@ -642,7 +643,7 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) __activate_traps(vcpu); sysreg_restore_guest_state_vhe(guest_ctxt); - __debug_switch_to_guest(vcpu); + __debug_restore_guest_context(vcpu); __set_guest_arch_workaround_state(vcpu); @@ -656,6 +657,7 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) __set_host_arch_workaround_state(vcpu); sysreg_save_guest_state_vhe(guest_ctxt); + __debug_save_guest_context(vcpu); __deactivate_traps(vcpu); @@ -664,7 +666,7 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) __fpsimd_save_fpexc32(vcpu); - __debug_switch_to_host(vcpu); + __debug_restore_host_context(vcpu); return exit_code; } @@ -698,6 +700,7 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) pmu_switch_needed = __pmu_switch_to_guest(host_ctxt); __sysreg_save_state_nvhe(host_ctxt); + __debug_save_host_context(vcpu); /* * We must restore the 32-bit state before the sysregs, thanks @@ -716,7 +719,7 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) __hyp_vgic_restore_state(vcpu); __timer_enable_traps(vcpu); - __debug_switch_to_guest(vcpu); + __debug_restore_guest_context(vcpu); __set_guest_arch_workaround_state(vcpu); @@ -730,6 +733,7 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) __set_host_arch_workaround_state(vcpu); __sysreg_save_state_nvhe(guest_ctxt); + __debug_save_guest_context(vcpu); __sysreg32_save_state(vcpu); __timer_disable_traps(vcpu); __hyp_vgic_save_state(vcpu); @@ -746,7 +750,7 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) * This must come after restoring the host sysregs, since a non-VHE * system may enable SPE here and make use of the TTBRs. */ - __debug_switch_to_host(vcpu); + __debug_restore_host_context(vcpu); if (pmu_switch_needed) __pmu_switch_to_host(host_ctxt); From patchwork Fri Dec 20 14:30:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305655 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C5CF66C1 for ; Fri, 20 Dec 2019 14:33:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ADAB321D7E for ; Fri, 20 Dec 2019 14:33:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728086AbfLTOc6 (ORCPT ); Fri, 20 Dec 2019 09:32:58 -0500 Received: from foss.arm.com ([217.140.110.172]:51246 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727875AbfLTOas (ORCPT ); Fri, 20 Dec 2019 09:30:48 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B549531B; Fri, 20 Dec 2019 06:30:47 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DCF893F718; Fri, 20 Dec 2019 06:30:45 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 07/18] arm64: KVM/debug: drop pmscr_el1 and use sys_regs[PMSCR_EL1] in kvm_cpu_context Date: Fri, 20 Dec 2019 14:30:14 +0000 Message-Id: <20191220143025.33853-8-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla kvm_cpu_context now has support to stash the complete SPE buffer control context. We no longer need the pmscr_el1 kvm_vcpu_arch and it can be dropped. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- arch/arm64/include/asm/kvm_host.h | 2 -- arch/arm64/kvm/hyp/debug-sr.c | 26 +++++++++++++++----------- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 9eb85f14df90..333c6491bec7 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -307,8 +307,6 @@ struct kvm_vcpu_arch { struct { /* {Break,watch}point registers */ struct kvm_guest_debug_arch regs; - /* Statistical profiling extension */ - u64 pmscr_el1; } host_debug_state; /* VGIC state */ diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index c803daebd596..8a70a493345e 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -85,19 +85,19 @@ default: write_debug(ptr[0], reg, 0); \ } -static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) +static void __hyp_text __debug_save_spe_nvhe(struct kvm_cpu_context *ctxt) { u64 reg; /* Clear pmscr in case of early return */ - *pmscr_el1 = 0; + ctxt->sys_regs[PMSCR_EL1] = 0; /* SPE present on this CPU? */ if (!cpuid_feature_extract_unsigned_field(read_sysreg(id_aa64dfr0_el1), ID_AA64DFR0_PMSVER_SHIFT)) return; - /* Yes; is it owned by EL3? */ + /* Yes; is it owned by higher EL? */ reg = read_sysreg_s(SYS_PMBIDR_EL1); if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) return; @@ -108,7 +108,7 @@ static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) return; /* Yes; save the control register and disable data generation */ - *pmscr_el1 = read_sysreg_el1(SYS_PMSCR); + ctxt->sys_regs[PMSCR_EL1] = read_sysreg_el1(SYS_PMSCR); write_sysreg_el1(0, SYS_PMSCR); isb(); @@ -117,16 +117,16 @@ static void __hyp_text __debug_save_spe_nvhe(u64 *pmscr_el1) dsb(nsh); } -static void __hyp_text __debug_restore_spe_nvhe(u64 pmscr_el1) +static void __hyp_text __debug_restore_spe_nvhe(struct kvm_cpu_context *ctxt) { - if (!pmscr_el1) + if (!ctxt->sys_regs[PMSCR_EL1]) return; /* The host page table is installed, but not yet synchronised */ isb(); /* Re-enable data generation */ - write_sysreg_el1(pmscr_el1, SYS_PMSCR); + write_sysreg_el1(ctxt->sys_regs[PMSCR_EL1], SYS_PMSCR); } static void __hyp_text __debug_save_state(struct kvm_vcpu *vcpu, @@ -194,14 +194,15 @@ void __hyp_text __debug_restore_host_context(struct kvm_vcpu *vcpu) struct kvm_guest_debug_arch *host_dbg; struct kvm_guest_debug_arch *guest_dbg; + host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); + guest_ctxt = &vcpu->arch.ctxt; + if (!has_vhe()) - __debug_restore_spe_nvhe(vcpu->arch.host_debug_state.pmscr_el1); + __debug_restore_spe_nvhe(host_ctxt); if (!(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) return; - host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); - guest_ctxt = &vcpu->arch.ctxt; host_dbg = &vcpu->arch.host_debug_state.regs; guest_dbg = kern_hyp_va(vcpu->arch.debug_ptr); @@ -217,8 +218,11 @@ void __hyp_text __debug_save_host_context(struct kvm_vcpu *vcpu) * Non-VHE: Disable and flush SPE data generation * VHE: The vcpu can run, but it can't hide. */ + struct kvm_cpu_context *host_ctxt; + + host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); if (!has_vhe()) - __debug_save_spe_nvhe(&vcpu->arch.host_debug_state.pmscr_el1); + __debug_save_spe_nvhe(host_ctxt); } void __hyp_text __debug_save_guest_context(struct kvm_vcpu *vcpu) From patchwork Fri Dec 20 14:30:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305651 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3546D109A for ; Fri, 20 Dec 2019 14:32:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1D4F22465E for ; Fri, 20 Dec 2019 14:32:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727925AbfLTOav (ORCPT ); Fri, 20 Dec 2019 09:30:51 -0500 Received: from foss.arm.com ([217.140.110.172]:51258 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727806AbfLTOau (ORCPT ); Fri, 20 Dec 2019 09:30:50 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DDD54106F; Fri, 20 Dec 2019 06:30:49 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 113893F718; Fri, 20 Dec 2019 06:30:47 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 08/18] arm64: KVM: add support to save/restore SPE profiling buffer controls Date: Fri, 20 Dec 2019 14:30:15 +0000 Message-Id: <20191220143025.33853-9-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla Currently since we don't support profiling using SPE in the guests, we just save the PMSCR_EL1, flush the profiling buffers and disable sampling. However in order to support simultaneous sampling both in the host and guests, we need to save and reatore the complete SPE profiling buffer controls' context. Let's add the support for the same and keep it disabled for now. We can enable it conditionally only if guests are allowed to use SPE. Signed-off-by: Sudeep Holla [ Clear PMBSR bit when saving state to prevent spurious interrupts ] Signed-off-by: Andrew Murray --- arch/arm64/kvm/hyp/debug-sr.c | 51 +++++++++++++++++++++++++++++------ 1 file changed, 43 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index 8a70a493345e..12429b212a3a 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -85,7 +85,8 @@ default: write_debug(ptr[0], reg, 0); \ } -static void __hyp_text __debug_save_spe_nvhe(struct kvm_cpu_context *ctxt) +static void __hyp_text +__debug_save_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) { u64 reg; @@ -102,22 +103,46 @@ static void __hyp_text __debug_save_spe_nvhe(struct kvm_cpu_context *ctxt) if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) return; - /* No; is the host actually using the thing? */ - reg = read_sysreg_s(SYS_PMBLIMITR_EL1); - if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT))) + /* Save the control register and disable data generation */ + ctxt->sys_regs[PMSCR_EL1] = read_sysreg_el1(SYS_PMSCR); + + if (!ctxt->sys_regs[PMSCR_EL1]) return; /* Yes; save the control register and disable data generation */ - ctxt->sys_regs[PMSCR_EL1] = read_sysreg_el1(SYS_PMSCR); write_sysreg_el1(0, SYS_PMSCR); isb(); /* Now drain all buffered data to memory */ psb_csync(); dsb(nsh); + + if (!full_ctxt) + return; + + ctxt->sys_regs[PMBLIMITR_EL1] = read_sysreg_s(SYS_PMBLIMITR_EL1); + write_sysreg_s(0, SYS_PMBLIMITR_EL1); + + /* + * As PMBSR is conditionally restored when returning to the host we + * must ensure the service bit is unset here to prevent a spurious + * host SPE interrupt from being raised. + */ + ctxt->sys_regs[PMBSR_EL1] = read_sysreg_s(SYS_PMBSR_EL1); + write_sysreg_s(0, SYS_PMBSR_EL1); + + isb(); + + ctxt->sys_regs[PMSICR_EL1] = read_sysreg_s(SYS_PMSICR_EL1); + ctxt->sys_regs[PMSIRR_EL1] = read_sysreg_s(SYS_PMSIRR_EL1); + ctxt->sys_regs[PMSFCR_EL1] = read_sysreg_s(SYS_PMSFCR_EL1); + ctxt->sys_regs[PMSEVFR_EL1] = read_sysreg_s(SYS_PMSEVFR_EL1); + ctxt->sys_regs[PMSLATFR_EL1] = read_sysreg_s(SYS_PMSLATFR_EL1); + ctxt->sys_regs[PMBPTR_EL1] = read_sysreg_s(SYS_PMBPTR_EL1); } -static void __hyp_text __debug_restore_spe_nvhe(struct kvm_cpu_context *ctxt) +static void __hyp_text +__debug_restore_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) { if (!ctxt->sys_regs[PMSCR_EL1]) return; @@ -126,6 +151,16 @@ static void __hyp_text __debug_restore_spe_nvhe(struct kvm_cpu_context *ctxt) isb(); /* Re-enable data generation */ + if (full_ctxt) { + write_sysreg_s(ctxt->sys_regs[PMBPTR_EL1], SYS_PMBPTR_EL1); + write_sysreg_s(ctxt->sys_regs[PMBLIMITR_EL1], SYS_PMBLIMITR_EL1); + write_sysreg_s(ctxt->sys_regs[PMSFCR_EL1], SYS_PMSFCR_EL1); + write_sysreg_s(ctxt->sys_regs[PMSEVFR_EL1], SYS_PMSEVFR_EL1); + write_sysreg_s(ctxt->sys_regs[PMSLATFR_EL1], SYS_PMSLATFR_EL1); + write_sysreg_s(ctxt->sys_regs[PMSIRR_EL1], SYS_PMSIRR_EL1); + write_sysreg_s(ctxt->sys_regs[PMSICR_EL1], SYS_PMSICR_EL1); + write_sysreg_s(ctxt->sys_regs[PMBSR_EL1], SYS_PMBSR_EL1); + } write_sysreg_el1(ctxt->sys_regs[PMSCR_EL1], SYS_PMSCR); } @@ -198,7 +233,7 @@ void __hyp_text __debug_restore_host_context(struct kvm_vcpu *vcpu) guest_ctxt = &vcpu->arch.ctxt; if (!has_vhe()) - __debug_restore_spe_nvhe(host_ctxt); + __debug_restore_spe_nvhe(host_ctxt, false); if (!(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) return; @@ -222,7 +257,7 @@ void __hyp_text __debug_save_host_context(struct kvm_vcpu *vcpu) host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); if (!has_vhe()) - __debug_save_spe_nvhe(host_ctxt); + __debug_save_spe_nvhe(host_ctxt, false); } void __hyp_text __debug_save_guest_context(struct kvm_vcpu *vcpu) From patchwork Fri Dec 20 14:30:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305649 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE56B6C1 for ; Fri, 20 Dec 2019 14:32:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B78FF24682 for ; Fri, 20 Dec 2019 14:32:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727918AbfLTOck (ORCPT ); Fri, 20 Dec 2019 09:32:40 -0500 Received: from foss.arm.com ([217.140.110.172]:51268 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727926AbfLTOaw (ORCPT ); Fri, 20 Dec 2019 09:30:52 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11DCF30E; Fri, 20 Dec 2019 06:30:52 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 39ABD3F718; Fri, 20 Dec 2019 06:30:50 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 09/18] arm64: KVM: enable conditional save/restore full SPE profiling buffer controls Date: Fri, 20 Dec 2019 14:30:16 +0000 Message-Id: <20191220143025.33853-10-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla Now that we can save/restore the full SPE controls, we can enable it if SPE is setup and ready to use in KVM. It's supported in KVM only if all the CPUs in the system supports SPE. However to support heterogenous systems, we need to move the check if host supports SPE and do a partial save/restore. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- arch/arm64/kvm/hyp/debug-sr.c | 33 ++++++++++++++++----------------- include/kvm/arm_spe.h | 6 ++++++ 2 files changed, 22 insertions(+), 17 deletions(-) diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c index 12429b212a3a..d8d857067e6d 100644 --- a/arch/arm64/kvm/hyp/debug-sr.c +++ b/arch/arm64/kvm/hyp/debug-sr.c @@ -86,18 +86,13 @@ } static void __hyp_text -__debug_save_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) +__debug_save_spe_context(struct kvm_cpu_context *ctxt, bool full_ctxt) { u64 reg; /* Clear pmscr in case of early return */ ctxt->sys_regs[PMSCR_EL1] = 0; - /* SPE present on this CPU? */ - if (!cpuid_feature_extract_unsigned_field(read_sysreg(id_aa64dfr0_el1), - ID_AA64DFR0_PMSVER_SHIFT)) - return; - /* Yes; is it owned by higher EL? */ reg = read_sysreg_s(SYS_PMBIDR_EL1); if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) @@ -142,7 +137,7 @@ __debug_save_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) } static void __hyp_text -__debug_restore_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) +__debug_restore_spe_context(struct kvm_cpu_context *ctxt, bool full_ctxt) { if (!ctxt->sys_regs[PMSCR_EL1]) return; @@ -210,11 +205,14 @@ void __hyp_text __debug_restore_guest_context(struct kvm_vcpu *vcpu) struct kvm_guest_debug_arch *host_dbg; struct kvm_guest_debug_arch *guest_dbg; + host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); + guest_ctxt = &vcpu->arch.ctxt; + + __debug_restore_spe_context(guest_ctxt, kvm_arm_spe_v1_ready(vcpu)); + if (!(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) return; - host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); - guest_ctxt = &vcpu->arch.ctxt; host_dbg = &vcpu->arch.host_debug_state.regs; guest_dbg = kern_hyp_va(vcpu->arch.debug_ptr); @@ -232,8 +230,7 @@ void __hyp_text __debug_restore_host_context(struct kvm_vcpu *vcpu) host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); guest_ctxt = &vcpu->arch.ctxt; - if (!has_vhe()) - __debug_restore_spe_nvhe(host_ctxt, false); + __debug_restore_spe_context(host_ctxt, kvm_arm_spe_v1_ready(vcpu)); if (!(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY)) return; @@ -249,19 +246,21 @@ void __hyp_text __debug_restore_host_context(struct kvm_vcpu *vcpu) void __hyp_text __debug_save_host_context(struct kvm_vcpu *vcpu) { - /* - * Non-VHE: Disable and flush SPE data generation - * VHE: The vcpu can run, but it can't hide. - */ struct kvm_cpu_context *host_ctxt; host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context); - if (!has_vhe()) - __debug_save_spe_nvhe(host_ctxt, false); + if (cpuid_feature_extract_unsigned_field(read_sysreg(id_aa64dfr0_el1), + ID_AA64DFR0_PMSVER_SHIFT)) + __debug_save_spe_context(host_ctxt, kvm_arm_spe_v1_ready(vcpu)); } void __hyp_text __debug_save_guest_context(struct kvm_vcpu *vcpu) { + bool kvm_spe_ready = kvm_arm_spe_v1_ready(vcpu); + + /* SPE present on this vCPU? */ + if (kvm_spe_ready) + __debug_save_spe_context(&vcpu->arch.ctxt, kvm_spe_ready); } u32 __hyp_text __kvm_get_mdcr_el2(void) diff --git a/include/kvm/arm_spe.h b/include/kvm/arm_spe.h index 48d118fdb174..30c40b1bc385 100644 --- a/include/kvm/arm_spe.h +++ b/include/kvm/arm_spe.h @@ -16,4 +16,10 @@ struct kvm_spe { bool irq_level; }; +#ifdef CONFIG_KVM_ARM_SPE +#define kvm_arm_spe_v1_ready(v) ((v)->arch.spe.ready) +#else +#define kvm_arm_spe_v1_ready(v) (false) +#endif /* CONFIG_KVM_ARM_SPE */ + #endif /* __ASM_ARM_KVM_SPE_H */ From patchwork Fri Dec 20 14:30:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305647 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 124366C1 for ; Fri, 20 Dec 2019 14:32:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E4FC82465E for ; Fri, 20 Dec 2019 14:32:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727881AbfLTOc3 (ORCPT ); Fri, 20 Dec 2019 09:32:29 -0500 Received: from foss.arm.com ([217.140.110.172]:51282 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727946AbfLTOay (ORCPT ); Fri, 20 Dec 2019 09:30:54 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3A33711D4; Fri, 20 Dec 2019 06:30:54 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 61B7D3F718; Fri, 20 Dec 2019 06:30:52 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 10/18] arm64: KVM/debug: use EL1&0 stage 1 translation regime Date: Fri, 20 Dec 2019 14:30:17 +0000 Message-Id: <20191220143025.33853-11-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla Now that we have all the save/restore mechanism in place, lets enable the translation regime used by buffer from EL2 stage 1 to EL1 stage 1 on VHE systems. Signed-off-by: Sudeep Holla [ Reword commit, don't trap to EL2 ] Signed-off-by: Andrew Murray --- arch/arm64/kvm/hyp/switch.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 67b7c160f65b..6c153b79829b 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -100,6 +100,7 @@ static void activate_traps_vhe(struct kvm_vcpu *vcpu) write_sysreg(val, cpacr_el1); + write_sysreg(vcpu->arch.mdcr_el2 | 3 << MDCR_EL2_E2PB_SHIFT, mdcr_el2); write_sysreg(kvm_get_hyp_vector(), vbar_el1); } NOKPROBE_SYMBOL(activate_traps_vhe); @@ -117,6 +118,7 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu) __activate_traps_fpsimd32(vcpu); } + write_sysreg(vcpu->arch.mdcr_el2 | 3 << MDCR_EL2_E2PB_SHIFT, mdcr_el2); write_sysreg(val, cptr_el2); if (cpus_have_const_cap(ARM64_WORKAROUND_1319367)) { From patchwork Fri Dec 20 14:30:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305643 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09614109A for ; Fri, 20 Dec 2019 14:32:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DC8E8222C2 for ; Fri, 20 Dec 2019 14:32:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727789AbfLTOcQ (ORCPT ); Fri, 20 Dec 2019 09:32:16 -0500 Received: from foss.arm.com ([217.140.110.172]:51296 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727959AbfLTOa4 (ORCPT ); Fri, 20 Dec 2019 09:30:56 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6220030E; Fri, 20 Dec 2019 06:30:56 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 89B8B3F718; Fri, 20 Dec 2019 06:30:54 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 11/18] KVM: arm64: don't trap Statistical Profiling controls to EL2 Date: Fri, 20 Dec 2019 14:30:18 +0000 Message-Id: <20191220143025.33853-12-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org As we now save/restore the profiler state there is no need to trap accesses to the statistical profiling controls. Let's unset the _TPMS bit. Signed-off-by: Andrew Murray --- arch/arm64/kvm/debug.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index 43487f035385..07ca783e7d9e 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -88,7 +88,6 @@ void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) * - Performance monitors (MDCR_EL2_TPM/MDCR_EL2_TPMCR) * - Debug ROM Address (MDCR_EL2_TDRA) * - OS related registers (MDCR_EL2_TDOSA) - * - Statistical profiler (MDCR_EL2_TPMS/MDCR_EL2_E2PB) * * Additionally, KVM only traps guest accesses to the debug registers if * the guest is not actively using them (see the KVM_ARM64_DEBUG_DIRTY @@ -111,7 +110,6 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) */ vcpu->arch.mdcr_el2 = __this_cpu_read(mdcr_el2) & MDCR_EL2_HPMN_MASK; vcpu->arch.mdcr_el2 |= (MDCR_EL2_TPM | - MDCR_EL2_TPMS | MDCR_EL2_TPMCR | MDCR_EL2_TDRA | MDCR_EL2_TDOSA); From patchwork Fri Dec 20 14:30:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305615 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 34CFA6C1 for ; Fri, 20 Dec 2019 14:31:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1334224689 for ; Fri, 20 Dec 2019 14:31:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727981AbfLTObA (ORCPT ); Fri, 20 Dec 2019 09:31:00 -0500 Received: from foss.arm.com ([217.140.110.172]:51302 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727849AbfLTOa7 (ORCPT ); Fri, 20 Dec 2019 09:30:59 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B3B7711FB; Fri, 20 Dec 2019 06:30:58 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B2CE23F718; Fri, 20 Dec 2019 06:30:56 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 12/18] KVM: arm64: add a new vcpu device control group for SPEv1 Date: Fri, 20 Dec 2019 14:30:19 +0000 Message-Id: <20191220143025.33853-13-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla To configure the virtual SPEv1 overflow interrupt number, we use the vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_SPE_V1_IRQ attribute within the KVM_ARM_VCPU_SPE_V1_CTRL group. After configuring the SPEv1, call the vcpu ioctl with attribute KVM_ARM_VCPU_SPE_V1_INIT to initialize the SPEv1. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- Documentation/virt/kvm/devices/vcpu.txt | 28 ++++ arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/include/uapi/asm/kvm.h | 4 + arch/arm64/kvm/Makefile | 1 + arch/arm64/kvm/guest.c | 6 + arch/arm64/kvm/reset.c | 3 + include/kvm/arm_spe.h | 45 +++++++ include/uapi/linux/kvm.h | 1 + virt/kvm/arm/arm.c | 1 + virt/kvm/arm/spe.c | 163 ++++++++++++++++++++++++ 10 files changed, 253 insertions(+), 1 deletion(-) create mode 100644 virt/kvm/arm/spe.c diff --git a/Documentation/virt/kvm/devices/vcpu.txt b/Documentation/virt/kvm/devices/vcpu.txt index 6f3bd64a05b0..cefad056d677 100644 --- a/Documentation/virt/kvm/devices/vcpu.txt +++ b/Documentation/virt/kvm/devices/vcpu.txt @@ -74,3 +74,31 @@ Specifies the base address of the stolen time structure for this VCPU. The base address must be 64 byte aligned and exist within a valid guest memory region. See Documentation/virt/kvm/arm/pvtime.txt for more information including the layout of the stolen time structure. + +4. GROUP: KVM_ARM_VCPU_SPE_V1_CTRL +Architectures: ARM64 + +4.1. ATTRIBUTE: KVM_ARM_VCPU_SPE_V1_IRQ +Parameters: in kvm_device_attr.addr the address for SPE buffer overflow interrupt + is a pointer to an int +Returns: -EBUSY: The SPE overflow interrupt is already set + -ENXIO: The overflow interrupt not set when attempting to get it + -ENODEV: SPEv1 not supported + -EINVAL: Invalid SPE overflow interrupt number supplied or + trying to set the IRQ number without using an in-kernel + irqchip. + +A value describing the SPEv1 (Statistical Profiling Extension v1) overflow +interrupt number for this vcpu. This interrupt should be PPI and the interrupt +type and number must be same for each vcpu. + +4.2 ATTRIBUTE: KVM_ARM_VCPU_SPE_V1_INIT +Parameters: no additional parameter in kvm_device_attr.addr +Returns: -ENODEV: SPEv1 not supported or GIC not initialized + -ENXIO: SPEv1 not properly configured or in-kernel irqchip not + configured as required prior to calling this attribute + -EBUSY: SPEv1 already initialized + +Request the initialization of the SPEv1. If using the SPEv1 with an in-kernel +virtual GIC implementation, this must be done after initializing the in-kernel +irqchip. diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 333c6491bec7..d00f450dc4cd 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -39,7 +39,7 @@ #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS -#define KVM_VCPU_MAX_FEATURES 7 +#define KVM_VCPU_MAX_FEATURES 8 #define KVM_REQ_SLEEP \ KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 820e5751ada7..905a73f30079 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -106,6 +106,7 @@ struct kvm_regs { #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ +#define KVM_ARM_VCPU_SPE_V1 7 /* Support guest SPEv1 */ struct kvm_vcpu_init { __u32 target; @@ -326,6 +327,9 @@ struct kvm_vcpu_events { #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 #define KVM_ARM_VCPU_PVTIME_CTRL 2 #define KVM_ARM_VCPU_PVTIME_IPA 0 +#define KVM_ARM_VCPU_SPE_V1_CTRL 3 +#define KVM_ARM_VCPU_SPE_V1_IRQ 0 +#define KVM_ARM_VCPU_SPE_V1_INIT 1 /* KVM_IRQ_LINE irq field index values */ #define KVM_ARM_IRQ_VCPU2_SHIFT 28 diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 5ffbdc39e780..526f3bf09321 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -37,3 +37,4 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic/vgic-debug.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/irqchip.o kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o +kvm-$(CONFIG_KVM_ARM_SPE) += $(KVM)/arm/spe.o diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 2fff06114a8f..50fea538b8bd 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -874,6 +874,8 @@ int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, break; case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_set_attr(vcpu, attr); + case KVM_ARM_VCPU_SPE_V1_CTRL: + ret = kvm_arm_spe_v1_set_attr(vcpu, attr); break; default: ret = -ENXIO; @@ -897,6 +899,8 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, break; case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_get_attr(vcpu, attr); + case KVM_ARM_VCPU_SPE_V1_CTRL: + ret = kvm_arm_spe_v1_get_attr(vcpu, attr); break; default: ret = -ENXIO; @@ -920,6 +924,8 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, break; case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_has_attr(vcpu, attr); + case KVM_ARM_VCPU_SPE_V1_CTRL: + ret = kvm_arm_spe_v1_has_attr(vcpu, attr); break; default: ret = -ENXIO; diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index f4a8ae918827..cf17aff1489d 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -80,6 +80,9 @@ int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_ARM_INJECT_SERROR_ESR: r = cpus_have_const_cap(ARM64_HAS_RAS_EXTN); break; + case KVM_CAP_ARM_SPE_V1: + r = kvm_arm_support_spe_v1(); + break; case KVM_CAP_SET_GUEST_DEBUG: case KVM_CAP_VCPU_ATTRIBUTES: r = 1; diff --git a/include/kvm/arm_spe.h b/include/kvm/arm_spe.h index 30c40b1bc385..d1f3c564dfd0 100644 --- a/include/kvm/arm_spe.h +++ b/include/kvm/arm_spe.h @@ -8,6 +8,7 @@ #include #include +#include struct kvm_spe { int irq_num; @@ -18,8 +19,52 @@ struct kvm_spe { #ifdef CONFIG_KVM_ARM_SPE #define kvm_arm_spe_v1_ready(v) ((v)->arch.spe.ready) +#define kvm_arm_spe_irq_initialized(v) \ + ((v)->arch.spe.irq_num >= VGIC_NR_SGIS && \ + (v)->arch.spe.irq_num <= VGIC_MAX_PRIVATE) + +static inline bool kvm_arm_support_spe_v1(void) +{ + u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + + return !!cpuid_feature_extract_unsigned_field(dfr0, + ID_AA64DFR0_PMSVER_SHIFT); +} + +int kvm_arm_spe_v1_set_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); +int kvm_arm_spe_v1_get_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); +int kvm_arm_spe_v1_has_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); +int kvm_arm_spe_v1_enable(struct kvm_vcpu *vcpu); #else #define kvm_arm_spe_v1_ready(v) (false) +#define kvm_arm_support_spe_v1() (false) +#define kvm_arm_spe_irq_initialized(v) (false) + +static inline int kvm_arm_spe_v1_set_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + return -ENXIO; +} + +static inline int kvm_arm_spe_v1_get_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + return -ENXIO; +} + +static inline int kvm_arm_spe_v1_has_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + return -ENXIO; +} + +static inline int kvm_arm_spe_v1_enable(struct kvm_vcpu *vcpu) +{ + return 0; +} #endif /* CONFIG_KVM_ARM_SPE */ #endif /* __ASM_ARM_KVM_SPE_H */ diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index f0a16b4adbbd..1a362c230e4a 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1009,6 +1009,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PPC_GUEST_DEBUG_SSTEP 176 #define KVM_CAP_ARM_NISV_TO_USER 177 #define KVM_CAP_ARM_INJECT_EXT_DABT 178 +#define KVM_CAP_ARM_SPE_V1 179 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 12e0280291ce..340d2388ee2c 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -22,6 +22,7 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include "trace.h" diff --git a/virt/kvm/arm/spe.c b/virt/kvm/arm/spe.c new file mode 100644 index 000000000000..83ac2cce2cc3 --- /dev/null +++ b/virt/kvm/arm/spe.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 ARM Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +int kvm_arm_spe_v1_enable(struct kvm_vcpu *vcpu) +{ + if (!vcpu->arch.spe.created) + return 0; + + /* + * A valid interrupt configuration for the SPE is either to have a + * properly configured interrupt number and using an in-kernel irqchip. + */ + if (irqchip_in_kernel(vcpu->kvm)) { + int irq = vcpu->arch.spe.irq_num; + + if (!kvm_arm_spe_irq_initialized(vcpu)) + return -EINVAL; + + if (!irq_is_ppi(irq)) + return -EINVAL; + } + + vcpu->arch.spe.ready = true; + + return 0; +} + +static int kvm_arm_spe_v1_init(struct kvm_vcpu *vcpu) +{ + if (!kvm_arm_support_spe_v1()) + return -ENODEV; + + if (!test_bit(KVM_ARM_VCPU_SPE_V1, vcpu->arch.features)) + return -ENXIO; + + if (vcpu->arch.spe.created) + return -EBUSY; + + if (irqchip_in_kernel(vcpu->kvm)) { + int ret; + + /* + * If using the SPE with an in-kernel virtual GIC + * implementation, we require the GIC to be already + * initialized when initializing the SPE. + */ + if (!vgic_initialized(vcpu->kvm)) + return -ENODEV; + + ret = kvm_vgic_set_owner(vcpu, vcpu->arch.spe.irq_num, + &vcpu->arch.spe); + if (ret) + return ret; + } + + vcpu->arch.spe.created = true; + return 0; +} + +/* + * For one VM the interrupt type must be same for each vcpu. + * As a PPI, the interrupt number is the same for all vcpus, + * while as an SPI it must be a separate number per vcpu. + */ +static bool spe_irq_is_valid(struct kvm *kvm, int irq) +{ + int i; + struct kvm_vcpu *vcpu; + + kvm_for_each_vcpu(i, vcpu, kvm) { + if (!kvm_arm_spe_irq_initialized(vcpu)) + continue; + + if (vcpu->arch.spe.irq_num != irq) + return false; + } + + return true; +} + +int kvm_arm_spe_v1_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_SPE_V1_IRQ: { + int __user *uaddr = (int __user *)(long)attr->addr; + int irq; + + if (!irqchip_in_kernel(vcpu->kvm)) + return -EINVAL; + + if (!test_bit(KVM_ARM_VCPU_SPE_V1, vcpu->arch.features)) + return -ENODEV; + + if (get_user(irq, uaddr)) + return -EFAULT; + + /* The SPE overflow interrupt can be a PPI only */ + if (!(irq_is_ppi(irq))) + return -EINVAL; + + if (!spe_irq_is_valid(vcpu->kvm, irq)) + return -EINVAL; + + if (kvm_arm_spe_irq_initialized(vcpu)) + return -EBUSY; + + kvm_debug("Set kvm ARM SPE irq: %d\n", irq); + vcpu->arch.spe.irq_num = irq; + return 0; + } + case KVM_ARM_VCPU_SPE_V1_INIT: + return kvm_arm_spe_v1_init(vcpu); + } + + return -ENXIO; +} + +int kvm_arm_spe_v1_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_SPE_V1_IRQ: { + int __user *uaddr = (int __user *)(long)attr->addr; + int irq; + + if (!irqchip_in_kernel(vcpu->kvm)) + return -EINVAL; + + if (!test_bit(KVM_ARM_VCPU_SPE_V1, vcpu->arch.features)) + return -ENODEV; + + if (!kvm_arm_spe_irq_initialized(vcpu)) + return -ENXIO; + + irq = vcpu->arch.spe.irq_num; + return put_user(irq, uaddr); + } + } + + return -ENXIO; +} + +int kvm_arm_spe_v1_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_SPE_V1_IRQ: + case KVM_ARM_VCPU_SPE_V1_INIT: + if (kvm_arm_support_spe_v1() && + test_bit(KVM_ARM_VCPU_SPE_V1, vcpu->arch.features)) + return 0; + } + + return -ENXIO; +} From patchwork Fri Dec 20 14:30:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305635 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D5189109A for ; Fri, 20 Dec 2019 14:32:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BD2FB206CB for ; Fri, 20 Dec 2019 14:32:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727734AbfLTOb7 (ORCPT ); Fri, 20 Dec 2019 09:31:59 -0500 Received: from foss.arm.com ([217.140.110.172]:51312 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727983AbfLTObB (ORCPT ); Fri, 20 Dec 2019 09:31:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DB5FF11D4; Fri, 20 Dec 2019 06:31:00 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0EEF63F718; Fri, 20 Dec 2019 06:30:58 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 13/18] perf: arm_spe: Add KVM structure for obtaining IRQ info Date: Fri, 20 Dec 2019 14:30:20 +0000 Message-Id: <20191220143025.33853-14-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM requires knowledge of the physical SPE IRQ number such that it can associate it with any virtual IRQ for guests that require SPE emulation. Let's create a structure to hold this information and an accessor that KVM can use to retrieve this information. We expect that each SPE device will have the same physical PPI number and thus will warn when this is not the case. Signed-off-by: Andrew Murray --- drivers/perf/arm_spe_pmu.c | 23 +++++++++++++++++++++++ include/kvm/arm_spe.h | 6 ++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 4e4984a55cd1..2d24af4cfcab 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -34,6 +34,9 @@ #include #include +#include +#include + #include #include #include @@ -1127,6 +1130,24 @@ static void arm_spe_pmu_dev_teardown(struct arm_spe_pmu *spe_pmu) free_percpu_irq(spe_pmu->irq, spe_pmu->handle); } +#ifdef CONFIG_KVM_ARM_SPE +static struct arm_spe_kvm_info arm_spe_kvm_info; + +struct arm_spe_kvm_info *arm_spe_get_kvm_info(void) +{ + return &arm_spe_kvm_info; +} + +static void arm_spe_populate_kvm_info(struct arm_spe_pmu *spe_pmu) +{ + WARN_ON_ONCE(arm_spe_kvm_info.physical_irq != 0 && + arm_spe_kvm_info.physical_irq != spe_pmu->irq); + arm_spe_kvm_info.physical_irq = spe_pmu->irq; +} +#else +static void arm_spe_populate_kvm_info(struct arm_spe_pmu *spe_pmu) {} +#endif + /* Driver and device probing */ static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu) { @@ -1149,6 +1170,8 @@ static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu) } spe_pmu->irq = irq; + arm_spe_populate_kvm_info(spe_pmu); + return 0; } diff --git a/include/kvm/arm_spe.h b/include/kvm/arm_spe.h index d1f3c564dfd0..9c65130d726d 100644 --- a/include/kvm/arm_spe.h +++ b/include/kvm/arm_spe.h @@ -17,6 +17,12 @@ struct kvm_spe { bool irq_level; }; +struct arm_spe_kvm_info { + int physical_irq; +}; + +struct arm_spe_kvm_info *arm_spe_get_kvm_info(void); + #ifdef CONFIG_KVM_ARM_SPE #define kvm_arm_spe_v1_ready(v) ((v)->arch.spe.ready) #define kvm_arm_spe_irq_initialized(v) \ From patchwork Fri Dec 20 14:30:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305631 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B9436C1 for ; Fri, 20 Dec 2019 14:31:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0446A206CB for ; Fri, 20 Dec 2019 14:31:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728009AbfLTObE (ORCPT ); Fri, 20 Dec 2019 09:31:04 -0500 Received: from foss.arm.com ([217.140.110.172]:51318 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727995AbfLTObD (ORCPT ); Fri, 20 Dec 2019 09:31:03 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0FE4D12FC; Fri, 20 Dec 2019 06:31:03 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 370353F718; Fri, 20 Dec 2019 06:31:01 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 14/18] KVM: arm64: spe: Provide guest virtual interrupts for SPE Date: Fri, 20 Dec 2019 14:30:21 +0000 Message-Id: <20191220143025.33853-15-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Upon the exit of a guest, let's determine if the SPE device has generated an interrupt - if so we'll inject a virtual interrupt to the guest. Upon the entry and exit of a guest we'll also update the state of the physical IRQ such that it is active when a guest interrupt is pending and the guest is running. Finally we map the physical IRQ to the virtual IRQ such that the guest can deactivate the interrupt when it handles the interrupt. Signed-off-by: Andrew Murray --- include/kvm/arm_spe.h | 6 ++++ virt/kvm/arm/arm.c | 5 ++- virt/kvm/arm/spe.c | 71 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 81 insertions(+), 1 deletion(-) diff --git a/include/kvm/arm_spe.h b/include/kvm/arm_spe.h index 9c65130d726d..91b2214f543a 100644 --- a/include/kvm/arm_spe.h +++ b/include/kvm/arm_spe.h @@ -37,6 +37,9 @@ static inline bool kvm_arm_support_spe_v1(void) ID_AA64DFR0_PMSVER_SHIFT); } +void kvm_spe_flush_hwstate(struct kvm_vcpu *vcpu); +inline void kvm_spe_sync_hwstate(struct kvm_vcpu *vcpu); + int kvm_arm_spe_v1_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); int kvm_arm_spe_v1_get_attr(struct kvm_vcpu *vcpu, @@ -49,6 +52,9 @@ int kvm_arm_spe_v1_enable(struct kvm_vcpu *vcpu); #define kvm_arm_support_spe_v1() (false) #define kvm_arm_spe_irq_initialized(v) (false) +static inline void kvm_spe_flush_hwstate(struct kvm_vcpu *vcpu) {} +static inline void kvm_spe_sync_hwstate(struct kvm_vcpu *vcpu) {} + static inline int kvm_arm_spe_v1_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr) { diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 340d2388ee2c..a66085c8e785 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -741,6 +741,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) preempt_disable(); kvm_pmu_flush_hwstate(vcpu); + kvm_spe_flush_hwstate(vcpu); local_irq_disable(); @@ -782,6 +783,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) kvm_request_pending(vcpu)) { vcpu->mode = OUTSIDE_GUEST_MODE; isb(); /* Ensure work in x_flush_hwstate is committed */ + kvm_spe_sync_hwstate(vcpu); kvm_pmu_sync_hwstate(vcpu); if (static_branch_unlikely(&userspace_irqchip_in_use)) kvm_timer_sync_hwstate(vcpu); @@ -816,11 +818,12 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) kvm_arm_clear_debug(vcpu); /* - * We must sync the PMU state before the vgic state so + * We must sync the PMU and SPE state before the vgic state so * that the vgic can properly sample the updated state of the * interrupt line. */ kvm_pmu_sync_hwstate(vcpu); + kvm_spe_sync_hwstate(vcpu); /* * Sync the vgic state before syncing the timer state because diff --git a/virt/kvm/arm/spe.c b/virt/kvm/arm/spe.c index 83ac2cce2cc3..097ed39014e4 100644 --- a/virt/kvm/arm/spe.c +++ b/virt/kvm/arm/spe.c @@ -35,6 +35,68 @@ int kvm_arm_spe_v1_enable(struct kvm_vcpu *vcpu) return 0; } +static inline void set_spe_irq_phys_active(struct arm_spe_kvm_info *info, + bool active) +{ + int r; + r = irq_set_irqchip_state(info->physical_irq, IRQCHIP_STATE_ACTIVE, + active); + WARN_ON(r); +} + +void kvm_spe_flush_hwstate(struct kvm_vcpu *vcpu) +{ + struct kvm_spe *spe = &vcpu->arch.spe; + bool phys_active = false; + struct arm_spe_kvm_info *info = arm_spe_get_kvm_info(); + + if (!kvm_arm_spe_v1_ready(vcpu)) + return; + + if (irqchip_in_kernel(vcpu->kvm)) + phys_active = kvm_vgic_map_is_active(vcpu, spe->irq_num); + + phys_active |= spe->irq_level; + + set_spe_irq_phys_active(info, phys_active); +} + +void kvm_spe_sync_hwstate(struct kvm_vcpu *vcpu) +{ + struct kvm_spe *spe = &vcpu->arch.spe; + u64 pmbsr; + int r; + bool service; + struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; + struct arm_spe_kvm_info *info = arm_spe_get_kvm_info(); + + if (!kvm_arm_spe_v1_ready(vcpu)) + return; + + set_spe_irq_phys_active(info, false); + + pmbsr = ctxt->sys_regs[PMBSR_EL1]; + service = !!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT)); + if (spe->irq_level == service) + return; + + spe->irq_level = service; + + if (likely(irqchip_in_kernel(vcpu->kvm))) { + r = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, + spe->irq_num, service, spe); + WARN_ON(r); + } +} + +static inline bool kvm_arch_arm_spe_v1_get_input_level(int vintid) +{ + struct kvm_vcpu *vcpu = kvm_arm_get_running_vcpu(); + struct kvm_spe *spe = &vcpu->arch.spe; + + return spe->irq_level; +} + static int kvm_arm_spe_v1_init(struct kvm_vcpu *vcpu) { if (!kvm_arm_support_spe_v1()) @@ -48,6 +110,7 @@ static int kvm_arm_spe_v1_init(struct kvm_vcpu *vcpu) if (irqchip_in_kernel(vcpu->kvm)) { int ret; + struct arm_spe_kvm_info *info; /* * If using the SPE with an in-kernel virtual GIC @@ -57,10 +120,18 @@ static int kvm_arm_spe_v1_init(struct kvm_vcpu *vcpu) if (!vgic_initialized(vcpu->kvm)) return -ENODEV; + info = arm_spe_get_kvm_info(); + if (!info->physical_irq) + return -ENODEV; + ret = kvm_vgic_set_owner(vcpu, vcpu->arch.spe.irq_num, &vcpu->arch.spe); if (ret) return ret; + + ret = kvm_vgic_map_phys_irq(vcpu, info->physical_irq, + vcpu->arch.spe.irq_num, + kvm_arch_arm_spe_v1_get_input_level); } vcpu->arch.spe.created = true; From patchwork Fri Dec 20 14:30:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305629 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B2F366C1 for ; Fri, 20 Dec 2019 14:31:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 91BEB24684 for ; Fri, 20 Dec 2019 14:31:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727572AbfLTObl (ORCPT ); Fri, 20 Dec 2019 09:31:41 -0500 Received: from foss.arm.com ([217.140.110.172]:51332 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728025AbfLTObF (ORCPT ); Fri, 20 Dec 2019 09:31:05 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4079811D4; Fri, 20 Dec 2019 06:31:05 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5FB2F3F718; Fri, 20 Dec 2019 06:31:03 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 15/18] perf: arm_spe: Handle guest/host exclusion flags Date: Fri, 20 Dec 2019 14:30:22 +0000 Message-Id: <20191220143025.33853-16-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org A side effect of supporting the SPE in guests is that we prevent the host from collecting data whilst inside a guest thus creating a black-out window. This occurs because instead of emulating the SPE, we share it with our guests. Let's accurately describe our capabilities by using the perf exclude flags to prevent !exclude_guest and exclude_host flags from being used. Signed-off-by: Andrew Murray --- drivers/perf/arm_spe_pmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 2d24af4cfcab..3703dbf459de 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -679,6 +679,9 @@ static int arm_spe_pmu_event_init(struct perf_event *event) if (attr->exclude_idle) return -EOPNOTSUPP; + if (!attr->exclude_guest || attr->exclude_host) + return -EOPNOTSUPP; + /* * Feedback-directed frequency throttling doesn't work when we * have a buffer of samples. We'd need to manually count the From patchwork Fri Dec 20 14:30:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 233A3109A for ; Fri, 20 Dec 2019 14:31:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B23524689 for ; Fri, 20 Dec 2019 14:31:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728051AbfLTObI (ORCPT ); Fri, 20 Dec 2019 09:31:08 -0500 Received: from foss.arm.com ([217.140.110.172]:51340 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728039AbfLTObH (ORCPT ); Fri, 20 Dec 2019 09:31:07 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5FC1811B3; Fri, 20 Dec 2019 06:31:07 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 87C853F86C; Fri, 20 Dec 2019 06:31:05 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 16/18] KVM: arm64: enable SPE support Date: Fri, 20 Dec 2019 14:30:23 +0000 Message-Id: <20191220143025.33853-17-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sudeep Holla We have all the bits and pieces to enable SPE for guest in place, so lets enable it. Signed-off-by: Sudeep Holla Signed-off-by: Andrew Murray --- virt/kvm/arm/arm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index a66085c8e785..fb3ad0835255 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -611,6 +611,10 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu) return ret; ret = kvm_arm_pmu_v3_enable(vcpu); + if (ret) + return ret; + + ret = kvm_arm_spe_v1_enable(vcpu); return ret; } From patchwork Fri Dec 20 14:30:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305627 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1121B1892 for ; Fri, 20 Dec 2019 14:31:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E333421D7E for ; Fri, 20 Dec 2019 14:31:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728070AbfLTObL (ORCPT ); Fri, 20 Dec 2019 09:31:11 -0500 Received: from foss.arm.com ([217.140.110.172]:51352 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728060AbfLTObK (ORCPT ); Fri, 20 Dec 2019 09:31:10 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 893C611B3; Fri, 20 Dec 2019 06:31:09 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AFC5B3F718; Fri, 20 Dec 2019 06:31:07 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 17/18, KVMTOOL] update_headers: Sync kvm UAPI headers with linux v5.5-rc2 Date: Fri, 20 Dec 2019 14:30:24 +0000 Message-Id: <20191220143025.33853-18-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The local copies of the kvm user API headers are getting stale. In preparation for some arch-specific updated, this patch reflects a re-run of util/update_headers.sh to pull in upstream updates from linux v5.5-rc2. Signed-off-by: Sudeep Holla [ Update headers to v5.5-rc2 ] Signed-off-by: Andrew Murray --- arm/aarch32/include/asm/kvm.h | 7 +++++-- arm/aarch64/include/asm/kvm.h | 13 +++++++++++-- include/linux/kvm.h | 18 ++++++++++++++++++ powerpc/include/asm/kvm.h | 3 +++ 4 files changed, 37 insertions(+), 4 deletions(-) diff --git a/arm/aarch32/include/asm/kvm.h b/arm/aarch32/include/asm/kvm.h index a4217c1a5d01..03cd7c19a683 100644 --- a/arm/aarch32/include/asm/kvm.h +++ b/arm/aarch32/include/asm/kvm.h @@ -131,8 +131,9 @@ struct kvm_vcpu_events { struct { __u8 serror_pending; __u8 serror_has_esr; + __u8 ext_dabt_pending; /* Align it to 8 bytes */ - __u8 pad[6]; + __u8 pad[5]; __u64 serror_esr; } exception; __u32 reserved[12]; @@ -266,8 +267,10 @@ struct kvm_vcpu_events { #define KVM_DEV_ARM_ITS_CTRL_RESET 4 /* KVM_IRQ_LINE irq field index values */ +#define KVM_ARM_IRQ_VCPU2_SHIFT 28 +#define KVM_ARM_IRQ_VCPU2_MASK 0xf #define KVM_ARM_IRQ_TYPE_SHIFT 24 -#define KVM_ARM_IRQ_TYPE_MASK 0xff +#define KVM_ARM_IRQ_TYPE_MASK 0xf #define KVM_ARM_IRQ_VCPU_SHIFT 16 #define KVM_ARM_IRQ_VCPU_MASK 0xff #define KVM_ARM_IRQ_NUM_SHIFT 0 diff --git a/arm/aarch64/include/asm/kvm.h b/arm/aarch64/include/asm/kvm.h index 9a507716ae2f..905a73f30079 100644 --- a/arm/aarch64/include/asm/kvm.h +++ b/arm/aarch64/include/asm/kvm.h @@ -106,6 +106,7 @@ struct kvm_regs { #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ +#define KVM_ARM_VCPU_SPE_V1 7 /* Support guest SPEv1 */ struct kvm_vcpu_init { __u32 target; @@ -164,8 +165,9 @@ struct kvm_vcpu_events { struct { __u8 serror_pending; __u8 serror_has_esr; + __u8 ext_dabt_pending; /* Align it to 8 bytes */ - __u8 pad[6]; + __u8 pad[5]; __u64 serror_esr; } exception; __u32 reserved[12]; @@ -323,10 +325,17 @@ struct kvm_vcpu_events { #define KVM_ARM_VCPU_TIMER_CTRL 1 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 +#define KVM_ARM_VCPU_PVTIME_CTRL 2 +#define KVM_ARM_VCPU_PVTIME_IPA 0 +#define KVM_ARM_VCPU_SPE_V1_CTRL 3 +#define KVM_ARM_VCPU_SPE_V1_IRQ 0 +#define KVM_ARM_VCPU_SPE_V1_INIT 1 /* KVM_IRQ_LINE irq field index values */ +#define KVM_ARM_IRQ_VCPU2_SHIFT 28 +#define KVM_ARM_IRQ_VCPU2_MASK 0xf #define KVM_ARM_IRQ_TYPE_SHIFT 24 -#define KVM_ARM_IRQ_TYPE_MASK 0xff +#define KVM_ARM_IRQ_TYPE_MASK 0xf #define KVM_ARM_IRQ_VCPU_SHIFT 16 #define KVM_ARM_IRQ_VCPU_MASK 0xff #define KVM_ARM_IRQ_NUM_SHIFT 0 diff --git a/include/linux/kvm.h b/include/linux/kvm.h index 5e3f12d5359e..1a362c230e4a 100644 --- a/include/linux/kvm.h +++ b/include/linux/kvm.h @@ -235,6 +235,7 @@ struct kvm_hyperv_exit { #define KVM_EXIT_S390_STSI 25 #define KVM_EXIT_IOAPIC_EOI 26 #define KVM_EXIT_HYPERV 27 +#define KVM_EXIT_ARM_NISV 28 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -243,6 +244,8 @@ struct kvm_hyperv_exit { #define KVM_INTERNAL_ERROR_SIMUL_EX 2 /* Encounter unexpected vm-exit due to delivery event. */ #define KVM_INTERNAL_ERROR_DELIVERY_EV 3 +/* Encounter unexpected vm-exit reason */ +#define KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON 4 /* for KVM_RUN, returned by mmap(vcpu_fd, offset=0) */ struct kvm_run { @@ -392,6 +395,11 @@ struct kvm_run { } eoi; /* KVM_EXIT_HYPERV */ struct kvm_hyperv_exit hyperv; + /* KVM_EXIT_ARM_NISV */ + struct { + __u64 esr_iss; + __u64 fault_ipa; + } arm_nisv; /* Fix the size of the union. */ char padding[256]; }; @@ -996,6 +1004,12 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_ARM_PTRAUTH_ADDRESS 171 #define KVM_CAP_ARM_PTRAUTH_GENERIC 172 #define KVM_CAP_PMU_EVENT_FILTER 173 +#define KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 174 +#define KVM_CAP_HYPERV_DIRECT_TLBFLUSH 175 +#define KVM_CAP_PPC_GUEST_DEBUG_SSTEP 176 +#define KVM_CAP_ARM_NISV_TO_USER 177 +#define KVM_CAP_ARM_INJECT_EXT_DABT 178 +#define KVM_CAP_ARM_SPE_V1 179 #ifdef KVM_CAP_IRQ_ROUTING @@ -1142,6 +1156,7 @@ struct kvm_dirty_tlb { #define KVM_REG_S390 0x5000000000000000ULL #define KVM_REG_ARM64 0x6000000000000000ULL #define KVM_REG_MIPS 0x7000000000000000ULL +#define KVM_REG_RISCV 0x8000000000000000ULL #define KVM_REG_SIZE_SHIFT 52 #define KVM_REG_SIZE_MASK 0x00f0000000000000ULL @@ -1222,6 +1237,8 @@ enum kvm_device_type { #define KVM_DEV_TYPE_ARM_VGIC_ITS KVM_DEV_TYPE_ARM_VGIC_ITS KVM_DEV_TYPE_XIVE, #define KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_XIVE + KVM_DEV_TYPE_ARM_PV_TIME, +#define KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_MAX, }; @@ -1332,6 +1349,7 @@ struct kvm_s390_ucas_mapping { #define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char) /* Available with KVM_CAP_PMU_EVENT_FILTER */ #define KVM_SET_PMU_EVENT_FILTER _IOW(KVMIO, 0xb2, struct kvm_pmu_event_filter) +#define KVM_PPC_SVM_OFF _IO(KVMIO, 0xb3) /* ioctl for vm fd */ #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device) diff --git a/powerpc/include/asm/kvm.h b/powerpc/include/asm/kvm.h index b0f72dea8b11..264e266a85bf 100644 --- a/powerpc/include/asm/kvm.h +++ b/powerpc/include/asm/kvm.h @@ -667,6 +667,8 @@ struct kvm_ppc_cpu_char { /* PPC64 eXternal Interrupt Controller Specification */ #define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */ +#define KVM_DEV_XICS_GRP_CTRL 2 +#define KVM_DEV_XICS_NR_SERVERS 1 /* Layout of 64-bit source attribute values */ #define KVM_XICS_DESTINATION_SHIFT 0 @@ -683,6 +685,7 @@ struct kvm_ppc_cpu_char { #define KVM_DEV_XIVE_GRP_CTRL 1 #define KVM_DEV_XIVE_RESET 1 #define KVM_DEV_XIVE_EQ_SYNC 2 +#define KVM_DEV_XIVE_NR_SERVERS 3 #define KVM_DEV_XIVE_GRP_SOURCE 2 /* 64-bit source identifier */ #define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */ #define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */ From patchwork Fri Dec 20 14:30:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 11305623 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CEEA36C1 for ; Fri, 20 Dec 2019 14:31:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AE62324685 for ; Fri, 20 Dec 2019 14:31:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728076AbfLTOb3 (ORCPT ); Fri, 20 Dec 2019 09:31:29 -0500 Received: from foss.arm.com ([217.140.110.172]:51362 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727441AbfLTObM (ORCPT ); Fri, 20 Dec 2019 09:31:12 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B240831B; Fri, 20 Dec 2019 06:31:11 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D9AF03F718; Fri, 20 Dec 2019 06:31:09 -0800 (PST) From: Andrew Murray To: Marc Zyngier , Catalin Marinas , Will Deacon Cc: Sudeep Holla , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland Subject: [PATCH v2 18/18, KVMTOOL] kvm: add a vcpu feature for SPEv1 support Date: Fri, 20 Dec 2019 14:30:25 +0000 Message-Id: <20191220143025.33853-19-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191220143025.33853-1-andrew.murray@arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This is a runtime configurable for KVM tool to enable Statistical Profiling Extensions version 1 support in guest kernel. A command line option --spe is required to use the same. Signed-off-by: Sudeep Holla [ Add SPE to init features ] Signed-off-by: Andrew Murray --- Makefile | 2 +- arm/aarch64/arm-cpu.c | 2 + arm/aarch64/include/kvm/kvm-config-arch.h | 2 + arm/aarch64/include/kvm/kvm-cpu-arch.h | 3 +- arm/aarch64/kvm-cpu.c | 4 ++ arm/include/arm-common/kvm-config-arch.h | 1 + arm/include/arm-common/spe.h | 4 ++ arm/spe.c | 81 +++++++++++++++++++++++ 8 files changed, 97 insertions(+), 2 deletions(-) create mode 100644 arm/include/arm-common/spe.h create mode 100644 arm/spe.c diff --git a/Makefile b/Makefile index 3862112c5ec6..04dddb3e7699 100644 --- a/Makefile +++ b/Makefile @@ -158,7 +158,7 @@ endif # ARM OBJS_ARM_COMMON := arm/fdt.o arm/gic.o arm/gicv2m.o arm/ioport.o \ arm/kvm.o arm/kvm-cpu.o arm/pci.o arm/timer.o \ - arm/pmu.o + arm/pmu.o arm/spe.o HDRS_ARM_COMMON := arm/include ifeq ($(ARCH), arm) DEFINES += -DCONFIG_ARM diff --git a/arm/aarch64/arm-cpu.c b/arm/aarch64/arm-cpu.c index d7572b7790b1..6ccea033f361 100644 --- a/arm/aarch64/arm-cpu.c +++ b/arm/aarch64/arm-cpu.c @@ -6,6 +6,7 @@ #include "arm-common/gic.h" #include "arm-common/timer.h" #include "arm-common/pmu.h" +#include "arm-common/spe.h" #include #include @@ -17,6 +18,7 @@ static void generate_fdt_nodes(void *fdt, struct kvm *kvm) gic__generate_fdt_nodes(fdt, kvm->cfg.arch.irqchip); timer__generate_fdt_nodes(fdt, kvm, timer_interrupts); pmu__generate_fdt_nodes(fdt, kvm); + spe__generate_fdt_nodes(fdt, kvm); } static int arm_cpu__vcpu_init(struct kvm_cpu *vcpu) diff --git a/arm/aarch64/include/kvm/kvm-config-arch.h b/arm/aarch64/include/kvm/kvm-config-arch.h index 04be43dfa9b2..9968e1666de5 100644 --- a/arm/aarch64/include/kvm/kvm-config-arch.h +++ b/arm/aarch64/include/kvm/kvm-config-arch.h @@ -6,6 +6,8 @@ "Run AArch32 guest"), \ OPT_BOOLEAN('\0', "pmu", &(cfg)->has_pmuv3, \ "Create PMUv3 device"), \ + OPT_BOOLEAN('\0', "spe", &(cfg)->has_spev1, \ + "Create SPEv1 device"), \ OPT_U64('\0', "kaslr-seed", &(cfg)->kaslr_seed, \ "Specify random seed for Kernel Address Space " \ "Layout Randomization (KASLR)"), diff --git a/arm/aarch64/include/kvm/kvm-cpu-arch.h b/arm/aarch64/include/kvm/kvm-cpu-arch.h index 8dfb82ecbc37..080183fa4f81 100644 --- a/arm/aarch64/include/kvm/kvm-cpu-arch.h +++ b/arm/aarch64/include/kvm/kvm-cpu-arch.h @@ -8,7 +8,8 @@ #define ARM_VCPU_FEATURE_FLAGS(kvm, cpuid) { \ [0] = ((!!(cpuid) << KVM_ARM_VCPU_POWER_OFF) | \ (!!(kvm)->cfg.arch.aarch32_guest << KVM_ARM_VCPU_EL1_32BIT) | \ - (!!(kvm)->cfg.arch.has_pmuv3 << KVM_ARM_VCPU_PMU_V3)) \ + (!!(kvm)->cfg.arch.has_pmuv3 << KVM_ARM_VCPU_PMU_V3) | \ + (!!(kvm)->cfg.arch.has_spev1 << KVM_ARM_VCPU_SPE_V1)) \ } #define ARM_MPIDR_HWID_BITMASK 0xFF00FFFFFFUL diff --git a/arm/aarch64/kvm-cpu.c b/arm/aarch64/kvm-cpu.c index 9f3e8586880c..90c2e1784e97 100644 --- a/arm/aarch64/kvm-cpu.c +++ b/arm/aarch64/kvm-cpu.c @@ -140,6 +140,10 @@ void kvm_cpu__select_features(struct kvm *kvm, struct kvm_vcpu_init *init) /* Enable SVE if available */ if (kvm__supports_extension(kvm, KVM_CAP_ARM_SVE)) init->features[0] |= 1UL << KVM_ARM_VCPU_SVE; + + /* Enable SPE if available */ + if (kvm__supports_extension(kvm, KVM_CAP_ARM_SPE_V1)) + init->features[0] |= 1UL << KVM_ARM_VCPU_SPE_V1; } int kvm_cpu__configure_features(struct kvm_cpu *vcpu) diff --git a/arm/include/arm-common/kvm-config-arch.h b/arm/include/arm-common/kvm-config-arch.h index 5734c46ab9e6..742733e289af 100644 --- a/arm/include/arm-common/kvm-config-arch.h +++ b/arm/include/arm-common/kvm-config-arch.h @@ -9,6 +9,7 @@ struct kvm_config_arch { bool virtio_trans_pci; bool aarch32_guest; bool has_pmuv3; + bool has_spev1; u64 kaslr_seed; enum irqchip_type irqchip; u64 fw_addr; diff --git a/arm/include/arm-common/spe.h b/arm/include/arm-common/spe.h new file mode 100644 index 000000000000..bcfa40877f6f --- /dev/null +++ b/arm/include/arm-common/spe.h @@ -0,0 +1,4 @@ + +#define KVM_ARM_SPEV1_PPI 21 + +void spe__generate_fdt_nodes(void *fdt, struct kvm *kvm); diff --git a/arm/spe.c b/arm/spe.c new file mode 100644 index 000000000000..ec03b01a3866 --- /dev/null +++ b/arm/spe.c @@ -0,0 +1,81 @@ +#include "kvm/fdt.h" +#include "kvm/kvm.h" +#include "kvm/kvm-cpu.h" +#include "kvm/util.h" + +#include "arm-common/gic.h" +#include "arm-common/spe.h" + +#ifdef CONFIG_ARM64 +static int set_spe_attr(struct kvm *kvm, int vcpu_idx, + struct kvm_device_attr *attr) +{ + int ret, fd; + + fd = kvm->cpus[vcpu_idx]->vcpu_fd; + + ret = ioctl(fd, KVM_HAS_DEVICE_ATTR, attr); + if (!ret) { + ret = ioctl(fd, KVM_SET_DEVICE_ATTR, attr); + if (ret) + pr_err("SPE KVM_SET_DEVICE_ATTR failed (%d)\n", ret); + } else { + pr_err("Unsupported SPE on vcpu%d\n", vcpu_idx); + } + + return ret; +} + +void spe__generate_fdt_nodes(void *fdt, struct kvm *kvm) +{ + const char compatible[] = "arm,statistical-profiling-extension-v1"; + int irq = KVM_ARM_SPEV1_PPI; + int i, ret; + + u32 cpu_mask = (((1 << kvm->nrcpus) - 1) << GIC_FDT_IRQ_PPI_CPU_SHIFT) \ + & GIC_FDT_IRQ_PPI_CPU_MASK; + u32 irq_prop[] = { + cpu_to_fdt32(GIC_FDT_IRQ_TYPE_PPI), + cpu_to_fdt32(irq - 16), + cpu_to_fdt32(cpu_mask | IRQ_TYPE_LEVEL_HIGH), + }; + + if (!kvm->cfg.arch.has_spev1) + return; + + if (!kvm__supports_extension(kvm, KVM_CAP_ARM_SPE_V1)) { + pr_info("SPE unsupported\n"); + return; + } + + for (i = 0; i < kvm->nrcpus; i++) { + struct kvm_device_attr spe_attr; + + spe_attr = (struct kvm_device_attr){ + .group = KVM_ARM_VCPU_SPE_V1_CTRL, + .addr = (u64)(unsigned long)&irq, + .attr = KVM_ARM_VCPU_SPE_V1_IRQ, + }; + + ret = set_spe_attr(kvm, i, &spe_attr); + if (ret) + return; + + spe_attr = (struct kvm_device_attr){ + .group = KVM_ARM_VCPU_SPE_V1_CTRL, + .attr = KVM_ARM_VCPU_SPE_V1_INIT, + }; + + ret = set_spe_attr(kvm, i, &spe_attr); + if (ret) + return; + } + + _FDT(fdt_begin_node(fdt, "spe")); + _FDT(fdt_property(fdt, "compatible", compatible, sizeof(compatible))); + _FDT(fdt_property(fdt, "interrupts", irq_prop, sizeof(irq_prop))); + _FDT(fdt_end_node(fdt)); +} +#else +void spe__generate_fdt_nodes(void *fdt, struct kvm *kvm) { } +#endif