From patchwork Mon Dec 23 09:29:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11307931 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0BA8213A4 for ; Mon, 23 Dec 2019 09:30:41 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DA0C22073A for ; Mon, 23 Dec 2019 09:30:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="N/cafDWJ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DA0C22073A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1052+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id xAd0YY1556264x0TCtsL9dSy; Mon, 23 Dec 2019 01:30:40 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web10.1188.1577093440120576216 for ; Mon, 23 Dec 2019 01:30:40 -0800 X-Received: by mail.kernel.org (Postfix) id D68B820709; Mon, 23 Dec 2019 09:30:39 +0000 (UTC) X-Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B38B3206B7; Mon, 23 Dec 2019 09:30:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B38B3206B7 X-Received: by mail-pf1-f194.google.com with SMTP id w62so8886970pfw.8; Mon, 23 Dec 2019 01:30:39 -0800 (PST) X-Gm-Message-State: fTUwaseC2VE6ql7AbfAy6g2jx1554929AA= X-Google-Smtp-Source: APXvYqza5MD792QT+nyRwcyGu7WT8kB0fIjU+ImLq/F0W/YGH+avcbTNUD3sHcm/TzClUblK7TUxQA== X-Received: by 2002:a63:f202:: with SMTP id v2mr29843658pgh.420.1577093438868; Mon, 23 Dec 2019 01:30:38 -0800 (PST) X-Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id i127sm24625970pfc.55.2019.12.23.01.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Dec 2019 01:30:38 -0800 (PST) From: Chunyan Zhang To: Linuxkernel+Patchwork-Soc via Email Integration Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Chunyan Zhang , Chunyan Zhang Subject: [PATCH v5 1/3] dt-bindings: arm: sprd: add global registers bindings Date: Mon, 23 Dec 2019 17:29:46 +0800 Message-Id: <20191223092948.24824-2-zhang.lyra@gmail.com> In-Reply-To: <20191223092948.24824-1-zhang.lyra@gmail.com> References: <20191223092948.24824-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1577093440; bh=vJZOZCCbOVf2mY97Uv9ITa6ht3DRNv75Na/91d9dEds=; h=Cc:Date:From:Reply-To:Subject:To; b=N/cafDWJJTadgn8jr6szaaaPO4lOg9fMVSqlIyMA8TuE/538UPk1S5P/0wY7t9dC9rP 7bka1bL3VhQgdE+jUsrjQP1rRPw4nKryljEH3MXs0pgfSEBjq6XtGKWx9VjQ4HJXwMt47 GV+nDVOSUPlayqcyETZD3Z69fRvhp6jhw+Q= From: Chunyan Zhang The global registers would be used by different peripheral devices which we can see them as syscon clients which can use regmap interface that syscon driver provides. Signed-off-by: Chunyan Zhang --- .../bindings/arm/sprd/global-regs.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sprd/global-regs.yaml diff --git a/Documentation/devicetree/bindings/arm/sprd/global-regs.yaml b/Documentation/devicetree/bindings/arm/sprd/global-regs.yaml new file mode 100644 index 000000000000..012207166116 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sprd/global-regs.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019 Unisoc Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/sprd/global-regs.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Unisoc Global Registers + +maintainers: + - Orson Zhai + - Baolin Wang + - Chunyan Zhang + +properties: + compatible: + oneOf: + - items: + - enum: + - sprd,sc9860-glbregs + - sprd,sc9863a-glbregs + - const: syscon + + reg: + maxItems: 1 + +examples: + - | + apb_regs: syscon@402e0000 { + compatible = "sprd,sc9863a-glbregs", "syscon"; + reg = <0x402e0000 0x4000>; + }; + +... From patchwork Mon Dec 23 09:29:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11307933 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 42381109A for ; Mon, 23 Dec 2019 09:30:44 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1CE26207FF for ; Mon, 23 Dec 2019 09:30:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="YoqUCOTq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1CE26207FF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1053+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id TQs5YY1556264xPSl2Jq9rMb; Mon, 23 Dec 2019 01:30:43 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web10.1189.1577093443593608097 for ; Mon, 23 Dec 2019 01:30:43 -0800 X-Received: by mail.kernel.org (Postfix) id 6436F2073A; Mon, 23 Dec 2019 09:30:43 +0000 (UTC) X-Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 40117206B7; Mon, 23 Dec 2019 09:30:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 40117206B7 X-Received: by mail-pf1-f195.google.com with SMTP id i6so2040009pfc.1; Mon, 23 Dec 2019 01:30:43 -0800 (PST) X-Gm-Message-State: moOForY84VMvrgFFE6LI6d6bx1554929AA= X-Google-Smtp-Source: APXvYqy6jUhWMsGbnvXEiSZPKxZHudUU9AAn0+bumj0FabTgCjZ+gtRm8+ojZtiAV8heuhEuyYGcdQ== X-Received: by 2002:a65:6842:: with SMTP id q2mr31081741pgt.345.1577093442447; Mon, 23 Dec 2019 01:30:42 -0800 (PST) X-Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id i127sm24625970pfc.55.2019.12.23.01.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Dec 2019 01:30:41 -0800 (PST) From: Chunyan Zhang To: Linuxkernel+Patchwork-Soc via Email Integration Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Chunyan Zhang , Chunyan Zhang , Rob Herring Subject: [PATCH v5 2/3] dt-bindings: arm: move sprd board file to vendor directory Date: Mon, 23 Dec 2019 17:29:47 +0800 Message-Id: <20191223092948.24824-3-zhang.lyra@gmail.com> In-Reply-To: <20191223092948.24824-1-zhang.lyra@gmail.com> References: <20191223092948.24824-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1577093443; bh=V8gFrBVhv3edBIklQ3lCpa3a5/taLGWyP5N5WqZNfYo=; h=Cc:Date:From:Reply-To:Subject:To; b=YoqUCOTqb9WL/2w3PMtCxX7j8FJxifrNwgNSpjwCrWEFkNd62HMsLogtOOt+tJYmkEv aFOUht3fL3Y6xtYHK/LRvN4Md2pcTNmVxk5uU5fzNelHD9EXuaxnpjKKIvR1yKCrk91+l Fj5jAK5NMYEepGf/jQE+C5BSd8EmTHGBMz4= From: Chunyan Zhang We've created a vendor directory for sprd, so move the board bindings to there. Signed-off-by: Chunyan Zhang Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/{ => sprd}/sprd.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/arm/{ => sprd}/sprd.yaml (92%) diff --git a/Documentation/devicetree/bindings/arm/sprd.yaml b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml similarity index 92% rename from Documentation/devicetree/bindings/arm/sprd.yaml rename to Documentation/devicetree/bindings/arm/sprd/sprd.yaml index c35fb845ccaa..0258a96bfbde 100644 --- a/Documentation/devicetree/bindings/arm/sprd.yaml +++ b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml @@ -2,7 +2,7 @@ # Copyright 2019 Unisoc Inc. %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/sprd.yaml# +$id: http://devicetree.org/schemas/arm/sprd/sprd.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Unisoc platforms device tree bindings From patchwork Mon Dec 23 09:29:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11307935 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B7D9D13A4 for ; Mon, 23 Dec 2019 09:30:48 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 91FFD206B7 for ; Mon, 23 Dec 2019 09:30:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="pPB1hCZX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 91FFD206B7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1054+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id fDw9YY1556264xCKOCMPeSih; Mon, 23 Dec 2019 01:30:48 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web09.1168.1577093448126353763 for ; Mon, 23 Dec 2019 01:30:48 -0800 X-Received: by mail.kernel.org (Postfix) id E10A220709; Mon, 23 Dec 2019 09:30:47 +0000 (UTC) X-Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BE415206B7; Mon, 23 Dec 2019 09:30:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BE415206B7 X-Received: by mail-pg1-f195.google.com with SMTP id 6so8532859pgk.0; Mon, 23 Dec 2019 01:30:47 -0800 (PST) X-Gm-Message-State: phR2WbbV6ORGw2WdOvNV0xufx1554929AA= X-Google-Smtp-Source: APXvYqzZs42QrZP5lEE1tkaAWzWiiPap4DLdfu9Y7x07/+eWKcjDjMn3lc6ZbBFNiurLDnD93lWVgA== X-Received: by 2002:a65:420d:: with SMTP id c13mr31045579pgq.101.1577093446556; Mon, 23 Dec 2019 01:30:46 -0800 (PST) X-Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id i127sm24625970pfc.55.2019.12.23.01.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Dec 2019 01:30:45 -0800 (PST) From: Chunyan Zhang To: Linuxkernel+Patchwork-Soc via Email Integration Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Chunyan Zhang , Chunyan Zhang Subject: [PATCH v5 3/3] arm64: dts: Add Unisoc's SC9863A SoC support Date: Mon, 23 Dec 2019 17:29:48 +0800 Message-Id: <20191223092948.24824-4-zhang.lyra@gmail.com> In-Reply-To: <20191223092948.24824-1-zhang.lyra@gmail.com> References: <20191223092948.24824-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1577093448; bh=Qp3gdMhsEgi6TM6Us90ZJHgXZYRJv2ew0q5UmNmcaSU=; h=Cc:Date:From:Reply-To:Subject:To; b=pPB1hCZXSFmJQjXiPxooSQ5ZmeE7WcYYmzIEkEObf4O5fo3hct+OsIiMGZIwAh4bITh bvjK9TZYXW9FIxADrRDvNEzBMBPuqJ6leON2E5oVfTZy7ker16c2rPPWdCo/jL7U2UF7q UgubbMbdTlYAjAPrvzacQl2VoegI6xdOSP8= From: Chunyan Zhang Add basic DT to support Unisoc's SC9863A, with this patch, the board sp9863a-1h10 can run into console. Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/Makefile | 3 +- arch/arm64/boot/dts/sprd/sc9863a.dtsi | 523 ++++++++++++++++++++++ arch/arm64/boot/dts/sprd/sharkl3.dtsi | 78 ++++ arch/arm64/boot/dts/sprd/sp9863a-1h10.dts | 39 ++ 4 files changed, 642 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/sprd/sc9863a.dtsi create mode 100644 arch/arm64/boot/dts/sprd/sharkl3.dtsi create mode 100644 arch/arm64/boot/dts/sprd/sp9863a-1h10.dts diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile index 2bdc23804f40..f4f1f5148cc2 100644 --- a/arch/arm64/boot/dts/sprd/Makefile +++ b/arch/arm64/boot/dts/sprd/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \ - sp9860g-1h10.dtb + sp9860g-1h10.dtb \ + sp9863a-1h10.dtb diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi new file mode 100644 index 000000000000..cd80756c888d --- /dev/null +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Unisoc SC9863A SoC DTS file + * + * Copyright (C) 2019, Unisoc Inc. + */ + +#include +#include "sharkl3.dtsi" + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + core4 { + cpu = <&CPU4>; + }; + core5 { + cpu = <&CPU5>; + }; + core6 { + cpu = <&CPU6>; + }; + core7 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + }; + + idle-states { + entry-method = "arm,psci"; + CORE_PD: core-pd { + compatible = "arm,idle-state"; + entry-latency-us = <4000>; + exit-latency-us = <4000>; + min-residency-us = <10000>; + local-timer-stop; + arm,psci-suspend-param = <0x00010000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure PPI */ + , /* Physical Non-Secure PPI */ + , /* Virtual PPI */ + ; /* Hipervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + ; + }; + + soc { + gic: interrupt-controller@14000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + redistributor-stride = <0x0 0x20000>; /* 128KB stride */ + #redistributor-regions = <1>; + interrupt-controller; + reg = <0x0 0x14000000 0 0x20000>, /* GICD */ + <0x0 0x14040000 0 0x100000>; /* GICR */ + interrupts = ; + }; + + funnel@10001000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x10001000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_soc_out_port: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; + + in-ports { + port { + funnel_soc_in_port: endpoint { + remote-endpoint = + <&funnel_ca55_out_port>; + }; + }; + }; + }; + + etb@10003000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x10003000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + in-ports { + port { + etb_in: endpoint { + remote-endpoint = + <&funnel_soc_out_port>; + }; + }; + }; + }; + + funnel@12001000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x12001000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_little_out_port: endpoint { + remote-endpoint = + <&etf_little_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_little_in_port0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_little_in_port1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_little_in_port2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_little_in_port3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + }; + + etf@12002000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x12002000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_little_out: endpoint { + remote-endpoint = + <&funnel_ca55_in_port0>; + }; + }; + }; + + in-port { + port { + etf_little_in: endpoint { + remote-endpoint = + <&funnel_little_out_port>; + }; + }; + }; + }; + + etf@12003000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x12003000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_big_out: endpoint { + remote-endpoint = + <&funnel_ca55_in_port1>; + }; + }; + }; + + in-ports { + port { + etf_big_in: endpoint { + remote-endpoint = + <&funnel_big_out_port>; + }; + }; + }; + }; + + funnel@12004000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x12004000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_ca55_out_port: endpoint { + remote-endpoint = + <&funnel_soc_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ca55_in_port0: endpoint { + remote-endpoint = + <&etf_little_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_ca55_in_port1: endpoint { + remote-endpoint = + <&etf_big_out>; + }; + }; + }; + }; + + funnel@12005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x12005000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_big_out_port: endpoint { + remote-endpoint = + <&etf_big_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_big_in_port0: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_big_in_port1: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_big_in_port2: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_big_in_port3: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + etm@13040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13040000 0 0x1000>; + cpu = <&CPU0>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&funnel_little_in_port0>; + }; + }; + }; + }; + + etm@13140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13140000 0 0x1000>; + cpu = <&CPU1>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&funnel_little_in_port1>; + }; + }; + }; + }; + + etm@13240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13240000 0 0x1000>; + cpu = <&CPU2>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&funnel_little_in_port2>; + }; + }; + }; + }; + + etm@13340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13340000 0 0x1000>; + cpu = <&CPU3>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&funnel_little_in_port3>; + }; + }; + }; + }; + + etm@13440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13440000 0 0x1000>; + cpu = <&CPU4>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&funnel_big_in_port0>; + }; + }; + }; + }; + + etm@13540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13540000 0 0x1000>; + cpu = <&CPU5>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&funnel_big_in_port1>; + }; + }; + }; + }; + + etm@13640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13640000 0 0x1000>; + cpu = <&CPU6>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&funnel_big_in_port2>; + }; + }; + }; + }; + + etm@13740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x13740000 0 0x1000>; + cpu = <&CPU7>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&funnel_big_in_port3>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/sprd/sharkl3.dtsi b/arch/arm64/boot/dts/sprd/sharkl3.dtsi new file mode 100644 index 000000000000..0222128b10f7 --- /dev/null +++ b/arch/arm64/boot/dts/sprd/sharkl3.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Unisoc Sharkl3 platform DTS file + * + * Copyright (C) 2019, Unisoc Inc. + */ + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + apb@70000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x70000000 0x10000000>; + + uart0: serial@0 { + compatible = "sprd,sc9863a-uart", + "sprd,sc9836-uart"; + reg = <0x0 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart1: serial@100000 { + compatible = "sprd,sc9863a-uart", + "sprd,sc9836-uart"; + reg = <0x100000 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart2: serial@200000 { + compatible = "sprd,sc9863a-uart", + "sprd,sc9836-uart"; + reg = <0x200000 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart3: serial@300000 { + compatible = "sprd,sc9863a-uart", + "sprd,sc9836-uart"; + reg = <0x300000 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart4: serial@400000 { + compatible = "sprd,sc9863a-uart", + "sprd,sc9836-uart"; + reg = <0x400000 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + }; + }; + + ext_26m: ext-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext-26m"; + }; +}; diff --git a/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts b/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts new file mode 100644 index 000000000000..5c32c1596337 --- /dev/null +++ b/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Unisoc SP9863A-1h10 boards DTS file + * + * Copyright (C) 2019, Unisoc Inc. + */ + +/dts-v1/; + +#include "sc9863a.dtsi" + +/ { + model = "Spreadtrum SP9863A-1H10 Board"; + + compatible = "sprd,sp9863a-1h10", "sprd,sc9863a"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + bootargs = "earlycon"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +};