From patchwork Fri Dec 27 06:36:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11310935 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 85E04138D for ; Fri, 27 Dec 2019 06:37:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6E81C206CB for ; Fri, 27 Dec 2019 06:37:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726354AbfL0Gg7 (ORCPT ); Fri, 27 Dec 2019 01:36:59 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:54727 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725854AbfL0Gg7 (ORCPT ); Fri, 27 Dec 2019 01:36:59 -0500 Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 27 Dec 2019 14:37:17 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH v3 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings Date: Fri, 27 Dec 2019 14:36:41 +0800 Message-ID: <1577428606-69855-2-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> References: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add the Amlogic A1 Family USB2 PHY Bindings It supports Host mode only. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- .../bindings/phy/amlogic,meson-a1-usb2-phy.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml new file mode 100644 index 00000000..2b2c526 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Amlogic, Inc +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/amlogic,meson-a1-usb2-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic A1 USB2 PHY + +maintainers: + - Yue Wang + +properties: + compatible: + enum: + - amlogic,meson-a1-usb2-phy + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: phy + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 1 + description: + a phandle to respective power domain node as described by generic + PM domain bindings (see power/power_domain.txt for more information). + +required: + - compatible + - reg + - resets + - reset-names + - "#phy-cells" + - power-domains + +examples: + - | + usb2_phy1: phy@40000 { + status = "okay"; + compatible = "amlogic,a1-usb2-phy"; + reg = <0x0 0x40000 0x0 0x2000>; + resets = <&reset RESET_USBPHY>; + reset-names = "phy"; + #phy-cells = <0>; + power-domains = <&pwrc PWRC_USB_ID>; + }; From patchwork Fri Dec 27 06:36:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11310937 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4DD31138D for ; Fri, 27 Dec 2019 06:37:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3684C208C4 for ; Fri, 27 Dec 2019 06:37:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726408AbfL0GhB (ORCPT ); Fri, 27 Dec 2019 01:37:01 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:54727 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726343AbfL0GhA (ORCPT ); Fri, 27 Dec 2019 01:37:00 -0500 Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 27 Dec 2019 14:37:17 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH v3 2/6] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings Date: Fri, 27 Dec 2019 14:36:42 +0800 Message-ID: <1577428606-69855-3-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> References: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The Amlogic A1 SoC Family embeds 1 USB Controllers: - a DWC3 IP configured as Host for USB2 and USB3 A glue connects the controllers to the USB2 PHY of A1 SoC. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- .../bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml | 57 +++++++++++++++++++--- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml index 4efb77b..6103cc2 100644 --- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml +++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml @@ -9,6 +9,8 @@ title: Amlogic Meson G12A DWC3 USB SoC Controller Glue maintainers: - Neil Armstrong + - Hanjie Lin + - Yue Wang description: | The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 @@ -22,10 +24,14 @@ description: | The DWC3 Glue controls the PHY routing and power, an interrupt line is connected to the Glue to serve as OTG ID change detection. + The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in + host-only mode. + properties: compatible: enum: - amlogic,meson-g12a-usb-ctrl + - amlogic,meson-a1-usb-ctrl ranges: true @@ -37,6 +43,11 @@ properties: clocks: minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 resets: minItems: 1 @@ -47,17 +58,22 @@ properties: interrupts: maxItems: 1 + phys: + minItems: 1 + maxItems: 3 + phy-names: items: - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used - const: usb3-phy0 # USB3 PHY if USB3_0 is used - phys: - minItems: 1 - maxItems: 3 - - dr_mode: true + dr_mode: + description: usb mode for G12A + enum: + - host + - peripheral + - otg power-domains: maxItems: 1 @@ -80,9 +96,9 @@ required: - resets - reg - interrupts - - phy-names - phys - dr_mode + - phy-names examples: - | @@ -124,4 +140,33 @@ examples: snps,quirk-frame-length-adjustment; }; }; + - | + a1_usb: usb@ffe09000 { + status = "okay"; + compatible = "amlogic,meson-a1-usb-ctrl"; + reg = <0 0xffe09000 0x0 0xa0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&clkc_periphs 36>, + <&clkc_periphs 85>, + <&clkc_periphs 2>, + <&clkc_periphs 3>; + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_phy", + "xtal_usb_ctrl"; + + resets = <&reset 36>; + + phys = <&usb2_phy1>; + phy-names = "usb2-phy1"; + + a1_dwc3: usb@ff400000 { + compatible = "snps,dwc3"; + reg = <0xff400000 0x100000>; + interrupts = <0 90 4>; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + }; + }; From patchwork Fri Dec 27 06:36:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11310939 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B54F13A4 for ; Fri, 27 Dec 2019 06:37:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4AB6C208C4 for ; Fri, 27 Dec 2019 06:37:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726491AbfL0GhD (ORCPT ); Fri, 27 Dec 2019 01:37:03 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:54727 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725854AbfL0GhC (ORCPT ); Fri, 27 Dec 2019 01:37:02 -0500 Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 27 Dec 2019 14:37:18 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH v3 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver Date: Fri, 27 Dec 2019 14:36:43 +0800 Message-ID: <1577428606-69855-4-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> References: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org This adds support for the USB2 PHY found in the Amlogic A1 SoC Family. It supports host mode only. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- drivers/phy/amlogic/phy-meson-g12a-usb2.c | 93 +++++++++++++++++++++---------- 1 file changed, 64 insertions(+), 29 deletions(-) diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c index 9065ffc..a564747 100644 --- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c @@ -146,11 +146,17 @@ #define RESET_COMPLETE_TIME 1000 #define PLL_RESET_COMPLETE_TIME 100 +enum meson_soc_id { + MESON_SOC_G12A = 0, + MESON_SOC_A1, +}; + struct phy_meson_g12a_usb2_priv { struct device *dev; struct regmap *regmap; struct clk *clk; struct reset_control *reset; + int soc_id; }; static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = { @@ -164,6 +170,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) { struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy); int ret; + unsigned int value; ret = reset_control_reset(priv->reset); if (ret) @@ -192,18 +199,22 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) | FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9)); - regmap_write(priv->regmap, PHY_CTRL_R18, - FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | - FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | - FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) | - FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) | - FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) | - FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) | - FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) | - FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) | - FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) | - FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) | - PHY_CTRL_R18_MPLL_ACG_RANGE); + value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) | + FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) | + FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) | + FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) | + FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) | + FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) | + FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) | + FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) | + PHY_CTRL_R18_MPLL_ACG_RANGE; + + if (priv->soc_id == MESON_SOC_A1) + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL; + + regmap_write(priv->regmap, PHY_CTRL_R18, value); udelay(PLL_RESET_COMPLETE_TIME); @@ -227,13 +238,24 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) | FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0)); - regmap_write(priv->regmap, PHY_CTRL_R4, - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) | - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) | - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) | - PHY_CTRL_R4_TEST_BYPASS_MODE_EN | - FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) | - FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0)); + if (priv->soc_id == MESON_SOC_G12A) + regmap_write(priv->regmap, PHY_CTRL_R4, + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) | + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) | + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) | + PHY_CTRL_R4_TEST_BYPASS_MODE_EN | + FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) | + FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0)); + else if (priv->soc_id == MESON_SOC_A1) { + regmap_write(priv->regmap, PHY_CTRL_R21, + PHY_CTRL_R21_USB2_CAL_ACK_EN | + PHY_CTRL_R21_USB2_TX_STRG_PD | + FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2)); + + /* Analog Settings */ + regmap_write(priv->regmap, PHY_CTRL_R13, + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7)); + } /* Tuning Disconnect Threshold */ regmap_write(priv->regmap, PHY_CTRL_R3, @@ -241,11 +263,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy) FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) | FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3)); - /* Analog Settings */ - regmap_write(priv->regmap, PHY_CTRL_R14, 0); - regmap_write(priv->regmap, PHY_CTRL_R13, - PHY_CTRL_R13_UPDATE_PMA_SIGNALS | - FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7)); + if (priv->soc_id == MESON_SOC_G12A) { + /* Analog Settings */ + regmap_write(priv->regmap, PHY_CTRL_R14, 0); + regmap_write(priv->regmap, PHY_CTRL_R13, + PHY_CTRL_R13_UPDATE_PMA_SIGNALS | + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7)); + } return 0; } @@ -286,14 +310,18 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev); + priv->regmap = devm_regmap_init_mmio(dev, base, &phy_meson_g12a_usb2_regmap_conf); if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); - priv->clk = devm_clk_get(dev, "xtal"); - if (IS_ERR(priv->clk)) - return PTR_ERR(priv->clk); + if (priv->soc_id == MESON_SOC_G12A) { + priv->clk = devm_clk_get(dev, "xtal"); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + } priv->reset = devm_reset_control_get(dev, "phy"); if (IS_ERR(priv->reset)) @@ -321,8 +349,15 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev) } static const struct of_device_id phy_meson_g12a_usb2_of_match[] = { - { .compatible = "amlogic,g12a-usb2-phy", }, - { }, + { + .compatible = "amlogic,g12a-usb2-phy", + .data = (void *)MESON_SOC_G12A, + }, + { + .compatible = "amlogic,a1-usb2-phy", + .data = (void *)MESON_SOC_A1, + }, + { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match); From patchwork Fri Dec 27 06:36:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11310943 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 20716138D for ; Fri, 27 Dec 2019 06:37:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 001B7208C4 for ; Fri, 27 Dec 2019 06:37:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726502AbfL0GhF (ORCPT ); Fri, 27 Dec 2019 01:37:05 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:54727 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726483AbfL0GhE (ORCPT ); Fri, 27 Dec 2019 01:37:04 -0500 Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 27 Dec 2019 14:37:18 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH v3 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue Date: Fri, 27 Dec 2019 14:36:44 +0800 Message-ID: <1577428606-69855-5-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> References: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Adds support for Amlogic A1 USB Control Glue HW. The Amlogic A1 SoC Family embeds 1 USB Controllers: - a DWC3 IP configured as Host for USB2 and USB3 A glue connects the controllers to the USB2 PHY of A1 SoC. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- drivers/usb/dwc3/dwc3-meson-g12a.c | 105 +++++++++++++++++++++++++++---------- 1 file changed, 78 insertions(+), 27 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 8a3ec1a..916a200 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -96,6 +96,11 @@ #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8) #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16) +enum meson_soc_id { + MESON_SOC_G12A = 0, + MESON_SOC_A1, +}; + enum { USB2_HOST_PHY = 0, USB2_OTG_PHY, @@ -107,10 +112,22 @@ static const char *phy_names[PHY_COUNT] = { "usb2-phy0", "usb2-phy1", "usb3-phy0", }; +static const struct clk_bulk_data meson_g12a_clocks[] = { + { .id = NULL}, +}; + +static const struct clk_bulk_data meson_a1_clocks[] = { + { .id = "usb_ctrl"}, + { .id = "usb_bus"}, + { .id = "xtal_usb_phy"}, + { .id = "xtal_usb_ctrl"}, +}; + struct dwc3_meson_g12a { struct device *dev; struct regmap *regmap; - struct clk *clk; + struct clk_bulk_data *clks; + int num_clks; struct reset_control *reset; struct phy *phys[PHY_COUNT]; enum usb_dr_mode otg_mode; @@ -120,6 +137,7 @@ struct dwc3_meson_g12a { struct regulator *vbus; struct usb_role_switch_desc switch_desc; struct usb_role_switch *role_switch; + int soc_id; }; static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, @@ -138,10 +156,13 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) { int i; - if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) - priv->otg_phy_mode = PHY_MODE_USB_DEVICE; - else - priv->otg_phy_mode = PHY_MODE_USB_HOST; + /* only G12A supports otg mode */ + if (priv->soc_id == MESON_SOC_G12A) { + if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) + priv->otg_phy_mode = PHY_MODE_USB_DEVICE; + else + priv->otg_phy_mode = PHY_MODE_USB_HOST; + } for (i = 0 ; i < USB3_HOST_PHY ; ++i) { if (!priv->phys[i]) @@ -151,7 +172,7 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) U2P_R0_POWER_ON_RESET, U2P_R0_POWER_ON_RESET); - if (i == USB2_OTG_PHY) { + if (priv->soc_id == MESON_SOC_G12A && i == USB2_OTG_PHY) { regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, @@ -295,7 +316,8 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv, { int ret; - if (!priv->phys[USB2_OTG_PHY]) + /* only G12A supports otg mode */ + if (priv->soc_id != MESON_SOC_G12A || !priv->phys[USB2_OTG_PHY]) return -EINVAL; if (mode == PHY_MODE_USB_HOST) @@ -409,17 +431,32 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) priv->vbus = NULL; } - priv->clk = devm_clk_get(dev, NULL); - if (IS_ERR(priv->clk)) - return PTR_ERR(priv->clk); + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev); + + if (priv->soc_id == MESON_SOC_G12A) { + priv->clks = devm_kmemdup(dev, meson_g12a_clocks, + sizeof(meson_g12a_clocks), + GFP_KERNEL); + priv->num_clks = ARRAY_SIZE(meson_g12a_clocks); + } else if (priv->soc_id == MESON_SOC_A1) { + priv->clks = devm_kmemdup(dev, meson_a1_clocks, + sizeof(meson_a1_clocks), + GFP_KERNEL); + priv->num_clks = ARRAY_SIZE(meson_a1_clocks); + } else { + return -EINVAL; + } + + if (!priv->clks) + return -ENOMEM; - ret = clk_prepare_enable(priv->clk); + ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks); if (ret) return ret; - devm_add_action_or_reset(dev, - (void(*)(void *))clk_disable_unprepare, - priv->clk); + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return ret; platform_set_drvdata(pdev, priv); priv->dev = dev; @@ -433,22 +470,23 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) ret = reset_control_reset(priv->reset); if (ret) - return ret; + goto err_disable_clks; ret = dwc3_meson_g12a_get_phys(priv); if (ret) - return ret; + goto err_disable_clks; if (priv->vbus) { ret = regulator_enable(priv->vbus); if (ret) - return ret; + goto err_disable_clks; } /* Get dr_mode */ priv->otg_mode = usb_get_dr_mode(dev); - if (priv->otg_mode == USB_DR_MODE_OTG) { + if (priv->soc_id == MESON_SOC_G12A && + priv->otg_mode == USB_DR_MODE_OTG) { /* Ack irq before registering */ regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_IRQ, 0); @@ -458,7 +496,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) dwc3_meson_g12a_irq_thread, IRQF_ONESHOT, pdev->name, priv); if (ret) - return ret; + goto err_disable_clks; } dwc3_meson_g12a_usb_init(priv); @@ -467,7 +505,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) for (i = 0 ; i < PHY_COUNT ; ++i) { ret = phy_init(priv->phys[i]); if (ret) - return ret; + goto err_disable_clks; } /* Set PHY Power */ @@ -478,10 +516,11 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) } ret = of_platform_populate(np, NULL, NULL, dev); - if (ret) { - clk_disable_unprepare(priv->clk); + if (ret) goto err_phys_power; - } + + if (priv->soc_id != MESON_SOC_G12A) + goto setup_pm_runtime; /* Setup OTG mode corresponding to the ID pin */ if (priv->otg_mode == USB_DR_MODE_OTG) { @@ -504,6 +543,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) if (IS_ERR(priv->role_switch)) dev_warn(dev, "Unable to register Role Switch\n"); +setup_pm_runtime: pm_runtime_set_active(dev); pm_runtime_enable(dev); pm_runtime_get_sync(dev); @@ -518,6 +558,9 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) for (i = 0 ; i < PHY_COUNT ; ++i) phy_exit(priv->phys[i]); +err_disable_clks: + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + return ret; } @@ -527,7 +570,8 @@ static int dwc3_meson_g12a_remove(struct platform_device *pdev) struct device *dev = &pdev->dev; int i; - usb_role_switch_unregister(priv->role_switch); + if (priv->soc_id == MESON_SOC_G12A) + usb_role_switch_unregister(priv->role_switch); of_platform_depopulate(dev); @@ -547,7 +591,7 @@ static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev) { struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); - clk_disable(priv->clk); + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); return 0; } @@ -556,7 +600,7 @@ static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev) { struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); - return clk_enable(priv->clk); + return clk_bulk_prepare_enable(priv->num_clks, priv->clks); } static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev) @@ -619,7 +663,14 @@ static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = { }; static const struct of_device_id dwc3_meson_g12a_match[] = { - { .compatible = "amlogic,meson-g12a-usb-ctrl" }, + { + .compatible = "amlogic,meson-g12a-usb-ctrl", + .data = (void *)MESON_SOC_G12A, + }, + { + .compatible = "amlogic,meson-a1-usb-ctrl", + .data = (void *)MESON_SOC_A1, + }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match); From patchwork Fri Dec 27 06:36:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11310945 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7887B13A4 for ; Fri, 27 Dec 2019 06:37:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 57DA62173E for ; Fri, 27 Dec 2019 06:37:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726584AbfL0GhG (ORCPT ); Fri, 27 Dec 2019 01:37:06 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:54727 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726495AbfL0GhF (ORCPT ); Fri, 27 Dec 2019 01:37:05 -0500 Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 27 Dec 2019 14:37:18 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH v3 5/6] arm64: dts: meson: a1: Enable USB2 PHY Date: Fri, 27 Dec 2019 14:36:45 +0800 Message-ID: <1577428606-69855-6-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> References: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Enable USB2 PHY for Meson A1 SoC. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 6fdc0dd..bd63374a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { compatible = "amlogic,a1"; @@ -100,6 +101,16 @@ #power-domain-cells = <1>; status = "okay"; }; + + usb2_phy1: phy@40000 { + status = "okay"; + compatible = "amlogic,a1-usb2-phy"; + reg = <0x0 0x40000 0x0 0x2000>; + resets = <&reset RESET_USBPHY>; + reset-names = "phy"; + #phy-cells = <0>; + power-domains = <&pwrc PWRC_USB_ID>; + }; }; gic: interrupt-controller@ff901000 { From patchwork Fri Dec 27 06:36:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11310947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE9EA13A4 for ; Fri, 27 Dec 2019 06:37:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BBEDF2173E for ; Fri, 27 Dec 2019 06:37:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726605AbfL0GhH (ORCPT ); Fri, 27 Dec 2019 01:37:07 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:54727 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726483AbfL0GhH (ORCPT ); Fri, 27 Dec 2019 01:37:07 -0500 Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 27 Dec 2019 14:37:18 +0800 From: Hanjie Lin To: Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH v3 6/6] arm64: dts: meson: a1: Enable DWC3 controller Date: Fri, 27 Dec 2019 14:36:46 +0800 Message-ID: <1577428606-69855-7-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> References: <1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Enable DWC3 controller for Meson A1 SoC. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index bd63374a..76f787d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -7,6 +7,8 @@ #include #include #include +#include +#include / { compatible = "amlogic,a1"; @@ -125,6 +127,37 @@ #interrupt-cells = <3>; #address-cells = <0>; }; + + usb: usb@ffe09000 { + status = "okay"; + compatible = "amlogic,meson-a1-usb-ctrl"; + reg = <0x0 0xffe09000 0x0 0xa0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc_periphs CLKID_USB_CTRL>, + <&clkc_periphs CLKID_USB_BUS>, + <&clkc_periphs CLKID_XTAL_USB_PHY>, + <&clkc_periphs CLKID_XTAL_USB_CTRL>; + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_phy", + "xtal_usb_ctrl"; + resets = <&reset RESET_USBCTRL>; + + dr_mode = "host"; + + phys = <&usb2_phy1>; + phy-names = "usb2-phy1"; + + dwc3: usb@ff400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff400000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + }; + }; }; timer {