From patchwork Mon Dec 30 18:50:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 11313631 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 71072138D for ; Mon, 30 Dec 2019 18:50:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 43F3020409 for ; Mon, 30 Dec 2019 18:50:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jC0L2VYZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727621AbfL3Sue (ORCPT ); Mon, 30 Dec 2019 13:50:34 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:45598 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727278AbfL3Sue (ORCPT ); Mon, 30 Dec 2019 13:50:34 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBUIoV3Q059668; Mon, 30 Dec 2019 12:50:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1577731831; bh=K/zgbiWOtXqQ9vevxL61UQfd+KZVNoS3lO85fhB6OJY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jC0L2VYZS2RA8gA6eucN22QpIXh8RYpMOw40eDZBsh50syEGayNUEjT2S8AuMAUW/ AkrE1eCf2ZlOT9kYWstUVRujDlfKVzaSLa3a0zyFLdgxcoSzNitYwW2ZiXVGoQwhVK PtHG6Od+gC4lTiZBDOrkcEU5GgqxtGac2ybiSKBQ= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBUIoV7O097214 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 30 Dec 2019 12:50:31 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 30 Dec 2019 12:50:31 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 30 Dec 2019 12:50:31 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBUIoVCa015884; Mon, 30 Dec 2019 12:50:31 -0600 Received: from localhost ([10.250.65.50]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id xBUIoUu06779; Mon, 30 Dec 2019 12:50:30 -0600 (CST) From: "Andrew F. Davis" To: Tony Lindgren CC: , , "Andrew F . Davis" Subject: [PATCH v3 1/4] ARM: OMAP2+: Add omap_secure_init callback hook for secure initialization Date: Mon, 30 Dec 2019 13:50:01 -0500 Message-ID: <20191230185004.32279-2-afd@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191230185004.32279-1-afd@ti.com> References: <20191230185004.32279-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org This can be used for detecting secure features or making early device init sequence changes based on device security type. Signed-off-by: Andrew F. Davis --- arch/arm/mach-omap2/io.c | 11 +++++++++++ arch/arm/mach-omap2/omap-secure.c | 4 ++++ arch/arm/mach-omap2/omap-secure.h | 2 ++ 3 files changed, 17 insertions(+) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 349e48042982..f28047233665 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -51,6 +51,7 @@ #include "prm33xx.h" #include "prm44xx.h" #include "opp2xxx.h" +#include "omap-secure.h" /* * omap_clk_soc_init: points to a function that does the SoC-specific @@ -430,6 +431,7 @@ void __init omap2420_init_early(void) omap_hwmod_init_postsetup(); omap_clk_soc_init = omap2420_dt_clk_init; rate_table = omap2420_rate_table; + omap_secure_init(); } void __init omap2420_init_late(void) @@ -454,6 +456,7 @@ void __init omap2430_init_early(void) omap_hwmod_init_postsetup(); omap_clk_soc_init = omap2430_dt_clk_init; rate_table = omap2430_rate_table; + omap_secure_init(); } void __init omap2430_init_late(void) @@ -481,6 +484,7 @@ void __init omap3_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_secure_init(); } void __init omap3430_init_early(void) @@ -533,6 +537,7 @@ void __init ti814x_init_early(void) dm814x_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dm814x_dt_clk_init; + omap_secure_init(); } void __init ti816x_init_early(void) @@ -549,6 +554,7 @@ void __init ti816x_init_early(void) dm816x_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dm816x_dt_clk_init; + omap_secure_init(); } #endif @@ -566,6 +572,7 @@ void __init am33xx_init_early(void) am33xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = am33xx_dt_clk_init; + omap_secure_init(); } void __init am33xx_init_late(void) @@ -589,6 +596,7 @@ void __init am43xx_init_early(void) omap_hwmod_init_postsetup(); omap_l2_cache_init(); omap_clk_soc_init = am43xx_dt_clk_init; + omap_secure_init(); } void __init am43xx_init_late(void) @@ -617,6 +625,7 @@ void __init omap4430_init_early(void) omap_hwmod_init_postsetup(); omap_l2_cache_init(); omap_clk_soc_init = omap4xxx_dt_clk_init; + omap_secure_init(); } void __init omap4430_init_late(void) @@ -643,6 +652,7 @@ void __init omap5_init_early(void) omap54xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = omap5xxx_dt_clk_init; + omap_secure_init(); } void __init omap5_init_late(void) @@ -666,6 +676,7 @@ void __init dra7xx_init_early(void) dra7xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dra7xx_dt_clk_init; + omap_secure_init(); } void __init dra7xx_init_late(void) diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index 24298e47b9f1..e936732cdc4f 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -163,3 +163,7 @@ u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) NO_FLAG, 3, ptr, count, flag, 0); } + +void __init omap_secure_init(void) +{ +} diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 20046e8f8ecb..9aeeb236a224 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -72,6 +72,8 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); +void omap_secure_init(void); + #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER void set_cntfreq(void); #else From patchwork Mon Dec 30 18:50:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 11313633 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B7CC8138D for ; Mon, 30 Dec 2019 18:50:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 93C3E20409 for ; Mon, 30 Dec 2019 18:50:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="SYFhu2ft" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727655AbfL3Suk (ORCPT ); Mon, 30 Dec 2019 13:50:40 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:58020 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727278AbfL3Suk (ORCPT ); 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Mon, 30 Dec 2019 12:50:36 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBUIoarN043929; Mon, 30 Dec 2019 12:50:36 -0600 Received: from localhost ([10.250.65.50]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id xBUIoZu06881; Mon, 30 Dec 2019 12:50:35 -0600 (CST) From: "Andrew F. Davis" To: Tony Lindgren CC: , , "Andrew F . Davis" Subject: [PATCH v3 2/4] ARM: OMAP2+: Introduce check for OP-TEE in omap_secure_init() Date: Mon, 30 Dec 2019 13:50:02 -0500 Message-ID: <20191230185004.32279-3-afd@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191230185004.32279-1-afd@ti.com> References: <20191230185004.32279-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org This check and associated flag can be used to signal the presence of OP-TEE on the platform. This can be used to determine which SMC calls to make to perform secure operations. Signed-off-by: Andrew F. Davis --- arch/arm/mach-omap2/omap-secure.c | 14 ++++++++++++++ arch/arm/mach-omap2/omap-secure.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index e936732cdc4f..39d8070aede6 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -20,6 +21,18 @@ static phys_addr_t omap_secure_memblock_base; +bool optee_available; + +static void __init omap_optee_init_check(void) +{ + struct device_node *np; + + np = of_find_node_by_path("/firmware/optee"); + if (np && of_device_is_available(np)) + optee_available = true; + of_node_put(np); +} + /** * omap_sec_dispatcher: Routine to dispatch low power secure * service routines @@ -166,4 +179,5 @@ u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) void __init omap_secure_init(void) { + omap_optee_init_check(); } diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 9aeeb236a224..78a1c4f04bbe 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -10,6 +10,8 @@ #ifndef OMAP_ARCH_OMAP_SECURE_H #define OMAP_ARCH_OMAP_SECURE_H +#include + /* Monitor error code */ #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF @@ -72,6 +74,7 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); +extern bool optee_available; void omap_secure_init(void); #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER From patchwork Mon Dec 30 18:50:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 11313635 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF6B11395 for ; Mon, 30 Dec 2019 18:50:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B200320409 for ; Mon, 30 Dec 2019 18:50:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="h9SkhOD6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727673AbfL3Sup (ORCPT ); Mon, 30 Dec 2019 13:50:45 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:44330 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727278AbfL3Suo (ORCPT ); Mon, 30 Dec 2019 13:50:44 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBUIogDP033123; Mon, 30 Dec 2019 12:50:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1577731842; bh=oq06FeNTSrVdnZTZ0YySVTawPG99vf9FqZbFKv4Mw80=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=h9SkhOD6XwQ1f5O6Vv2JTYW0vIhhWhTiu944vPTogW44wholL1bvRjc1PuURidvbi O2EzkUmm/vVzgvqEtjwVMlqZQr+QBwL8vJnWPksqr6a/RgtlpUD/e1n1eickymo8k7 RX7K9ea+AeqQDq3HoOzENyb05MRjf7r1bzpsUmBI= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBUIogml048226 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 30 Dec 2019 12:50:42 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 30 Dec 2019 12:50:42 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 30 Dec 2019 12:50:42 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBUIofMv044153; Mon, 30 Dec 2019 12:50:41 -0600 Received: from localhost ([10.250.65.50]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id xBUIofu06990; Mon, 30 Dec 2019 12:50:41 -0600 (CST) From: "Andrew F. Davis" To: Tony Lindgren CC: , , "Andrew F . Davis" Subject: [PATCH v3 3/4] ARM: OMAP2+: Use ARM SMC Calling Convention when OP-TEE is available Date: Mon, 30 Dec 2019 13:50:03 -0500 Message-ID: <20191230185004.32279-4-afd@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191230185004.32279-1-afd@ti.com> References: <20191230185004.32279-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On High-Security(HS) OMAP2+ class devices a couple actions must be performed from the ARM TrustZone during boot. These traditionally can be performed by calling into the secure ROM code resident in this secure world using legacy SMC calls. Optionally OP-TEE can replace this secure world functionality by replacing the ROM after boot. ARM recommends a standard calling convention is used for this interaction (SMC Calling Convention). We check for the presence of OP-TEE and use this type of call to perform the needed actions, falling back to the legacy OMAP ROM call if OP-TEE is not available. Signed-off-by: Andrew F. Davis --- arch/arm/mach-omap2/common.h | 2 +- arch/arm/mach-omap2/omap-secure.c | 27 +++++++++++++++++++++++++++ arch/arm/mach-omap2/omap-secure.h | 2 ++ arch/arm/mach-omap2/omap-smc.S | 6 +++--- 4 files changed, 33 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 223b37c48389..3b1fd8e7d705 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -255,7 +255,7 @@ extern void gic_dist_disable(void); extern void gic_dist_enable(void); extern bool gic_dist_disabled(void); extern void gic_timer_retrigger(void); -extern void omap_smc1(u32 fn, u32 arg); +extern void _omap_smc1(u32 fn, u32 arg); extern void omap4_sar_ram_init(void); extern void __iomem *omap4_get_sar_ram_base(void); extern void omap4_mpuss_early_init(void); diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index 39d8070aede6..3a09d860c7a9 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -8,6 +8,7 @@ * Copyright (C) 2013 Pali Rohár */ +#include #include #include #include @@ -17,12 +18,17 @@ #include #include +#include "common.h" #include "omap-secure.h" static phys_addr_t omap_secure_memblock_base; bool optee_available; +#define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_SIP, (func_num)) + static void __init omap_optee_init_check(void) { struct device_node *np; @@ -66,6 +72,27 @@ u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, return ret; } +void omap_smccc_smc(u32 fn, u32 arg) +{ + struct arm_smccc_res res; + + arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg, + 0, 0, 0, 0, 0, 0, &res); + WARN(res.a0, "Secure function call 0x%08x failed\n", fn); +} + +void omap_smc1(u32 fn, u32 arg) +{ + /* + * If this platform has OP-TEE installed we use ARM SMC calls + * otherwise fall back to the OMAP ROM style calls. + */ + if (optee_available) + omap_smccc_smc(fn, arg); + else + _omap_smc1(fn, arg); +} + /* Allocate the memory to save secure ram */ int __init omap_secure_ram_reserve_memblock(void) { diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 78a1c4f04bbe..736e594365f4 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -62,6 +62,8 @@ extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, u32 arg3, u32 arg4); +extern void omap_smccc_smc(u32 fn, u32 arg); +extern void omap_smc1(u32 fn, u32 arg); extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs); extern phys_addr_t omap_secure_ram_mempool_base(void); diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S index fd2bcd91f4a1..d4832845a4e8 100644 --- a/arch/arm/mach-omap2/omap-smc.S +++ b/arch/arm/mach-omap2/omap-smc.S @@ -18,18 +18,18 @@ * the monitor API number. It uses few CPU registers * internally and hence they need be backed up including * link register "lr". - * Function signature : void omap_smc1(u32 fn, u32 arg) + * Function signature : void _omap_smc1(u32 fn, u32 arg) */ .arch armv7-a .arch_extension sec -ENTRY(omap_smc1) +ENTRY(_omap_smc1) stmfd sp!, {r2-r12, lr} mov r12, r0 mov r0, r1 dsb smc #0 ldmfd sp!, {r2-r12, pc} -ENDPROC(omap_smc1) +ENDPROC(_omap_smc1) /** * u32 omap_smc2(u32 id, u32 falg, u32 pargs) From patchwork Mon Dec 30 18:50:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 11313637 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 521A31395 for ; Mon, 30 Dec 2019 18:50:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 307DC20409 for ; Mon, 30 Dec 2019 18:50:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hmtGRWwe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727687AbfL3Sut (ORCPT ); Mon, 30 Dec 2019 13:50:49 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:44338 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727278AbfL3Sut (ORCPT ); Mon, 30 Dec 2019 13:50:49 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBUIolJp033147; Mon, 30 Dec 2019 12:50:47 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1577731847; bh=4xHbqA2AvQ1Ph+xX9DQl0PYR8DUBmPi/SjnZd2OQaXo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hmtGRWwe99nSiVAY7NOrRcRI6K/imzEa+aArB2YWeCWRIkQzKu1JYG4UXk+wg70tZ HOWS6ntqXMO/Q8213txAmmMNJE0UxTIarbmK8H/b7ZGU58ATcif3V9QdC6EX355Ru+ pmWpX7rs9azZ7mUbKxRiQvcLLLB4DPXsjwo5rwNY= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBUIoltZ035307; Mon, 30 Dec 2019 12:50:47 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 30 Dec 2019 12:50:46 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 30 Dec 2019 12:50:46 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBUIokq1055963; Mon, 30 Dec 2019 12:50:46 -0600 Received: from localhost ([10.250.65.50]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id xBUIoju07076; Mon, 30 Dec 2019 12:50:46 -0600 (CST) From: "Andrew F. Davis" To: Tony Lindgren CC: , , "Andrew F . Davis" Subject: [PATCH v3 4/4] ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers Date: Mon, 30 Dec 2019 13:50:04 -0500 Message-ID: <20191230185004.32279-5-afd@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191230185004.32279-1-afd@ti.com> References: <20191230185004.32279-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org During suspend CPU context may be lost in both non-secure and secure CPU states. The kernel can handle saving and restoring the non-secure context but must call into the secure side to allow it to save any context it may lose. Add these calls here. Note that on systems with OP-TEE available the suspend call is issued to OP-TEE using the ARM SMCCC, but the resume call is always issued to the ROM. This is because on waking from suspend the ROM is restored as the secure monitor. It is this resume call that instructs the ROM to restore OP-TEE, all subsequent calls will be handled by OP-TEE and should use the ARM SMCCC. Signed-off-by: Andrew F. Davis Acked-by: Dave Gerlach --- arch/arm/mach-omap2/omap-secure.h | 3 +++ arch/arm/mach-omap2/pm33xx-core.c | 17 +++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 736e594365f4..ba8c486c0454 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -53,6 +53,9 @@ #define OMAP4_PPA_L2_POR_INDEX 0x23 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 +#define AM43xx_PPA_SVC_PM_SUSPEND 0x71 +#define AM43xx_PPA_SVC_PM_RESUME 0x72 + /* Secure RX-51 PPA (Primary Protected Application) APIs */ #define RX51_PPA_HWRNG 29 #define RX51_PPA_L2_INVAL 40 diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c index f11442ed3eff..4a564f676ff9 100644 --- a/arch/arm/mach-omap2/pm33xx-core.c +++ b/arch/arm/mach-omap2/pm33xx-core.c @@ -28,6 +28,7 @@ #include "prm33xx.h" #include "soc.h" #include "sram.h" +#include "omap-secure.h" static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; static struct clockdomain *gfx_l4ls_clkdm; @@ -166,6 +167,16 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), { int ret = 0; + /* Suspend secure side on HS devices */ + if (omap_type() != OMAP2_DEVICE_TYPE_GP) { + if (optee_available) + omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0); + else + omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND, + FLAG_START_CRITICAL, + 0, 0, 0, 0, 0); + } + amx3_pre_suspend_common(); scu_power_mode(scu_base, SCU_PM_POWEROFF); ret = cpu_suspend(args, fn); @@ -174,6 +185,12 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), if (!am43xx_check_off_mode_enable()) amx3_post_suspend_common(); + /* Resume secure side on HS devices */ + if (omap_type() != OMAP2_DEVICE_TYPE_GP) + omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME, + FLAG_START_CRITICAL, + 0, 0, 0, 0, 0); + return ret; }