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Mon, 24 Sep 2018 11:01:27 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges1new.samsung.com (EUCPMTA) with SMTP id C6.0D.04441.604C8AB5; Mon, 24 Sep 2018 12:01:26 +0100 (BST) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180924110126eucas1p221aba92e694fcdf2f0f288f20a0b07a2~XUQaHjDIW0509905099eucas1p2I; Mon, 24 Sep 2018 11:01:26 +0000 (GMT) X-AuditID: cbfec7f2-5e3ff70000001159-a8-5ba8c4066190 Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id B1.FE.04284.504C8AB5; Mon, 24 Sep 2018 12:01:25 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PFK00GQA3YABG50@eusync1.samsung.com>; Mon, 24 Sep 2018 12:01:25 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Joonyoung Shim , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH] clk: samsung: exynos5420: Enable PERIS clocks for suspend Date: Mon, 24 Sep 2018 13:01:20 +0200 Message-id: <20180924110120.21319-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBIsWRmVeSWpSXmKPExsWy7djP87psR1ZEG/y5a2mxccZ6VovrX56z Wry4d5HF4vz5DewWH3vusVrMOL+PyWLtkbvsFu1PXzI7cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZD47JF1xgr1g1cQNzA+MOti5GTg4JAROJDwe7mEFsIYEVjBI3p6V3MXIB 2Z8ZJa6eWckIU3R6/WJ2iMQyRon/1zezQjgNTBK/7nWDjWITMJToetsFZosIOEh8/vSaEaSI WaCXSeL/6YtgCWEBL4n5366CjWURUJXY3n6CCcTmFbCVaD72DeomeYnVGw4wgzRLCDxklfg9 /zoLRMJFYvb/R1A3CUu8Or6FHcKWkejsOMgE0dDMKNE+YxY7hNPDKLF1Dsyr1hKHj19kBbGZ BfgkJm2bDrSCAyjOK9HRJgRR4iGx/doCFkhoxErcfbGXaQKjxAJGhlWM4qmlxbnpqcWGeanl esWJucWleel6yfm5mxiB8XX63/FPOxi/Xko6xCjAwajEw8twb3m0EGtiWXFl7iFGCQ5mJRFe t1tAId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rx8WmnRQgLpiSWp2ampBalFMFkmDk6pBsb9KtGt 7ebTla8dWiYQf855h/8Ce9POtGtX5hg/nbbo1+H6X9kL1dorNd9Z/dfbLl2QxJkom9wrxKNQ cTs0672ocsiOJAVbzorzyjN5JmplSJlsP7H6U80Lv3Mp3y40PN511da4yHNyZkv5n++mT1TX lltn7dFLv/okvys48IVmdLOWr1APnxJLcUaioRZzUXEiACRAKgGrAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrFJMWRmVeSWpSXmKPExsVy+t/xy7qsR1ZEGxzdYWGxccZ6VovrX56z Wry4d5HF4vz5DewWH3vusVrMOL+PyWLtkbvsFu1PXzI7cHhsWtXJ5tG3ZRWjx+dNcgHMUVw2 Kak5mWWpRfp2CVwZD47JF1xgr1g1cQNzA+MOti5GTg4JAROJ0+sXs3cxcnEICSxhlDh+7BAT hNPEJNHzYw4jSBWbgKFE19susA4RAQeJz59eM4IUMQv0M0nsPPqWGSQhLOAlMf/bVbAGFgFV ie3tJ5hAbF4BW4nmY9+g1slLrN5wgHkCI9cCRoZVjCKppcW56bnFhnrFibnFpXnpesn5uZsY gSGw7djPzTsYL20MPsQowMGoxMPLcG95tBBrYllxZe4hRgkOZiURXrdbQCHelMTKqtSi/Pii 0pzU4kOM0hwsSuK85w0qo4QE0hNLUrNTUwtSi2CyTBycUg2MDvlX/yi5O55zq+63tDq1/OzH 3PmLVHV1+p5slt34uONbWdxtycTGNf9WvlpqmsyjY+4fcXFtf7sDG7fnCaeLATxC70+yhpsL hd1KuMHD4RTcdCDYMPVs6RkJl3crKq/OcRB8oDvf8IDWmxzO/V2MKx4pCvU4xNzaaLlvV+dO c4eJJR7pU8SUWIozEg21mIuKEwFMHrKI/QEAAA== X-CMS-MailID: 20180924110126eucas1p221aba92e694fcdf2f0f288f20a0b07a2 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180924110126eucas1p221aba92e694fcdf2f0f288f20a0b07a2 References: Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Ensure that clocks for core SoC modules (including TZPC0..9 modules) are enabled for suspend/resume cycle. This fixes suspend/resume support on Exynos5422-based Odroid XU3/XU4 boards. Suggested-by: Joonyoung Shim Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5420.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index a2d6e7f4bcd3..34cce3c5898f 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -276,6 +276,7 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, + { .offset = GATE_IP_PERIS, .value = 0xffffffff, }, }; /* list of all parent clocks */