From patchwork Thu Jan 2 21:13:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11316053 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE175138C for ; Thu, 2 Jan 2020 21:15:23 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CA7FD21582 for ; Thu, 2 Jan 2020 21:15:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="eL9BWZOx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CA7FD21582 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=soleen.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1in7nJ-00017z-5V; Thu, 02 Jan 2020 21:14:13 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1in7nH-00017d-Ns for xen-devel@lists.xenproject.org; Thu, 02 Jan 2020 21:14:11 +0000 X-Inumbo-ID: cde31b8e-2da4-11ea-88e7-bc764e2007e4 Received: from mail-qv1-xf41.google.com (unknown [2607:f8b0:4864:20::f41]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id cde31b8e-2da4-11ea-88e7-bc764e2007e4; Thu, 02 Jan 2020 21:14:04 +0000 (UTC) Received: by mail-qv1-xf41.google.com with SMTP id p2so15474310qvo.10 for ; Thu, 02 Jan 2020 13:14:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=iY0wdT6Iyx/8ZKhCgZ1KdFJ1x/iuAERq6Pe9L1nXo/s=; b=eL9BWZOxdS+It5wCivmlzGJvzcHKxYfpeEJgOm/agfxG0fy8fHTWhK8NooW1Qg6hVC YWCJ/ORKZJbVJITfTKL5pleI0gtEkz+3x7Cju2sjYrLOABAzOdIlKO7U4fVlBpJ6A4z5 zkP8Trwi4Ek2K3i7mE3yzoFSKZqyJTWCIRLfXGOPk5rzE47mr+pOVkgKORYULGMGNqe1 82jxp+rE33JgphK8VS+M9p6Jjf3hrxNeRDsfzboK8qpHCnxeg/Y4/wtchPtJdEa3quI2 yZoXM3p8uoQnEl/fn+f3i0M0itchsq8FULtwHMcugghKpSCMCCGn6gyzs0e9JRDHU+xd 30uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=iY0wdT6Iyx/8ZKhCgZ1KdFJ1x/iuAERq6Pe9L1nXo/s=; b=LTjaDAeqxTU20wjHgoYvcvKENOzwQB9xKt0ktYwnGHdTOu5CxdWcJFCz1YHD3gVic5 kbAOkd3b6QMHmcs+2rlJLTwllZcG7TyJEcEJcv7QS5VGl5OKdCQCnn32bI83G6F6hAkI JRH2ZWGjtsq6m7Mszrjtmz0+xrUqO1P9G53ct7q0///hxg+0Jee0+NV0aUMfuWVtN12s 1a9KLorIgj/i78UgK9oHii9G8E8yoB42KI6TpTCridZrVUKujA6BhRWBB28Pb8WOmdDr B0YObDtMnozizvAl7tWWWH1N0cwrKaxexsHZgfTWg3nuTrB40F6H9s4c3MwzrZkZDSbN 03MA== X-Gm-Message-State: APjAAAUASAwErRSD5dtEbpvlhSx6Oge/GVOryTQzhis4B7TLquCr3yHj dXzmgeKXPInwD9HKKgHkj2tqRw== X-Google-Smtp-Source: APXvYqz2QuO4lxo78Y6Z0xG0VtOUyLpXY1pvFdChYQ3oReObbyuczepNVqWt0iK7l5riEUD6iu35yw== X-Received: by 2002:a05:6214:192f:: with SMTP id es15mr66400422qvb.219.1577999643711; Thu, 02 Jan 2020 13:14:03 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id f97sm17384185qtb.18.2020.01.02.13.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2020 13:14:03 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Thu, 2 Jan 2020 16:13:53 -0500 Message-Id: <20200102211357.8042-3-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200102211357.8042-1-pasha.tatashin@soleen.com> References: <20200102211357.8042-1-pasha.tatashin@soleen.com> Subject: [Xen-devel] [PATCH v5 2/6] arm/arm64/xen: use C inlines for privcmd_call X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" privcmd_call requires to enable access to userspace for the duration of the hypercall. Currently, this is done via assembly macros. Change it to C inlines instead. Signed-off-by: Pavel Tatashin Acked-by: Stefano Stabellini Reviewed-by: Julien Grall --- arch/arm/include/asm/xen/hypercall.h | 6 ++++++ arch/arm/xen/enlighten.c | 2 +- arch/arm/xen/hypercall.S | 4 ++-- arch/arm64/include/asm/xen/hypercall.h | 24 ++++++++++++++++++++++++ arch/arm64/xen/hypercall.S | 19 ++----------------- include/xen/arm/hypercall.h | 6 +++--- 6 files changed, 38 insertions(+), 23 deletions(-) diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h index c6882bba5284..cac5bd9ef519 100644 --- a/arch/arm/include/asm/xen/hypercall.h +++ b/arch/arm/include/asm/xen/hypercall.h @@ -2,4 +2,10 @@ #define _ASM_ARM_XEN_HYPERCALL_H #include +static inline long privcmd_call(unsigned int call, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5) +{ + return arch_privcmd_call(call, a1, a2, a3, a4, a5); +} #endif /* _ASM_ARM_XEN_HYPERCALL_H */ diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index dd6804a64f1a..e87280c6d25d 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -440,4 +440,4 @@ EXPORT_SYMBOL_GPL(HYPERVISOR_platform_op_raw); EXPORT_SYMBOL_GPL(HYPERVISOR_multicall); EXPORT_SYMBOL_GPL(HYPERVISOR_vm_assist); EXPORT_SYMBOL_GPL(HYPERVISOR_dm_op); -EXPORT_SYMBOL_GPL(privcmd_call); +EXPORT_SYMBOL_GPL(arch_privcmd_call); diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S index b11bba542fac..277078c7da49 100644 --- a/arch/arm/xen/hypercall.S +++ b/arch/arm/xen/hypercall.S @@ -94,7 +94,7 @@ HYPERCALL2(multicall); HYPERCALL2(vm_assist); HYPERCALL3(dm_op); -ENTRY(privcmd_call) +ENTRY(arch_privcmd_call) stmdb sp!, {r4} mov r12, r0 mov r0, r1 @@ -119,4 +119,4 @@ ENTRY(privcmd_call) ldm sp!, {r4} ret lr -ENDPROC(privcmd_call); +ENDPROC(arch_privcmd_call); diff --git a/arch/arm64/include/asm/xen/hypercall.h b/arch/arm64/include/asm/xen/hypercall.h index c3198f9ccd2e..1a74fb28607f 100644 --- a/arch/arm64/include/asm/xen/hypercall.h +++ b/arch/arm64/include/asm/xen/hypercall.h @@ -1,5 +1,29 @@ #ifndef _ASM_ARM64_XEN_HYPERCALL_H #define _ASM_ARM64_XEN_HYPERCALL_H #include +#include +static inline long privcmd_call(unsigned int call, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5) +{ + long rv; + + /* + * Privcmd calls are issued by the userspace. The kernel needs to + * enable access to TTBR0_EL1 as the hypervisor would issue stage 1 + * translations to user memory via AT instructions. Since AT + * instructions are not affected by the PAN bit (ARMv8.1), we only + * need the explicit uaccess_enable/disable if the TTBR0 PAN emulation + * is enabled (it implies that hardware UAO and PAN disabled). + */ + uaccess_ttbr0_enable(); + rv = arch_privcmd_call(call, a1, a2, a3, a4, a5); + /* + * Disable userspace access from kernel once the hyp call completed. + */ + uaccess_ttbr0_disable(); + + return rv; +} #endif /* _ASM_ARM64_XEN_HYPERCALL_H */ diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S index c5f05c4a4d00..921611778d2a 100644 --- a/arch/arm64/xen/hypercall.S +++ b/arch/arm64/xen/hypercall.S @@ -49,7 +49,6 @@ #include #include -#include #include @@ -86,27 +85,13 @@ HYPERCALL2(multicall); HYPERCALL2(vm_assist); HYPERCALL3(dm_op); -ENTRY(privcmd_call) +ENTRY(arch_privcmd_call) mov x16, x0 mov x0, x1 mov x1, x2 mov x2, x3 mov x3, x4 mov x4, x5 - /* - * Privcmd calls are issued by the userspace. The kernel needs to - * enable access to TTBR0_EL1 as the hypervisor would issue stage 1 - * translations to user memory via AT instructions. Since AT - * instructions are not affected by the PAN bit (ARMv8.1), we only - * need the explicit uaccess_enable/disable if the TTBR0 PAN emulation - * is enabled (it implies that hardware UAO and PAN disabled). - */ - uaccess_ttbr0_enable x6, x7, x8 hvc XEN_IMM - - /* - * Disable userspace access from kernel once the hyp call completed. - */ - uaccess_ttbr0_disable x6, x7 ret -ENDPROC(privcmd_call); +ENDPROC(arch_privcmd_call); diff --git a/include/xen/arm/hypercall.h b/include/xen/arm/hypercall.h index babcc08af965..624c8ad7e42a 100644 --- a/include/xen/arm/hypercall.h +++ b/include/xen/arm/hypercall.h @@ -41,9 +41,9 @@ struct xen_dm_op_buf; -long privcmd_call(unsigned call, unsigned long a1, - unsigned long a2, unsigned long a3, - unsigned long a4, unsigned long a5); +long arch_privcmd_call(unsigned int call, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5); int HYPERVISOR_xen_version(int cmd, void *arg); int HYPERVISOR_console_io(int cmd, int count, char *str); int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count); From patchwork Thu Jan 2 21:13:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11316045 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 21DBC138C for ; Thu, 2 Jan 2020 21:15:19 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F20B2217F4 for ; Thu, 2 Jan 2020 21:15:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="ASVWYtcu" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F20B2217F4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=soleen.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1in7nN-000193-FJ; Thu, 02 Jan 2020 21:14:17 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1in7nM-00018l-Mt for xen-devel@lists.xenproject.org; Thu, 02 Jan 2020 21:14:16 +0000 X-Inumbo-ID: cefe7a0e-2da4-11ea-a914-bc764e2007e4 Received: from mail-qt1-x842.google.com (unknown [2607:f8b0:4864:20::842]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id cefe7a0e-2da4-11ea-a914-bc764e2007e4; Thu, 02 Jan 2020 21:14:05 +0000 (UTC) Received: by mail-qt1-x842.google.com with SMTP id n15so35572600qtp.5 for ; Thu, 02 Jan 2020 13:14:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=OGOfxfwChenCUUYWwVx63kTdDOJ5xGJqR8SyGhsE/0o=; b=ASVWYtcuY5JgNsB9AmozFOaf3IagjfA7LG3Kld7VSh0wYdUywlMDvMCo/I8a8oS5Zo iFquKkCITUBqnTv97Xw9a4spOa16Ao90LXXcKxSco8vKrPptHC6t48IMitnpndg5KWwX 5rFUdBFejur9ImoKK+WQFhdw+wJcf5cNhI8CGlMrDDUNKcCB2W7OWG3ipnFtsga7Aqaw GXE6e6Y2Uag5Xdz5iQSfJJkoxlqtFdLDAw8cdgiGekyjuc06GpLIG0PGd78mI8UIVx2d yUg+045k3AZZGpxH8hyN6yQ52VCHgdxjIbPXYY2MwMroUxCwBur7C1ZK7AE0k5sYjaXK yJGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=OGOfxfwChenCUUYWwVx63kTdDOJ5xGJqR8SyGhsE/0o=; b=VApyoAIXCNoK2eGk8smALV33/cBRz59tqhiwW45uiLtYu2PCOR76P825oMKylHY3at aWCXS55KlTl2MVbKTjFHEOJo11dwFMMCNjpu8RDniGt+ypVkPJYBfdOvPz6lwuLWcIQY CpGgWnFaF5Y37WbxG2og/pVVn6NcoOY+ptrM6a1qJoeWhA8HjnzNQqLccpHbOO0lE958 1xYO6PPyCanH9JbxGUB5OMmpXDXBK8K6AJBvYmkkWtnABpm6sIpApvkRU7+aj92lIqcB W/OxroCxNUyTranL+n5BQcgns1Sl+sBAP5fKESIDR9/fOMSML1UyteSKnsKzageZW4cz eUlQ== X-Gm-Message-State: APjAAAXtD0wkWumdyYbg3Xl+3NREXoS7uEGuJygu9bbYfdZARDiK6/Gd CBajy2p/FajbSaEFSefWEh87Fw== X-Google-Smtp-Source: APXvYqw7yHNZGnj4/bjHHjA907ucWBhe02hvFPT3nG+AplQbPkSo5eatsNyv95qLjtjyuw+nv2SNWQ== X-Received: by 2002:ac8:410f:: with SMTP id q15mr61226584qtl.192.1577999645574; Thu, 02 Jan 2020 13:14:05 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id f97sm17384185qtb.18.2020.01.02.13.14.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2020 13:14:04 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Thu, 2 Jan 2020 16:13:54 -0500 Message-Id: <20200102211357.8042-4-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200102211357.8042-1-pasha.tatashin@soleen.com> References: <20200102211357.8042-1-pasha.tatashin@soleen.com> Subject: [Xen-devel] [PATCH v5 3/6] arm64: remove uaccess_ttbr0 asm macros from cache functions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" We currently duplicate the logic to enable/disable uaccess via TTBR0, with C functions and assembly macros. This is a maintenenace burden and is liable to lead to subtle bugs, so let's get rid of the assembly macros, and always use the C functions. This requires refactoring some assembly functions to have a C wrapper. Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/asm-uaccess.h | 22 ---------------- arch/arm64/include/asm/cacheflush.h | 39 +++++++++++++++++++++++++--- arch/arm64/mm/cache.S | 36 ++++++++++--------------- arch/arm64/mm/flush.c | 2 +- 4 files changed, 50 insertions(+), 49 deletions(-) diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h index f68a0e64482a..fba2a69f7fef 100644 --- a/arch/arm64/include/asm/asm-uaccess.h +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -34,28 +34,6 @@ msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 isb .endm - - .macro uaccess_ttbr0_disable, tmp1, tmp2 -alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp2 // avoid preemption - __uaccess_ttbr0_disable \tmp1 - restore_irq \tmp2 -alternative_else_nop_endif - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 -alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp3 // avoid preemption - __uaccess_ttbr0_enable \tmp1, \tmp2 - restore_irq \tmp3 -alternative_else_nop_endif - .endm -#else - .macro uaccess_ttbr0_disable, tmp1, tmp2 - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 - .endm #endif #endif diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index 665c78e0665a..cb00c61e0bde 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -61,16 +61,49 @@ * - kaddr - page address * - size - region size */ -extern void __flush_icache_range(unsigned long start, unsigned long end); -extern int invalidate_icache_range(unsigned long start, unsigned long end); +extern void __asm_flush_icache_range(unsigned long start, unsigned long end); +extern long __asm_flush_cache_user_range(unsigned long start, + unsigned long end); +extern int __asm_invalidate_icache_range(unsigned long start, + unsigned long end); extern void __flush_dcache_area(void *addr, size_t len); extern void __inval_dcache_area(void *addr, size_t len); extern void __clean_dcache_area_poc(void *addr, size_t len); extern void __clean_dcache_area_pop(void *addr, size_t len); extern void __clean_dcache_area_pou(void *addr, size_t len); -extern long __flush_cache_user_range(unsigned long start, unsigned long end); extern void sync_icache_aliases(void *kaddr, unsigned long len); +static inline long __flush_cache_user_range(unsigned long start, + unsigned long end) +{ + int ret; + + uaccess_ttbr0_enable(); + ret = __asm_flush_cache_user_range(start, end); + uaccess_ttbr0_disable(); + + return ret; +} + +static inline void __flush_icache_range(unsigned long start, unsigned long end) +{ + uaccess_ttbr0_enable(); + __asm_flush_icache_range(start, end); + uaccess_ttbr0_disable(); +} + +static inline int invalidate_icache_range(unsigned long start, + unsigned long end) +{ + int ret; + + uaccess_ttbr0_enable(); + ret = __asm_invalidate_icache_range(start, end); + uaccess_ttbr0_disable(); + + return ret; +} + static inline void flush_icache_range(unsigned long start, unsigned long end) { __flush_icache_range(start, end); diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index db767b072601..602b9aa8603a 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -15,7 +15,7 @@ #include /* - * flush_icache_range(start,end) + * __asm_flush_icache_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, @@ -24,11 +24,11 @@ * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(__flush_icache_range) +ENTRY(__asm_flush_icache_range) /* FALLTHROUGH */ /* - * __flush_cache_user_range(start,end) + * __asm_flush_cache_user_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, @@ -37,8 +37,7 @@ ENTRY(__flush_icache_range) * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(__flush_cache_user_range) - uaccess_ttbr0_enable x2, x3, x4 +ENTRY(__asm_flush_cache_user_range) alternative_if ARM64_HAS_CACHE_IDC dsb ishst b 7f @@ -60,41 +59,32 @@ alternative_if ARM64_HAS_CACHE_DIC alternative_else_nop_endif invalidate_icache_by_line x0, x1, x2, x3, 9f 8: mov x0, #0 -1: - uaccess_ttbr0_disable x1, x2 - ret -9: - mov x0, #-EFAULT +1: ret +9: mov x0, #-EFAULT b 1b -ENDPROC(__flush_icache_range) -ENDPROC(__flush_cache_user_range) +ENDPROC(__asm_flush_icache_range) +ENDPROC(__asm_flush_cache_user_range) /* - * invalidate_icache_range(start,end) + * __asm_invalidate_icache_range(start,end) * * Ensure that the I cache is invalid within specified region. * * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(invalidate_icache_range) +ENTRY(__asm_invalidate_icache_range) alternative_if ARM64_HAS_CACHE_DIC mov x0, xzr isb ret alternative_else_nop_endif - - uaccess_ttbr0_enable x2, x3, x4 - invalidate_icache_by_line x0, x1, x2, x3, 2f mov x0, xzr -1: - uaccess_ttbr0_disable x1, x2 - ret -2: - mov x0, #-EFAULT +1: ret +2: mov x0, #-EFAULT b 1b -ENDPROC(invalidate_icache_range) +ENDPROC(__asm_invalidate_icache_range) /* * __flush_dcache_area(kaddr, size) diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index ac485163a4a7..b23f34d23f31 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -75,7 +75,7 @@ EXPORT_SYMBOL(flush_dcache_page); /* * Additional functions defined in assembly. */ -EXPORT_SYMBOL(__flush_icache_range); +EXPORT_SYMBOL(__asm_flush_icache_range); #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size) From patchwork Thu Jan 2 21:13:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11316049 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F2FB930 for ; Thu, 2 Jan 2020 21:15:21 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6B43321582 for ; Thu, 2 Jan 2020 21:15:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="OrYEDSt9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6B43321582 Authentication-Results: mail.kernel.org; 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[73.69.118.222]) by smtp.gmail.com with ESMTPSA id f97sm17384185qtb.18.2020.01.02.13.14.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2020 13:14:06 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Thu, 2 Jan 2020 16:13:55 -0500 Message-Id: <20200102211357.8042-5-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200102211357.8042-1-pasha.tatashin@soleen.com> References: <20200102211357.8042-1-pasha.tatashin@soleen.com> Subject: [Xen-devel] [PATCH v5 4/6] arm64: remove __asm_flush_icache_range X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" __asm_flush_icache_range is an alias to __asm_flush_cache_user_range, but now that these functions are called from C wrappers the fall through can instead be done at a higher level. Remove the __asm_flush_icache_range alias in assembly, and instead call __flush_cache_user_range() from __flush_icache_range(). Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/cacheflush.h | 5 +---- arch/arm64/mm/cache.S | 14 -------------- arch/arm64/mm/flush.c | 2 +- 3 files changed, 2 insertions(+), 19 deletions(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index cb00c61e0bde..047af338ba15 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -61,7 +61,6 @@ * - kaddr - page address * - size - region size */ -extern void __asm_flush_icache_range(unsigned long start, unsigned long end); extern long __asm_flush_cache_user_range(unsigned long start, unsigned long end); extern int __asm_invalidate_icache_range(unsigned long start, @@ -87,9 +86,7 @@ static inline long __flush_cache_user_range(unsigned long start, static inline void __flush_icache_range(unsigned long start, unsigned long end) { - uaccess_ttbr0_enable(); - __asm_flush_icache_range(start, end); - uaccess_ttbr0_disable(); + __flush_cache_user_range(start, end); } static inline int invalidate_icache_range(unsigned long start, diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 602b9aa8603a..1981cbaf5d92 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -14,19 +14,6 @@ #include #include -/* - * __asm_flush_icache_range(start,end) - * - * Ensure that the I and D caches are coherent within specified region. - * This is typically used when code has been written to a memory region, - * and will be executed. - * - * - start - virtual start address of region - * - end - virtual end address of region - */ -ENTRY(__asm_flush_icache_range) - /* FALLTHROUGH */ - /* * __asm_flush_cache_user_range(start,end) * @@ -62,7 +49,6 @@ alternative_else_nop_endif 1: ret 9: mov x0, #-EFAULT b 1b -ENDPROC(__asm_flush_icache_range) ENDPROC(__asm_flush_cache_user_range) /* diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index b23f34d23f31..61521285f27d 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -75,7 +75,7 @@ EXPORT_SYMBOL(flush_dcache_page); /* * Additional functions defined in assembly. */ -EXPORT_SYMBOL(__asm_flush_icache_range); +EXPORT_SYMBOL(__asm_flush_cache_user_range); #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size) From patchwork Thu Jan 2 21:13:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11316057 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1398930 for ; Thu, 2 Jan 2020 21:15:26 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BD78121582 for ; Thu, 2 Jan 2020 21:15:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="XMSSOxhT" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BD78121582 Authentication-Results: mail.kernel.org; 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[73.69.118.222]) by smtp.gmail.com with ESMTPSA id f97sm17384185qtb.18.2020.01.02.13.14.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2020 13:14:08 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Thu, 2 Jan 2020 16:13:56 -0500 Message-Id: <20200102211357.8042-6-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200102211357.8042-1-pasha.tatashin@soleen.com> References: <20200102211357.8042-1-pasha.tatashin@soleen.com> Subject: [Xen-devel] [PATCH v5 5/6] arm64: move ARM64_HAS_CACHE_DIC/_IDC from asm to C X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The assmbly functions __asm_flush_cache_user_range and __asm_invalidate_icache_range have alternatives: alternative_if ARM64_HAS_CACHE_DIC ... alternative_if ARM64_HAS_CACHE_IDC ... But, the implementation of those alternatives is trivial and therefore can be done in the C inline wrappers. Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/cacheflush.h | 19 +++++++++++++++++++ arch/arm64/mm/cache.S | 27 +++++---------------------- arch/arm64/mm/flush.c | 1 + 3 files changed, 25 insertions(+), 22 deletions(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index 047af338ba15..fc5217a18398 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -77,8 +77,22 @@ static inline long __flush_cache_user_range(unsigned long start, { int ret; + if (cpus_have_const_cap(ARM64_HAS_CACHE_IDC)) { + dsb(ishst); + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) { + isb(); + return 0; + } + } + uaccess_ttbr0_enable(); ret = __asm_flush_cache_user_range(start, end); + + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) + isb(); + else + __asm_invalidate_icache_range(start, end); + uaccess_ttbr0_disable(); return ret; @@ -94,6 +108,11 @@ static inline int invalidate_icache_range(unsigned long start, { int ret; + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) { + isb(); + return 0; + } + uaccess_ttbr0_enable(); ret = __asm_invalidate_icache_range(start, end); uaccess_ttbr0_disable(); diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 1981cbaf5d92..0093bb9fcd12 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -25,30 +25,18 @@ * - end - virtual end address of region */ ENTRY(__asm_flush_cache_user_range) -alternative_if ARM64_HAS_CACHE_IDC - dsb ishst - b 7f -alternative_else_nop_endif dcache_line_size x2, x3 sub x3, x2, #1 bic x4, x0, x3 -1: -user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE +1: user_alt 3f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE add x4, x4, x2 cmp x4, x1 b.lo 1b dsb ish - -7: -alternative_if ARM64_HAS_CACHE_DIC - isb - b 8f -alternative_else_nop_endif - invalidate_icache_by_line x0, x1, x2, x3, 9f -8: mov x0, #0 -1: ret -9: mov x0, #-EFAULT - b 1b + mov x0, #0 +2: ret +3: mov x0, #-EFAULT + b 2b ENDPROC(__asm_flush_cache_user_range) /* @@ -60,11 +48,6 @@ ENDPROC(__asm_flush_cache_user_range) * - end - virtual end address of region */ ENTRY(__asm_invalidate_icache_range) -alternative_if ARM64_HAS_CACHE_DIC - mov x0, xzr - isb - ret -alternative_else_nop_endif invalidate_icache_by_line x0, x1, x2, x3, 2f mov x0, xzr 1: ret diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index 61521285f27d..adfdacb163ad 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -76,6 +76,7 @@ EXPORT_SYMBOL(flush_dcache_page); * Additional functions defined in assembly. */ EXPORT_SYMBOL(__asm_flush_cache_user_range); +EXPORT_SYMBOL(__asm_invalidate_icache_range); #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size) From patchwork Thu Jan 2 21:13:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11316055 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 602BB138C for ; Thu, 2 Jan 2020 21:15:26 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 383D421582 for ; Thu, 2 Jan 2020 21:15:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="o3ZObMYh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 383D421582 Authentication-Results: mail.kernel.org; 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[73.69.118.222]) by smtp.gmail.com with ESMTPSA id f97sm17384185qtb.18.2020.01.02.13.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2020 13:14:10 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Thu, 2 Jan 2020 16:13:57 -0500 Message-Id: <20200102211357.8042-7-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200102211357.8042-1-pasha.tatashin@soleen.com> References: <20200102211357.8042-1-pasha.tatashin@soleen.com> Subject: [Xen-devel] [PATCH v5 6/6] arm64: remove the rest of asm-uaccess.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The __uaccess_ttbr0_disable and __uaccess_ttbr0_enable, are the last two macros defined in asm-uaccess.h. For now move them to entry.S where they are used. Eventually, these macros should be replaced with C wrappers to reduce the maintenance burden. Also, once these macros are unified with the C counterparts, it is a good idea to check that PAN is in correct state on every enable/disable calls. Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/asm-uaccess.h | 39 ---------------------------- arch/arm64/kernel/entry.S | 27 ++++++++++++++++++- arch/arm64/lib/clear_user.S | 2 +- arch/arm64/lib/copy_from_user.S | 2 +- arch/arm64/lib/copy_in_user.S | 2 +- arch/arm64/lib/copy_to_user.S | 2 +- arch/arm64/mm/cache.S | 1 - 7 files changed, 30 insertions(+), 45 deletions(-) delete mode 100644 arch/arm64/include/asm/asm-uaccess.h diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h deleted file mode 100644 index fba2a69f7fef..000000000000 --- a/arch/arm64/include/asm/asm-uaccess.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ASM_UACCESS_H -#define __ASM_ASM_UACCESS_H - -#include -#include -#include -#include -#include - -/* - * User access enabling/disabling macros. - */ -#ifdef CONFIG_ARM64_SW_TTBR0_PAN - .macro __uaccess_ttbr0_disable, tmp1 - mrs \tmp1, ttbr1_el1 // swapper_pg_dir - bic \tmp1, \tmp1, #TTBR_ASID_MASK - sub \tmp1, \tmp1, #RESERVED_TTBR0_SIZE // reserved_ttbr0 just before swapper_pg_dir - msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 - isb - add \tmp1, \tmp1, #RESERVED_TTBR0_SIZE - msr ttbr1_el1, \tmp1 // set reserved ASID - isb - .endm - - .macro __uaccess_ttbr0_enable, tmp1, tmp2 - get_current_task \tmp1 - ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 - mrs \tmp2, ttbr1_el1 - extr \tmp2, \tmp2, \tmp1, #48 - ror \tmp2, \tmp2, #16 - msr ttbr1_el1, \tmp2 // set the active ASID - isb - msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 - isb - .endm -#endif - -#endif diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 7c6a0a41676f..cc6c0dbb7734 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -22,8 +22,8 @@ #include #include #include +#include #include -#include #include /* @@ -144,6 +144,31 @@ alternative_cb_end #endif .endm +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + .macro __uaccess_ttbr0_disable, tmp1 + mrs \tmp1, ttbr1_el1 // swapper_pg_dir + bic \tmp1, \tmp1, #TTBR_ASID_MASK + sub \tmp1, \tmp1, #RESERVED_TTBR0_SIZE // reserved_ttbr0 just before swapper_pg_dir + msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 + isb + add \tmp1, \tmp1, #RESERVED_TTBR0_SIZE + msr ttbr1_el1, \tmp1 // set reserved ASID + isb + .endm + + .macro __uaccess_ttbr0_enable, tmp1, tmp2 + get_current_task \tmp1 + ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 + mrs \tmp2, ttbr1_el1 + extr \tmp2, \tmp2, \tmp1, #48 + ror \tmp2, \tmp2, #16 + msr ttbr1_el1, \tmp2 // set the active ASID + isb + msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 + isb + .endm +#endif + .macro kernel_entry, el, regsize = 64 .if \regsize == 32 mov w0, w0 // zero upper 32 bits of x0 diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S index aeafc03e961a..b0b4a86a09e2 100644 --- a/arch/arm64/lib/clear_user.S +++ b/arch/arm64/lib/clear_user.S @@ -6,7 +6,7 @@ */ #include -#include +#include #include .text diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S index ebb3c06cbb5d..142bc7505518 100644 --- a/arch/arm64/lib/copy_from_user.S +++ b/arch/arm64/lib/copy_from_user.S @@ -5,7 +5,7 @@ #include -#include +#include #include #include diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S index 3d8153a1ebce..04dc48ca26f7 100644 --- a/arch/arm64/lib/copy_in_user.S +++ b/arch/arm64/lib/copy_in_user.S @@ -7,7 +7,7 @@ #include -#include +#include #include #include diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S index 357eae2c18eb..8f3218ae88ab 100644 --- a/arch/arm64/lib/copy_to_user.S +++ b/arch/arm64/lib/copy_to_user.S @@ -5,7 +5,7 @@ #include -#include +#include #include #include diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 0093bb9fcd12..627be857b8d0 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -12,7 +12,6 @@ #include #include #include -#include /* * __asm_flush_cache_user_range(start,end)