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[92.133.126.221]) by smtp.gmail.com with ESMTPSA id a184sm1453539wmf.29.2020.01.10.00.54.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Jan 2020 00:54:59 -0800 (PST) From: Loic Poulain To: agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, Loic Poulain Subject: [PATCH] tty: serial: msm_serial: RX SW/FIFO mode fallback Date: Fri, 10 Jan 2020 09:58:04 +0100 Message-Id: <1578646684-17379-1-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org During db410c stress test and when the system is low on memory, the UART/console becomes unresponsive and never recover back. This has been narrowed down to the msm_start_rx_dma which does not manage error cases correctly (e.g. dma mapping failure), indeed, when an error happens, dma transfer is simply discarded and so never completed, leading to unconfigured RX path. This patch fixes this issue by switching to SW/FIFO mode in case of DMA issue. This mainly consists in resetting the receiver to apply RX BAM/DMA disabling change and re-enabling the RX level and stale interrupts (previously disabled for DMA transfers). The DMA will be re-enabled once memory is available since the SW/FIFO read function (msm_handle_rx_dm) retries to start dma on completion. Signed-off-by: Loic Poulain --- drivers/tty/serial/msm_serial.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c index 1cbae07..a63b703 100644 --- a/drivers/tty/serial/msm_serial.c +++ b/drivers/tty/serial/msm_serial.c @@ -610,7 +610,7 @@ static void msm_start_rx_dma(struct msm_port *msm_port) UARTDM_RX_SIZE, dma->dir); ret = dma_mapping_error(uart->dev, dma->phys); if (ret) - return; + goto sw_mode; dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, UARTDM_RX_SIZE, DMA_DEV_TO_MEM, @@ -661,6 +661,22 @@ static void msm_start_rx_dma(struct msm_port *msm_port) return; unmap: dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); + +sw_mode: + /* + * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN), + * receiver must be reset. + */ + msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR); + msm_write(uart, UART_CR_RX_ENABLE, UART_CR); + + msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR); + msm_write(uart, 0xFFFFFF, UARTDM_DMRX); + msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); + + /* Re-enable RX interrupts */ + msm_port->imr |= (UART_IMR_RXLEV | UART_IMR_RXSTALE); + msm_write(uart, msm_port->imr, UART_IMR); } static void msm_stop_rx(struct uart_port *port)