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Fri, 10 Jan 2020 08:05:23 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2601D1FF87; Fri, 10 Jan 2020 16:05:23 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: pbonzini@redhat.com Subject: [kvm-unit-tests PATCH] arm: expand the timer tests Date: Fri, 10 Jan 2020 16:05:11 +0000 Message-Id: <20200110160511.17821-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200110_080528_960663_3B0BF9AB X-CRM114-Status: GOOD ( 10.38 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, maz@kernel.org, christoffer.dall@arm.com, =?utf-8?q?Alex_Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This was an attempt to replicate a QEMU bug. However to trigger the bug you need to have an offset set in EL2 which kvm-unit-tests is unable to do. However it does exercise some more corner cases. Bug: https://bugs.launchpad.net/bugs/1859021 Signed-off-by: Alex Bennée --- arm/timer.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arm/timer.c b/arm/timer.c index f390e8e..ae1d299 100644 --- a/arm/timer.c +++ b/arm/timer.c @@ -214,21 +214,46 @@ static void test_timer(struct timer_info *info) * still read the pending state even if it's disabled. */ set_timer_irq_enabled(info, false); + /* Verify count goes up */ + report(info->read_counter() >= now, "counter increments"); + /* Enable the timer, but schedule it for much later */ info->write_cval(later); info->write_ctl(ARCH_TIMER_CTL_ENABLE); isb(); - report(!gic_timer_pending(info), "not pending before"); + report(!gic_timer_pending(info), "not pending before 10s"); + + /* Check with a maximum possible cval */ + info->write_cval(UINT64_MAX); + isb(); + report(!gic_timer_pending(info), "not pending before UINT64_MAX"); + + /* also by setting tval */ + info->write_tval(time_10s); + isb(); + report(!gic_timer_pending(info), "not pending before 10s (via tval)"); + report_info("TVAL is %d (delta CVAL %ld) ticks", + info->read_tval(), info->read_cval() - info->read_counter()); + /* check pending once cval is before now */ info->write_cval(now - 1); isb(); report(gic_timer_pending(info), "interrupt signal pending"); + report_info("TVAL is %d ticks", info->read_tval()); /* Disable the timer again and prepare to take interrupts */ info->write_ctl(0); set_timer_irq_enabled(info, true); report(!gic_timer_pending(info), "interrupt signal no longer pending"); + /* QEMU bug when cntvoff_el2 > 0 + * https://bugs.launchpad.net/bugs/1859021 */ + info->write_ctl(ARCH_TIMER_CTL_ENABLE); + info->write_cval(UINT64_MAX); + isb(); + report(!gic_timer_pending(info), "not pending before UINT64_MAX (irqs on)"); + info->write_ctl(0); + report(test_cval_10msec(info), "latency within 10 ms"); report(info->irq_received, "interrupt received");