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[222.224.164.52]) by smtp.gmail.com with ESMTPSA id u1sm3844581pfn.133.2020.01.10.13.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jan 2020 13:28:56 -0800 (PST) From: Stafford Horne To: shorne@gmail.com Subject: [PATCH] target/openrisc: Fix FPCSR mask to allow setting DZF Date: Sat, 11 Jan 2020 06:28:43 +0900 Message-Id: <20200110212843.27335-1-shorne@gmail.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Openrisc , QEMU Development , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The mask used when setting FPCSR allows setting bits 10 to 1. However, OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero Flag (DZF). This seems like an off-by-one bug. This was found when testing the GLIBC test suite which has test cases to set and clear all bits. Signed-off-by: Stafford Horne --- target/openrisc/fpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 59e1413279..6f75ea0505 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -70,7 +70,7 @@ void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val) float_round_down }; - env->fpcsr = val & 0x7ff; + env->fpcsr = val & 0xfff; set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], &env->fp_status); }