From patchwork Mon Jan 13 10:14:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329879 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 060276C1 for ; Mon, 13 Jan 2020 10:15:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D88A121739 for ; Mon, 13 Jan 2020 10:15:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="h/SuUs9Y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725978AbgAMKPY (ORCPT ); Mon, 13 Jan 2020 05:15:24 -0500 Received: from forward105p.mail.yandex.net ([77.88.28.108]:56124 "EHLO forward105p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725992AbgAMKPY (ORCPT ); Mon, 13 Jan 2020 05:15:24 -0500 Received: from mxback6j.mail.yandex.net (mxback6j.mail.yandex.net [IPv6:2a02:6b8:0:1619::10f]) by forward105p.mail.yandex.net (Yandex) with ESMTP id 0AE774D41389; Mon, 13 Jan 2020 13:15:21 +0300 (MSK) Received: from myt4-ee976ce519ac.qloud-c.yandex.net (myt4-ee976ce519ac.qloud-c.yandex.net [2a02:6b8:c00:1da4:0:640:ee97:6ce5]) by mxback6j.mail.yandex.net (mxback/Yandex) with ESMTP id sDXEVUDOTj-FK50ht9Q; Mon, 13 Jan 2020 13:15:21 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578910521; bh=SmZj3mYxPN02iCgwmcokvO3bplgROVcs4GPwKV2RwOE=; h=Subject:To:From:Cc:Date:Message-Id; b=h/SuUs9YevoVdhD5o6oTtoRlH9z9DsNQqIbJp9u+S0MYcq8QoDGW90dbl5QRnxdPY 29r+GjuQkFw/SbXGMY5QdKCuXnIVDOORfnYl5MMgej/YFy7V1zf85FJCZN3VxeO5WO 3+kSF6p31dCUEud3B+0aVxFGAPmSsNXLVsLwNtPo= Authentication-Results: mxback6j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by myt4-ee976ce519ac.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 2dzM4Y3ZVr-FGWK30Uk; Mon, 13 Jan 2020 13:15:19 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, linux-kernel@vger.kernel.org, Jiaxun Yang Subject: [PATCH 1/3] MIPS: Make DIEI support as a config option Date: Mon, 13 Jan 2020 18:14:59 +0800 Message-Id: <20200113101501.37985-1-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org DI(Disable Interrupt) and EI(Enable Interrupt) instructions is required by MIPSR2/MIPSR6, however, it appears to be buggy on some processors such as Loongson-3A1000. Thus we make it as a config option to allow disable it at compile time with CPU_MIPSR2 selected. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 9 +++++++++ arch/mips/include/asm/irqflags.h | 6 +++--- arch/mips/lib/mips-atomic.c | 4 ++-- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4b83507499f4..c3103f4eeafa 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2111,12 +2111,14 @@ config CPU_MIPSR2 bool default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON select CPU_HAS_RIXI + select CPU_HAS_DIEI if !CPU_DIEI_BROKEN select MIPS_SPRAM config CPU_MIPSR6 bool default y if CPU_MIPS32_R6 || CPU_MIPS64_R6 select CPU_HAS_RIXI + select CPU_HAS_DIEI if !CPU_DIEI_BROKEN select HAVE_ARCH_BITREVERSE select MIPS_ASID_BITS_VARIABLE select MIPS_CRC_SUPPORT @@ -2579,6 +2581,13 @@ config XKS01 config CPU_HAS_RIXI bool +config CPU_HAS_DIEI + depends on !CPU_DIEI_BROKEN + bool + +config CPU_DIEI_BROKEN + bool + config CPU_HAS_LOAD_STORE_LR bool help diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h index c4728bbdf15b..47a8ffc0b413 100644 --- a/arch/mips/include/asm/irqflags.h +++ b/arch/mips/include/asm/irqflags.h @@ -18,7 +18,7 @@ #include #include -#if defined(CONFIG_CPU_MIPSR2) || defined (CONFIG_CPU_MIPSR6) +#if defined(CONFIG_CPU_HAS_DIEI) static inline void arch_local_irq_disable(void) { @@ -94,7 +94,7 @@ static inline void arch_local_irq_restore(unsigned long flags) void arch_local_irq_disable(void); unsigned long arch_local_irq_save(void); void arch_local_irq_restore(unsigned long flags); -#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */ +#endif /* CONFIG_CPU_HAS_DIEI */ static inline void arch_local_irq_enable(void) { @@ -102,7 +102,7 @@ static inline void arch_local_irq_enable(void) " .set push \n" " .set reorder \n" " .set noat \n" -#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) +#if defined(CONFIG_CPU_HAS_DIEI) " ei \n" #else " mfc0 $1,$12 \n" diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c index 5530070e0d05..de03838b343b 100644 --- a/arch/mips/lib/mips-atomic.c +++ b/arch/mips/lib/mips-atomic.c @@ -15,7 +15,7 @@ #include #include -#if !defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_MIPSR6) +#if !defined(CONFIG_CPU_HAS_DIEI) /* * For cli() we have to insert nops to make sure that the new value @@ -110,4 +110,4 @@ notrace void arch_local_irq_restore(unsigned long flags) } EXPORT_SYMBOL(arch_local_irq_restore); -#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR6 */ +#endif /* !CONFIG_CPU_HAS_DIEI */ From patchwork Mon Jan 13 10:15:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329881 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 657806C1 for ; Mon, 13 Jan 2020 10:15:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 430962084D for ; Mon, 13 Jan 2020 10:15:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="ZVwk3M7w" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726946AbgAMKPb (ORCPT ); Mon, 13 Jan 2020 05:15:31 -0500 Received: from forward104p.mail.yandex.net ([77.88.28.107]:45089 "EHLO forward104p.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725992AbgAMKPb (ORCPT ); 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Mon, 13 Jan 2020 13:15:26 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, linux-kernel@vger.kernel.org, Jiaxun Yang Subject: [PATCH 2/3] MIPS: Loongson64: Bump ISA level to MIPSR2 Date: Mon, 13 Jan 2020 18:15:00 +0800 Message-Id: <20200113101501.37985-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200113101501.37985-1-jiaxun.yang@flygoat.com> References: <20200113101501.37985-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Despite early sample of Loongson-3A1000, the whole Loongson64 family have implemented all the features required by MIPS64 Release2. Thus we decide to bump the ISA option to R2. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 6 ++++-- arch/mips/include/asm/hazards.h | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c3103f4eeafa..d0b727daddb3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1443,11 +1443,15 @@ config CPU_LOONGSON64 bool "Loongson 64-bit CPU" depends on SYS_HAS_CPU_LOONGSON64 select ARCH_HAS_PHYS_TO_DMA + select CPU_MIPSR2 + select CPU_HAS_PREFETCH select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES select CPU_SUPPORTS_MSA select CPU_HAS_LOAD_STORE_LR + select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT + select CPU_MIPSR2_IRQ_VI select WEAK_ORDERING select WEAK_REORDERING_BEYOND_LLSC select MIPS_ASID_BITS_VARIABLE @@ -1465,8 +1469,6 @@ config CPU_LOONGSON64 config LOONGSON3_ENHANCEMENT bool "New Loongson-3 CPU Enhancements" default n - select CPU_MIPSR2 - select CPU_HAS_PREFETCH depends on CPU_LOONGSON64 help New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index a4f48b0f5541..a0b92205f933 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -23,7 +23,7 @@ * TLB hazards */ #if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \ - !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT) + !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64) /* * MIPSR2 defines ehb for hazard avoidance @@ -158,7 +158,7 @@ do { \ } while (0) #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ - defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \ + defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \ defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR) /* From patchwork Mon Jan 13 10:15:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 11329885 X-Patchwork-Delegate: paulburton@kernel.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5107E921 for ; Mon, 13 Jan 2020 10:15:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2FBA02084D for ; Mon, 13 Jan 2020 10:15:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="wjHzoUKt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728670AbgAMKPi (ORCPT ); Mon, 13 Jan 2020 05:15:38 -0500 Received: from forward100o.mail.yandex.net ([37.140.190.180]:49762 "EHLO forward100o.mail.yandex.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725992AbgAMKPi (ORCPT ); Mon, 13 Jan 2020 05:15:38 -0500 Received: from mxback7j.mail.yandex.net (mxback7j.mail.yandex.net [IPv6:2a02:6b8:0:1619::110]) by forward100o.mail.yandex.net (Yandex) with ESMTP id AB8EB4AC1730; Mon, 13 Jan 2020 13:15:35 +0300 (MSK) Received: from myt4-ee976ce519ac.qloud-c.yandex.net (myt4-ee976ce519ac.qloud-c.yandex.net [2a02:6b8:c00:1da4:0:640:ee97:6ce5]) by mxback7j.mail.yandex.net (mxback/Yandex) with ESMTP id ZDulr1oRqN-FZkakkFO; Mon, 13 Jan 2020 13:15:35 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; s=mail; t=1578910535; bh=YfizjYxlV5Q/zSWO3Voct7ZQ0gYO9260ZL6PffmuiVE=; h=In-Reply-To:Subject:To:From:Cc:References:Date:Message-Id; b=wjHzoUKt+rd/shkJKNGuyonVWE1xqnOn90pFBYiO6tW/SeIqCn4k7hKyjdTpcyPvy aXaTqLRdTG4SkqA7Cw8uvzzxulawMCwLpVlggFx2lJ4fXBKWiu6ucDENvQemQpAEnG KingDql5PY7DSPjf6NYkZ22sZkNyrxXH6ee3zQtY= Authentication-Results: mxback7j.mail.yandex.net; dkim=pass header.i=@flygoat.com Received: by myt4-ee976ce519ac.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id 2dzM4Y3ZVr-FTWKjnf0; Mon, 13 Jan 2020 13:15:32 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: chenhc@lemote.com, paul.burton@mips.com, linux-kernel@vger.kernel.org, Jiaxun Yang Subject: [PATCH 3/3] MIPS: Loongson64: Disable exec hazard Date: Mon, 13 Jan 2020 18:15:01 +0800 Message-Id: <20200113101501.37985-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200113101501.37985-1-jiaxun.yang@flygoat.com> References: <20200113101501.37985-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Loongson64 has hardware mechanism to prevent hazard issue, so we can simply disable exec hazard in cpu-features. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h index 7dc8d75445a9..23aa8ed7cb9e 100644 --- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h @@ -46,5 +46,6 @@ #define cpu_has_wsbh 1 #define cpu_has_ic_fills_f_dc 1 #define cpu_hwrena_impl_bits 0xc0000000 +#define cpu_has_mips_r2_exec_hazard 0 #endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */