From patchwork Sun Jan 19 13:30:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zenghui Yu X-Patchwork-Id: 11340685 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A85614B4 for ; Sun, 19 Jan 2020 13:33:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1467B20663 for ; Sun, 19 Jan 2020 13:33:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1467B20663 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1itAhx-0003qW-6D for patchwork-qemu-devel@patchwork.kernel.org; Sun, 19 Jan 2020 08:33:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33577) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1itAgy-0003J2-DS for qemu-devel@nongnu.org; Sun, 19 Jan 2020 08:32:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1itAgx-0007zE-Ai for qemu-devel@nongnu.org; Sun, 19 Jan 2020 08:32:40 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2688 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1itAgu-0007uI-Hl; Sun, 19 Jan 2020 08:32:36 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 0BB7FE69CDB940A01276; Sun, 19 Jan 2020 21:32:27 +0800 (CST) Received: from DESKTOP-8RFUVS3.china.huawei.com (10.173.222.27) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Sun, 19 Jan 2020 21:32:17 +0800 From: Zenghui Yu To: , , Subject: [PATCH] hw/intc/arm_gicv3_kvm: Stop wrongly programming GICR_PENDBASER.PTZ bit Date: Sun, 19 Jan 2020 21:30:51 +0800 Message-ID: <20200119133051.642-1-yuzenghui@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zenghui Yu , maz@kernel.org, kvmarm@lists.cs.columbia.edu, wanghaibin.wang@huawei.com, eric.auger@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" If LPIs are disabled, KVM will just ignore the GICR_PENDBASER.PTZ bit when restoring GICR_CTLR. Setting PTZ here makes littlt sense in "reduce GIC initialization time". And what's worse, PTZ is generally programmed by guest to indicate to the Redistributor whether the LPI Pending table is zero when enabling LPIs. If migration is triggered when the PTZ has just been cleared by guest (and before enabling LPIs), we will see PTZ==1 on the destination side, which is not as expected. Let's just drop this hackish userspace behavior. Also take this chance to refine the comment a bit. Fixes: 367b9f527bec ("hw/intc/arm_gicv3_kvm: Implement get/put functions") Signed-off-by: Zenghui Yu --- hw/intc/arm_gicv3_kvm.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 9c7f4ab871..49304ca589 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -336,7 +336,10 @@ static void kvm_arm_gicv3_put(GICv3State *s) kvm_gicd_access(s, GICD_CTLR, ®, true); if (redist_typer & GICR_TYPER_PLPIS) { - /* Set base addresses before LPIs are enabled by GICR_CTLR write */ + /* + * Restore base addresses before LPIs are potentially enabled by + * GICR_CTLR write + */ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { GICv3CPUState *c = &s->cpu[ncpu]; @@ -347,12 +350,6 @@ static void kvm_arm_gicv3_put(GICv3State *s) kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); reg64 = c->gicr_pendbaser; - if (!(c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { - /* Setting PTZ is advised if LPIs are disabled, to reduce - * GIC initialization time. - */ - reg64 |= GICR_PENDBASER_PTZ; - } regl = (uint32_t)reg64; kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); regh = (uint32_t)(reg64 >> 32);