From patchwork Tue Jan 28 22:16:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 11355279 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C2CAB13A4 for ; Tue, 28 Jan 2020 22:16:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9660F21739 for ; Tue, 28 Jan 2020 22:16:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="NLdGMSlW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726293AbgA1WQY (ORCPT ); Tue, 28 Jan 2020 17:16:24 -0500 Received: from mail25.static.mailgun.info ([104.130.122.25]:27282 "EHLO mail25.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726257AbgA1WQY (ORCPT ); Tue, 28 Jan 2020 17:16:24 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1580249783; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=FXsf/z/1DeoIKgsAIM/dfI6zvYtWCIvxuwhvpm/1k8o=; b=NLdGMSlWVAD6PMFvwgOQ8GP80ZYxTgLvqMbb/k4IcV/BtJEXgTnRzxTqwzdcT5/q6iu2Q2K/ S/TOm5UwvYcRHBlC3athb+7fp5Uejsj07itjviOdOhgVDSC650xfkpsHGrGsf+1Ge1dS3HMB tlYM2+y8rbHeOIDREcZoTmsb6Vk= X-Mailgun-Sending-Ip: 104.130.122.25 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e30b2b3.7f907e9094c8-smtp-out-n03; Tue, 28 Jan 2020 22:16:19 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 56309C4479F; Tue, 28 Jan 2020 22:16:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 29111C433A2; Tue, 28 Jan 2020 22:16:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 29111C433A2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: iommu@lists.linux-foundation.org Cc: robin.murphy@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Joerg Roedel , linux-kernel@vger.kernel.org Subject: [PATCH v1 1/6] iommu: Add DOMAIN_ATTR_PTBASE Date: Tue, 28 Jan 2020 15:16:05 -0700 Message-Id: <1580249770-1088-2-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> References: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add an attribute to return the base address of the pagetable. This is used by auxiliary domains from arm-smmu to return the address of the pagetable to the domain so that it can set the appropriate pagetable through it's own means. Signed-off-by: Jordan Crouse --- include/linux/iommu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index b14398b..0e9bcd9 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -128,6 +128,8 @@ enum iommu_attr { DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, /* Enable split pagetables (for example, TTBR1 on arm-smmu) */ DOMAIN_ATTR_SPLIT_TABLES, + /* Return the pagetable base address */ + DOMAIN_ATTR_PTBASE, DOMAIN_ATTR_MAX, }; From patchwork Tue Jan 28 22:16:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 11355285 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7FFFA13A4 for ; Tue, 28 Jan 2020 22:16:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 49AFE2173E for ; Tue, 28 Jan 2020 22:16:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="roBkL/Jq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726524AbgA1WQ1 (ORCPT ); Tue, 28 Jan 2020 17:16:27 -0500 Received: from mail25.static.mailgun.info ([104.130.122.25]:30054 "EHLO mail25.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726428AbgA1WQ0 (ORCPT ); Tue, 28 Jan 2020 17:16:26 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1580249785; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=KdcQ65gqI50OxnhTRGaxYktgrCkhdMIxF4WU3OuTTNg=; b=roBkL/JquBbbYyUY754H9P27PRIUVIA58qhM/fEDf/izolHTjptsamRyv81WQNrYUYy9TZdu 0rfr4V0HnLk5f0iC6t3hECk1cU7MV+M24httE0dF9B7McT5MH1dgzD48Z6NfdTf5/5d8czmG 6k+p0TPShPTNHDFndw20SjMJ1qU= X-Mailgun-Sending-Ip: 104.130.122.25 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e30b2b4.7f96e0aff420-smtp-out-n03; Tue, 28 Jan 2020 22:16:20 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9F6AEC433A2; Tue, 28 Jan 2020 22:16:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 28EFDC43383; Tue, 28 Jan 2020 22:16:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 28EFDC43383 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: iommu@lists.linux-foundation.org Cc: robin.murphy@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Joerg Roedel Subject: [PATCH v1 2/6] arm/smmu: Add auxiliary domain support for arm-smmuv2 Date: Tue, 28 Jan 2020 15:16:06 -0700 Message-Id: <1580249770-1088-3-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> References: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Support auxiliary domains for arm-smmu-v2 to initialize and support multiple pagetables for a single SMMU context bank. Since the smmu-v2 hardware doesn't have any built in support for switching the pagetable base it is left as an exercise to the caller to actually use the pagetable. Aux domains are supported if split pagetable (TTBR1) support has been enabled on the master domain. Each auxiliary domain will reuse the configuration of the master domain. By default the a domain with TTBR1 support will have the TTBR0 region disabled so the first attached aux domain will enable the TTBR0 region in the hardware and conversely the last domain to be detached will disable TTBR0 translations. All subsequent auxiliary domains create a pagetable but not touch the hardware. The leaf driver will be able to query the physical address of the pagetable with the DOMAIN_ATTR_PTBASE attribute so that it can use the address with whatever means it has to switch the pagetable base. Following is a pseudo code example of how a domain can be created /* Check to see if aux domains are supported */ if (iommu_dev_has_feature(dev, IOMMU_DEV_FEAT_AUX)) { iommu = iommu_domain_alloc(...); if (iommu_aux_attach_device(domain, dev)) return FAIL; /* Save the base address of the pagetable for use by the driver iommu_domain_get_attr(domain, DOMAIN_ATTR_PTBASE, &ptbase); } Then 'domain' can be used like any other iommu domain to map and unmap iova addresses in the pagetable. Signed-off-by: Jordan Crouse --- drivers/iommu/arm-smmu.c | 230 +++++++++++++++++++++++++++++++++++++++++++---- drivers/iommu/arm-smmu.h | 3 + 2 files changed, 217 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 23b22fa..85a6773 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -91,6 +91,8 @@ struct arm_smmu_cb { u32 tcr[2]; u32 mair[2]; struct arm_smmu_cfg *cfg; + atomic_t aux; + atomic_t refcount; }; struct arm_smmu_master_cfg { @@ -533,6 +535,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; + atomic_inc(&cb->refcount); cb->cfg = cfg; /* TCR */ @@ -671,6 +674,91 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); } +/* + * Update the context context bank to enable TTBR0. Assumes AARCH64 S1 + * configuration. + */ +static void arm_smmu_context_set_ttbr0(struct arm_smmu_cb *cb, + struct io_pgtable_cfg *pgtbl_cfg) +{ + u32 tcr = cb->tcr[0]; + + /* Add the TCR configuration from the new pagetable config */ + tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); + + /* Make sure that both TTBR0 and TTBR1 are enabled */ + tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); + + /* Udate the TCR register */ + cb->tcr[0] = tcr; + + /* Program the new TTBR0 */ + cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; + cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); +} + +/* + * Thus function assumes that the current model only allows aux domains for + * AARCH64 S1 configurations + */ +static int arm_smmu_aux_init_domain_context(struct iommu_domain *domain, + struct arm_smmu_device *smmu, struct arm_smmu_cfg *master) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct io_pgtable_ops *pgtbl_ops; + struct io_pgtable_cfg pgtbl_cfg; + + mutex_lock(&smmu_domain->init_mutex); + + /* Copy the configuration from the master */ + memcpy(&smmu_domain->cfg, master, sizeof(smmu_domain->cfg)); + + smmu_domain->flush_ops = &arm_smmu_s1_tlb_ops; + smmu_domain->smmu = smmu; + + pgtbl_cfg = (struct io_pgtable_cfg) { + .pgsize_bitmap = smmu->pgsize_bitmap, + .ias = smmu->va_size, + .oas = smmu->ipa_size, + .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK, + .tlb = smmu_domain->flush_ops, + .iommu_dev = smmu->dev, + .quirks = 0, + }; + + if (smmu_domain->non_strict) + pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; + + pgtbl_ops = alloc_io_pgtable_ops(ARM_64_LPAE_S1, &pgtbl_cfg, + smmu_domain); + if (!pgtbl_ops) { + mutex_unlock(&smmu_domain->init_mutex); + return -ENOMEM; + } + + domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; + + domain->geometry.aperture_end = (1UL << smmu->va_size) - 1; + domain->geometry.force_aperture = true; + + /* + * Add a reference to the context bank to make sure it stays programmed + * wile we are attached + */ + atomic_inc(&smmu->cbs[master->cbndx].refcount); + + /* enable TTBR0 when the the first aux domain is attached */ + if (atomic_inc_return(&smmu->cbs[master->cbndx].aux) == 1) { + arm_smmu_context_set_ttbr0(&smmu->cbs[master->cbndx], + &pgtbl_cfg); + arm_smmu_write_context_bank(smmu, master->cbndx); + } + + smmu_domain->ptbase = pgtbl_cfg.arm_lpae_s1_cfg.ttbr; + smmu_domain->pgtbl_ops = pgtbl_ops; + return 0; +} + static int arm_smmu_init_domain_context(struct iommu_domain *domain, struct arm_smmu_device *smmu) { @@ -882,36 +970,70 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, return ret; } +static void +arm_smmu_destroy_aux_domain_context(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + int ret; + + /* + * If this is the last aux domain to be freed, disable TTBR0 by turning + * off translations and clearing TTBR0 + */ + if (atomic_dec_return(&smmu->cbs[cfg->cbndx].aux) == 0) { + /* Clear out the T0 region */ + smmu->cbs[cfg->cbndx].tcr[0] &= ~GENMASK(15, 0); + /* Disable TTBR0 translations */ + smmu->cbs[cfg->cbndx].tcr[0] |= ARM_SMMU_TCR_EPD0; + /* Clear the TTBR0 pagetable address */ + smmu->cbs[cfg->cbndx].ttbr[0] = + FIELD_PREP(ARM_SMMU_TTBRn_ASID, cfg->asid); + + ret = arm_smmu_rpm_get(smmu); + if (!ret) { + arm_smmu_write_context_bank(smmu, cfg->cbndx); + arm_smmu_rpm_put(smmu); + } + } + +} + static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; - int ret, irq; if (!smmu || domain->type == IOMMU_DOMAIN_IDENTITY) return; - ret = arm_smmu_rpm_get(smmu); - if (ret < 0) - return; + if (smmu_domain->aux) + arm_smmu_destroy_aux_domain_context(smmu_domain); - /* - * Disable the context bank and free the page tables before freeing - * it. - */ - smmu->cbs[cfg->cbndx].cfg = NULL; - arm_smmu_write_context_bank(smmu, cfg->cbndx); + /* Check if the last user is done with the context bank */ + if (atomic_dec_return(&smmu->cbs[cfg->cbndx].refcount) == 0) { + int ret = arm_smmu_rpm_get(smmu); + int irq; - if (cfg->irptndx != ARM_SMMU_INVALID_IRPTNDX) { - irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; - devm_free_irq(smmu->dev, irq, domain); + if (ret < 0) + return; + + /* Disable the context bank */ + smmu->cbs[cfg->cbndx].cfg = NULL; + arm_smmu_write_context_bank(smmu, cfg->cbndx); + + if (cfg->irptndx != ARM_SMMU_INVALID_IRPTNDX) { + irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; + devm_free_irq(smmu->dev, irq, domain); + } + + __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); + arm_smmu_rpm_put(smmu); } + /* Destroy the pagetable */ free_io_pgtable_ops(smmu_domain->pgtbl_ops); - __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); - - arm_smmu_rpm_put(smmu); } static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) @@ -1181,6 +1303,73 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, return 0; } +static bool arm_smmu_dev_has_feat(struct device *dev, + enum iommu_dev_features feat) +{ + if (feat != IOMMU_DEV_FEAT_AUX) + return false; + + return true; +} + +static int arm_smmu_dev_enable_feat(struct device *dev, + enum iommu_dev_features feat) +{ + /* aux domain support is always available */ + if (feat == IOMMU_DEV_FEAT_AUX) + return 0; + + return -ENODEV; +} + +static int arm_smmu_dev_disable_feat(struct device *dev, + enum iommu_dev_features feat) +{ + return -EBUSY; +} + +static int arm_smmu_aux_attach_dev(struct iommu_domain *domain, + struct device *dev) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct arm_smmu_device *smmu = fwspec_smmu(fwspec); + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_cb *cb; + int idx, i, ret, cbndx = -1; + + /* Try to find the context bank configured for this device */ + for_each_cfg_sme(fwspec, i, idx) { + if (idx != INVALID_SMENDX) { + cbndx = smmu->s2crs[idx].cbndx; + break; + } + } + + if (cbndx == -1) + return -ENODEV; + + cb = &smmu->cbs[cbndx]; + + /* Aux domains are only supported for AARCH64 configurations */ + if (cb->cfg->fmt != ARM_SMMU_CTX_FMT_AARCH64) + return -EINVAL; + + /* Make sure that TTBR1 is enabled in the hardware */ + if ((cb->tcr[0] & ARM_SMMU_TCR_EPD1)) + return -EINVAL; + + smmu_domain->aux = true; + + ret = arm_smmu_rpm_get(smmu); + if (ret < 0) + return ret; + + ret = arm_smmu_aux_init_domain_context(domain, smmu, cb->cfg); + + arm_smmu_rpm_put(smmu); + return ret; +} + static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) { int ret; @@ -1549,6 +1738,11 @@ static int arm_smmu_domain_get_attr(struct iommu_domain *domain, case DOMAIN_ATTR_SPLIT_TABLES: *(int *)data = smmu_domain->split_pagetables; return 0; + case DOMAIN_ATTR_PTBASE: + if (!smmu_domain->aux) + return -EINVAL; + *(u64 *)data = smmu_domain->ptbase; + return 0; default: return -ENODEV; } @@ -1667,6 +1861,10 @@ static struct iommu_ops arm_smmu_ops = { .of_xlate = arm_smmu_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, .put_resv_regions = generic_iommu_put_resv_regions, + .dev_has_feat = arm_smmu_dev_has_feat, + .dev_enable_feat = arm_smmu_dev_enable_feat, + .dev_disable_feat = arm_smmu_dev_disable_feat, + .aux_attach_dev = arm_smmu_aux_attach_dev, .pgsize_bitmap = -1UL, /* Restricted during device attach */ }; diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index 53053fd..8266b29 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -345,6 +345,9 @@ struct arm_smmu_domain { spinlock_t cb_lock; /* Serialises ATS1* ops and TLB syncs */ struct iommu_domain domain; bool split_pagetables; + bool aux; + /* Shadow of the pagetable base for aux domains */ + u64 ptbase; }; static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) From patchwork Tue Jan 28 22:16:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 11355305 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03F5713A4 for ; Tue, 28 Jan 2020 22:16:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C949424687 for ; Tue, 28 Jan 2020 22:16:47 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Tue, 28 Jan 2020 22:16:22 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 7D5C2C433CB; Tue, 28 Jan 2020 22:16:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 17571C4479F; Tue, 28 Jan 2020 22:16:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 17571C4479F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: iommu@lists.linux-foundation.org Cc: robin.murphy@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Sean Paul , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Clark , David Airlie , freedreno@lists.freedesktop.org, Daniel Vetter Subject: [PATCH v1 3/6] drm/msm/adreno: ADd support for IOMMU auxiliary domains Date: Tue, 28 Jan 2020 15:16:07 -0700 Message-Id: <1580249770-1088-4-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> References: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for creating a auxiliary domain from the IOMMU device to implement per-instance pagetables. Also add a helper function to return the pagetable base address (ttbr) and asid to the caller so that the GPU target code can set up the pagetable switch. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_iommu.c | 72 +++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_mmu.h | 3 ++ 2 files changed, 75 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index e773ef8..df0d70a 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -7,9 +7,17 @@ #include "msm_drv.h" #include "msm_mmu.h" +/* + * It is up to us to assign ASIDS for our instances. Start at 32 to give a + * cushion to account for ASIDS assigned to real context banks + */ +static int msm_iommu_asid = 32; + struct msm_iommu { struct msm_mmu base; struct iommu_domain *domain; + u64 ttbr; + int asid; }; #define to_msm_iommu(x) container_of(x, struct msm_iommu, base) @@ -58,6 +66,20 @@ static void msm_iommu_destroy(struct msm_mmu *mmu) kfree(iommu); } +static void msm_iommu_aux_detach(struct msm_mmu *mmu) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + + iommu_aux_detach_device(iommu->domain, mmu->dev); +} + +static const struct msm_mmu_funcs aux_funcs = { + .detach = msm_iommu_aux_detach, + .map = msm_iommu_map, + .unmap = msm_iommu_unmap, + .destroy = msm_iommu_destroy, +}; + static const struct msm_mmu_funcs funcs = { .detach = msm_iommu_detach, .map = msm_iommu_map, @@ -65,6 +87,56 @@ static const struct msm_mmu_funcs funcs = { .destroy = msm_iommu_destroy, }; +bool msm_iommu_get_ptinfo(struct msm_mmu *mmu, u64 *ttbr, u32 *asid) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + + if (!iommu->ttbr) + return false; + + if (ttbr) + *ttbr = iommu->ttbr; + if (asid) + *asid = iommu->asid; + + return true; +} + +struct msm_mmu *msm_iommu_new_instance(struct device *dev, + struct iommu_domain *domain) +{ + struct msm_iommu *iommu; + u64 ptbase; + int ret; + + ret = iommu_aux_attach_device(domain, dev); + if (ret) + return ERR_PTR(ret); + + ret = iommu_domain_get_attr(domain, DOMAIN_ATTR_PTBASE, &ptbase); + if (ret) { + iommu_aux_detach_device(domain, dev); + return ERR_PTR(ret); + } + + iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); + if (!iommu) { + iommu_aux_detach_device(domain, dev); + return ERR_PTR(-ENOMEM); + } + + iommu->domain = domain; + iommu->ttbr = ptbase; + iommu->asid = msm_iommu_asid++; + + if (msm_iommu_asid > 0xff) + msm_iommu_asid = 32; + + msm_mmu_init(&iommu->base, dev, &aux_funcs); + + return &iommu->base; +} + struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) { struct msm_iommu *iommu; diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index bae9e8e..65a5cb2 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -32,6 +32,9 @@ static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev, } struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); +struct msm_mmu *msm_iommu_new_instance(struct device *dev, + struct iommu_domain *domain); +bool msm_iommu_get_ptinfo(struct msm_mmu *mmu, u64 *ttbr, u32 *asid); struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu); static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, From patchwork Tue Jan 28 22:16:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 11355301 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22F8A14B4 for ; Tue, 28 Jan 2020 22:16:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 00D622465B for ; Tue, 28 Jan 2020 22:16:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="qftK8xRR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726518AbgA1WQc (ORCPT ); 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Tue, 28 Jan 2020 22:16:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5A33CC43383; Tue, 28 Jan 2020 22:16:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5A33CC43383 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: iommu@lists.linux-foundation.org Cc: robin.murphy@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Sean Paul , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Clark , David Airlie , freedreno@lists.freedesktop.org, Daniel Vetter Subject: [PATCH v1 4/6] drm/msm: Add support to create target specific address spaces Date: Tue, 28 Jan 2020 15:16:08 -0700 Message-Id: <1580249770-1088-5-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> References: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support to create a GPU target specific address space for a context. For those targets that support per-instance pagetables they will return a new address space set up for the instance if possible otherwise just use the global device pagetable. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c | 22 +++++++++++++++++++--- drivers/gpu/drm/msm/msm_gpu.h | 2 ++ 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index e4b750b..e485dc1 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -585,6 +585,18 @@ static void load_gpu(struct drm_device *dev) mutex_unlock(&init_lock); } +static struct msm_gem_address_space *context_address_space(struct msm_gpu *gpu) +{ + if (!gpu) + return NULL; + + if (gpu->funcs->create_instance_space) + return gpu->funcs->create_instance_space(gpu); + + /* If all else fails use the default global space */ + return gpu->aspace; +} + static int context_init(struct drm_device *dev, struct drm_file *file) { struct msm_drm_private *priv = dev->dev_private; @@ -596,7 +608,7 @@ static int context_init(struct drm_device *dev, struct drm_file *file) msm_submitqueue_init(dev, ctx); - ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL; + ctx->aspace = context_address_space(priv->gpu); file->driver_priv = ctx; return 0; @@ -612,8 +624,12 @@ static int msm_open(struct drm_device *dev, struct drm_file *file) return context_init(dev, file); } -static void context_close(struct msm_file_private *ctx) +static void context_close(struct msm_drm_private *priv, + struct msm_file_private *ctx) { + if (priv->gpu && ctx->aspace != priv->gpu->aspace) + msm_gem_address_space_put(ctx->aspace); + msm_submitqueue_close(ctx); kfree(ctx); } @@ -628,7 +644,7 @@ static void msm_postclose(struct drm_device *dev, struct drm_file *file) priv->lastctx = NULL; mutex_unlock(&dev->struct_mutex); - context_close(ctx); + context_close(priv, ctx); } static irqreturn_t msm_irq(int irq, void *arg) diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index d496b68..76636da 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -64,6 +64,8 @@ struct msm_gpu_funcs { void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq); struct msm_gem_address_space *(*create_address_space) (struct msm_gpu *gpu, struct platform_device *pdev); + struct msm_gem_address_space *(*create_instance_space) + (struct msm_gpu *gpu); }; struct msm_gpu { From patchwork Tue Jan 28 22:16:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 11355289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0C6941398 for ; Tue, 28 Jan 2020 22:16:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF4672468D for ; Tue, 28 Jan 2020 22:16:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="JXWINBTX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726463AbgA1WQ3 (ORCPT ); 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Tue, 28 Jan 2020 22:16:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id B95D4C4479C; Tue, 28 Jan 2020 22:16:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B95D4C4479C Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: iommu@lists.linux-foundation.org Cc: robin.murphy@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Sean Paul , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Clark , David Airlie , freedreno@lists.freedesktop.org, Daniel Vetter Subject: [PATCH v1 5/6] drm/msm/gpu: Add ttbr0 to the memptrs Date: Tue, 28 Jan 2020 15:16:09 -0700 Message-Id: <1580249770-1088-6-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> References: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Targets that support per-instance pagetable switching will have to keep track of which pagetable belongs to each instance to be able to recover for preemption. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h index 7764373..c5822bd 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -29,6 +29,7 @@ struct msm_gpu_submit_stats { struct msm_rbmemptrs { volatile uint32_t rptr; volatile uint32_t fence; + volatile uint64_t ttbr0; volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; }; From patchwork Tue Jan 28 22:16:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 11355291 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED9AB1398 for ; Tue, 28 Jan 2020 22:16:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CC5C72467E for ; Tue, 28 Jan 2020 22:16:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="GQHVdOKG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726598AbgA1WQc (ORCPT ); Tue, 28 Jan 2020 17:16:32 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:28362 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726520AbgA1WQb (ORCPT ); Tue, 28 Jan 2020 17:16:31 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1580249790; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=Llw2kTJ4XUeuT4T/F2T53za68YIhWHzkSvM16vklV7s=; b=GQHVdOKG66u18uQdp7NU17M1hcim6myTJGX9LqbiNNUo4aOmG+QhW5JhVukMjiyWeE3Xxrpm gzv3N9h7Ty0gaxckkidNHzRyXCF5suXuZtG1INZMdB+SjyJHiOJk+lG2plX8xLhcSG8Iyqhb MWpzU1w+esPA6gkquG3C6z/oAGk= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e30b2bc.7f7e0360e228-smtp-out-n03; Tue, 28 Jan 2020 22:16:28 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 33847C447B0; Tue, 28 Jan 2020 22:16:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 143DFC433CB; Tue, 28 Jan 2020 22:16:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 143DFC433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: iommu@lists.linux-foundation.org Cc: robin.murphy@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Sean Paul , Sharat Masetty , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Clark , David Airlie , freedreno@lists.freedesktop.org, Daniel Vetter Subject: [PATCH v1 6/6] drm/msm/a6xx: Support per-instance pagetables Date: Tue, 28 Jan 2020 15:16:10 -0700 Message-Id: <1580249770-1088-7-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> References: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for per-instance pagetables for a6xx targets. Add support to handle split pagetables and create a new instance if the needed IOMMU support exists and insert the necessary PM4 commands to trigger a pagetable switch at the beginning of a user command. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 +++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 9bec603c..e1a257e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -12,6 +12,62 @@ #define GPU_PAS_ID 13 +static void a6xx_set_pagetable(struct msm_gpu *gpu, struct msm_ringbuffer *ring, + struct msm_file_private *ctx) +{ + u64 ttbr; + u32 asid; + + if (!msm_iommu_get_ptinfo(ctx->aspace->mmu, &ttbr, &asid)) + return; + + ttbr = ttbr | ((u64) asid) << 48; + + /* Turn off protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + /* Turn on APIV mode to access critical regions */ + OUT_PKT4(ring, REG_A6XX_CP_MISC_CNTL, 1); + OUT_RING(ring, 1); + + /* Make sure the ME is synchronized before staring the update */ + OUT_PKT7(ring, CP_WAIT_FOR_ME, 0); + + /* Execute the table update */ + OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); + OUT_RING(ring, lower_32_bits(ttbr)); + OUT_RING(ring, upper_32_bits(ttbr)); + /* CONTEXTIDR is currently unused */ + OUT_RING(ring, 0); + /* CONTEXTBANK is currently unused */ + OUT_RING(ring, 0); + + /* + * Write the new TTBR0 to the preemption records - this will be used to + * reload the pagetable if the current ring gets preempted out. + */ + OUT_PKT7(ring, CP_MEM_WRITE, 4); + OUT_RING(ring, lower_32_bits(rbmemptr(ring, ttbr0))); + OUT_RING(ring, upper_32_bits(rbmemptr(ring, ttbr0))); + OUT_RING(ring, lower_32_bits(ttbr)); + OUT_RING(ring, upper_32_bits(ttbr)); + + /* Invalidate the draw state so we start off fresh */ + OUT_PKT7(ring, CP_SET_DRAW_STATE, 3); + OUT_RING(ring, 0x40000); + OUT_RING(ring, 1); + OUT_RING(ring, 0); + + /* Turn off APRIV */ + OUT_PKT4(ring, REG_A6XX_CP_MISC_CNTL, 1); + OUT_RING(ring, 0); + + /* Turn off protected mode */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 1); +} + static inline bool _a6xx_check_idle(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -89,6 +145,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, struct msm_ringbuffer *ring = submit->ring; unsigned int i; + a6xx_set_pagetable(gpu, ring, ctx); + get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, rbmemptr_stats(ring, index, cpcycles_start)); @@ -878,6 +936,36 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) return (unsigned long)busy_time; } +static struct msm_gem_address_space* +a6xx_create_instance_space(struct msm_gpu *gpu) +{ + struct msm_gem_address_space *aspace; + struct iommu_domain *iommu; + struct msm_mmu *mmu; + + if (!iommu_dev_has_feature(&gpu->pdev->dev, IOMMU_DEV_FEAT_AUX)) + return gpu->aspace; + + iommu = iommu_domain_alloc(&platform_bus_type); + if (!iommu) + return gpu->aspace; + + mmu = msm_iommu_new_instance(&gpu->pdev->dev, iommu); + if (IS_ERR(mmu)) { + iommu_domain_free(iommu); + return gpu->aspace; + } + + aspace = msm_gem_address_space_create(mmu, "gpu", + 0x100000000ULL, 0x1ffffffffULL); + if (IS_ERR(aspace)) { + mmu->funcs->destroy(mmu); + return gpu->aspace; + } + + return aspace; +} + static struct msm_gem_address_space * a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) { @@ -951,6 +1039,7 @@ static const struct adreno_gpu_funcs funcs = { .gpu_state_put = a6xx_gpu_state_put, #endif .create_address_space = a6xx_create_address_space, + .create_instance_space = a6xx_create_instance_space, }, .get_timestamp = a6xx_get_timestamp, };