From patchwork Tue Feb 11 10:18:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11375147 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 880501580 for ; Tue, 11 Feb 2020 10:18:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5CAD620842 for ; Tue, 11 Feb 2020 10:18:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="Zr8feK0v" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728229AbgBKKSk (ORCPT ); Tue, 11 Feb 2020 05:18:40 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:52849 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727937AbgBKKSj (ORCPT ); Tue, 11 Feb 2020 05:18:39 -0500 Received: by mail-wm1-f67.google.com with SMTP id p9so2715248wmc.2 for ; Tue, 11 Feb 2020 02:18:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uZCAv4JP0mR1y+dfUp2XBUcP5A7SC7sXiDA7eSjSXMI=; b=Zr8feK0v14Exb3MJFeYI1O9Z4YDWNs16WJrx6uQd8eisb4wOQBECZAQpH8W3gpnUWC /EM5boDA0a8GauM0KEavTjAhNvgj/czgI5YQwqEuf7MeDFf1g9/3vVdzI43a3QBfY/gM W05a+V6/z6MV/Qx92PL4+8f2E5ckDlJqryfyw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uZCAv4JP0mR1y+dfUp2XBUcP5A7SC7sXiDA7eSjSXMI=; b=A69P4x/cwvLwga+R647mJEfQzX7aDol/RAbJQQ6CCH9pUY/9PbwRmxoo1VIUrvWY0+ YW1Yc4IydsWGM7arciicIotdzt6XiMRQkC0FQbcY2Shjm0Z8KxSloONVNelV4Eo1OoxE 4PW24PWiILpBlLmao7S6xKtqVB94o7BCxA5xNr7RsTF+sUVhmEzI76zotvfbq0CxG/zg ANKU5h1gxkMn/QHfIvfMRUZlP0ElCFm1MnzU64uRPUKbsKwTpgUxB5aUp0aD4V8e/bP/ NsbWvYW1rSh34EaoTe2MWD4+0oRnc3tzM5XabyCSzhMPj/ZAYhsnVGQG22g99qC9K/tz kTPg== X-Gm-Message-State: APjAAAXm9cGlvxnZK96ytrX/bopovmEXnFJk1tlNqIDym1/tWbtqEBXX qKmjQs5+vtkkQ5TWkav9DnSS7CpM3YswE8Kq5tzBfrkV33tX18raStolGxv05fbVRAFXSIIcYbH UUokfK/bTdQnXP3fbG7ifXXrVbx3k0AeSxty/Y0rjKGQ69aSP6aqfKhN7/acHvarUfbBh0fZ1Yb V0jZrCZMcCIVuzr/M/7t6bZSI= X-Google-Smtp-Source: APXvYqznpyo2BiC7QfH1yamXRn/Ai1N3jJomHBn+Zw8/SR8qX2RRUjnLsXli0oa33BkE/6ZYA9y5XQ== X-Received: by 2002:a7b:c94a:: with SMTP id i10mr4830060wml.88.1581416317348; Tue, 11 Feb 2020 02:18:37 -0800 (PST) Received: from dhcp-10-123-20-55.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id f65sm3058895wmf.29.2020.02.11.02.18.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Feb 2020 02:18:36 -0800 (PST) From: suganath-prabu.subramani@broadcom.com To: linux-scsi@vger.kernel.org Cc: sreekanth.reddy@broadcom.com, kashyap.desai@broadcom.com, sathya.prakash@broadcom.com, martin.petersen@oracle.com, Suganath Prabu S Subject: [PATCH 1/5] mpt3sas: Don't change the dma coherent mask after allocations Date: Tue, 11 Feb 2020 05:18:09 -0500 Message-Id: <1581416293-41610-2-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581416293-41610-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1581416293-41610-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Suganath Prabu S During driver load ioc->dma_mask is set to 0. Since this flag is not set, in _base_config_dma_addressing() driver always sets 32 bit DMA and later after allocating memory for RDPQ's the dma mask is set to 64/63 bit from _base_change_consistent_dma_mask. Removed Flag ioc->dma_mask and _base_change_consistent_dma_mask(). Set coherent dma mask to 64/63/32 bit based on controller at driver load time in _base_config_dma_addressing(). and If 63/64 bit fails attempt again with 32-bit DMA mask. Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c | 82 ++++++++++++++----------------------- drivers/scsi/mpt3sas/mpt3sas_base.h | 2 - 2 files changed, 30 insertions(+), 54 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 663782b..18c5045 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -2806,55 +2806,42 @@ _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, static int _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) { - u64 required_mask, coherent_mask; struct sysinfo s; - /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ - int dma_mask = (ioc->hba_mpi_version_belonged > MPI2_VERSION) ? 63 : 64; - + char *desc = "64"; + u64 consistent_dma_mask = DMA_BIT_MASK(64); if (ioc->is_mcpu_endpoint) goto try_32bit; - required_mask = dma_get_required_mask(&pdev->dev); - if (sizeof(dma_addr_t) == 4 || required_mask == 32) - goto try_32bit; - - if (ioc->dma_mask) - coherent_mask = DMA_BIT_MASK(dma_mask); - else - coherent_mask = DMA_BIT_MASK(32); - - if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)) || - dma_set_coherent_mask(&pdev->dev, coherent_mask)) - goto try_32bit; - - ioc->base_add_sg_single = &_base_add_sg_single_64; - ioc->sge_size = sizeof(Mpi2SGESimple64_t); - ioc->dma_mask = dma_mask; - goto out; - - try_32bit: - if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) + /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ + if (ioc->hba_mpi_version_belonged > MPI2_VERSION) { + consistent_dma_mask = DMA_BIT_MASK(63); + desc = "63"; + } + if (sizeof(dma_addr_t) > 4) { + const u64 required_mask = dma_get_required_mask(&pdev->dev); + if ((required_mask > DMA_BIT_MASK(32)) && + !pci_set_dma_mask(pdev, consistent_dma_mask) && + !pci_set_consistent_dma_mask(pdev, + consistent_dma_mask)) { + ioc->base_add_sg_single = &_base_add_sg_single_64; + ioc->sge_size = sizeof(Mpi2SGESimple64_t); + goto out; + } + } +try_32bit: + if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) + && !pci_set_consistent_dma_mask(pdev, + DMA_BIT_MASK(32))) { + ioc->base_add_sg_single = &_base_add_sg_single_32; + ioc->sge_size = sizeof(Mpi2SGESimple32_t); + desc = "32"; + } else return -ENODEV; - - ioc->base_add_sg_single = &_base_add_sg_single_32; - ioc->sge_size = sizeof(Mpi2SGESimple32_t); - ioc->dma_mask = 32; - out: +out: si_meminfo(&s); - ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", - ioc->dma_mask, convert_to_kb(s.totalram)); - - return 0; -} - -static int -_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc, - struct pci_dev *pdev) -{ - if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ioc->dma_mask))) { - if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) - return -ENODEV; - } + ioc_info(ioc, + "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", + desc, convert_to_kb(s.totalram)); return 0; } @@ -5169,14 +5156,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) total_sz += sz; } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); - if (ioc->dma_mask > 32) { - if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) { - ioc_warn(ioc, "no suitable consistent DMA mask for %s\n", - pci_name(ioc->pdev)); - goto out; - } - } - ioc->scsiio_depth = ioc->hba_queue_depth - ioc->hi_priority_depth - ioc->internal_depth; @@ -7158,7 +7137,6 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) ioc->smp_affinity_enable = smp_affinity_enable; ioc->rdpq_array_enable_assigned = 0; - ioc->dma_mask = 0; if (ioc->is_aero_ioc) ioc->base_readl = &_base_readl_aero; else diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index e719715..caae040 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -1026,7 +1026,6 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc); * @ir_firmware: IR firmware present * @bars: bitmask of BAR's that must be configured * @mask_interrupts: ignore interrupt - * @dma_mask: used to set the consistent dma mask * @pci_access_mutex: Mutex to synchronize ioctl, sysfs show path and * pci resource handling * @fault_reset_work_q_name: fw fault work queue @@ -1205,7 +1204,6 @@ struct MPT3SAS_ADAPTER { u8 ir_firmware; int bars; u8 mask_interrupts; - int dma_mask; /* fw fault handler */ char fault_reset_work_q_name[20]; From patchwork Tue Feb 11 10:18:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11375149 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BE1FA921 for ; Tue, 11 Feb 2020 10:18:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9EC262086A for ; Tue, 11 Feb 2020 10:18:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="BwMvL4o+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728242AbgBKKSn (ORCPT ); Tue, 11 Feb 2020 05:18:43 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:44859 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727937AbgBKKSn (ORCPT ); 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Tue, 11 Feb 2020 02:18:40 -0800 (PST) Received: from dhcp-10-123-20-55.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id f65sm3058895wmf.29.2020.02.11.02.18.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Feb 2020 02:18:39 -0800 (PST) From: suganath-prabu.subramani@broadcom.com To: linux-scsi@vger.kernel.org Cc: sreekanth.reddy@broadcom.com, kashyap.desai@broadcom.com, sathya.prakash@broadcom.com, martin.petersen@oracle.com, Suganath Prabu S Subject: [PATCH 2/5] mpt3sas: Rename function name is_MSB_are_same Date: Tue, 11 Feb 2020 05:18:10 -0500 Message-Id: <1581416293-41610-3-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581416293-41610-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1581416293-41610-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Suganath Prabu S Renamed is_MSB_are_same() to mpt3sas_check_same_4gb_region() for better readability. Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 18c5045..4718b86 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -4922,7 +4922,7 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) } /** - * is_MSB_are_same - checks whether all reply queues in a set are + * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are * having same upper 32bits in their base memory address. * @reply_pool_start_address: Base address of a reply queue set * @pool_sz: Size of single Reply Descriptor Post Queues pool size @@ -4932,7 +4932,7 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) */ static int -is_MSB_are_same(long reply_pool_start_address, u32 pool_sz) +mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz) { long reply_pool_end_address; @@ -5384,7 +5384,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) * Actual requirement is not alignment, but we need start and end of * DMA address must have same upper 32 bit address. */ - if (!is_MSB_are_same((long)ioc->sense, sz)) { + if (!mpt3sas_check_same_4gb_region((long)ioc->sense, sz)) { //Release Sense pool & Reallocate dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); dma_pool_destroy(ioc->sense_dma_pool); From patchwork Tue Feb 11 10:18:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11375151 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95AB71580 for ; Tue, 11 Feb 2020 10:18:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 753DD20848 for ; Tue, 11 Feb 2020 10:18:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="cBKdwlyq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728241AbgBKKSr (ORCPT ); Tue, 11 Feb 2020 05:18:47 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:33489 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727937AbgBKKSr (ORCPT ); Tue, 11 Feb 2020 05:18:47 -0500 Received: by mail-wm1-f65.google.com with SMTP id m10so1918821wmc.0 for ; Tue, 11 Feb 2020 02:18:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Mg77+Vkmr1pxwidUzM/drgkbfNBSA8a+O8NQjwl4X+o=; b=cBKdwlyqEZA43xibeY0G78wbCeu7gHlZ7hpiDCHxXxxSrDOKni/meY9HiuyvRVqwxf ZAA+9d9PhDjj86NGYxEigQ8tG4g6q+14lwdgllTTHWf6GB/r0YZ9Yexocg9LoI570RC7 KwbZoWLq+5i56l8/zFEd5Q/S9mHmgOSy628G0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Mg77+Vkmr1pxwidUzM/drgkbfNBSA8a+O8NQjwl4X+o=; b=cCpPwJMkVZlxfgrxRSETBvt+YuOgqdKAnrcpgN4rsFhMnHDvuVumzc9rYJPCKm2L+H H/UovdmkMZ8WoaO7OEXzsfA3nY/mnyzbVEKC+vN9gY//nvtxdQTw42VR40mdoZm126qJ 9MOEBRvgrW2hpxMkM0GA8Ff4wUOorHl6EiUZPPP+C/JYBj4FsnQVvt+dLHCHQP8ocMw2 kAkIRUq3SLuGO99sJrXD3SGqthjzYqfaYVcGb1jDHvaxpRis3yxLJ0JQy0na9ZxbW4YM yHqCsHxlrMQsFM+scCApU3p/+G9mrsRmYGCPvv+53maGDG6mA8kQf+sTnzBFHiRb5/KY D2VQ== X-Gm-Message-State: APjAAAXvuO2fM5H16oIH/cIrn45YzuAJZZpOVZ24chcneCVkvzn4ytTg S5hKzh+HofQhHFdodhnu/CxX71u9KEDWdcC97VPuUtSos1tG/Wcgvp90lpFzv8b1dkYOVCVHmV/ WXeB/FJK743nfNxO5fgwqAJN2tK5zOGsK87qoqoSkfOxuOkD+v70qKzx2avQaKSLpCGkaTSMwTc HC/QfpIxrh0txk8EFZx+qYgfw= X-Google-Smtp-Source: APXvYqxrkf/Sy0UaaPSamntYbVxD5j58e0OOdnP43ORoI3LU5h1g6Ncku6desuVNxnKanSVf0j0jSA== X-Received: by 2002:a1c:670a:: with SMTP id b10mr3826038wmc.2.1581416323627; Tue, 11 Feb 2020 02:18:43 -0800 (PST) Received: from dhcp-10-123-20-55.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id f65sm3058895wmf.29.2020.02.11.02.18.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Feb 2020 02:18:43 -0800 (PST) From: suganath-prabu.subramani@broadcom.com To: linux-scsi@vger.kernel.org Cc: sreekanth.reddy@broadcom.com, kashyap.desai@broadcom.com, sathya.prakash@broadcom.com, martin.petersen@oracle.com, Suganath Prabu S Subject: [PATCH 3/5] mpt3sas: Code Refactoring. Date: Tue, 11 Feb 2020 05:18:11 -0500 Message-Id: <1581416293-41610-4-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581416293-41610-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1581416293-41610-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Suganath Prabu S Separate out RDPQ allocations to new function base_alloc_rdpq_dma_pool(). Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c | 88 +++++++++++++++++++++---------------- 1 file changed, 51 insertions(+), 37 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 4718b86..8739310 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -4946,6 +4946,55 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz) } /** + * base_alloc_rdpq_dma_pool - Allocating DMA'able memory + * for reply queues. + * @ioc: er object + * @sz: DMA Pool size + * Return: 0 for success, non-zero for failure. + */ +static int +base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz) +{ + int i; + + ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? + (ioc->reply_queue_count):1, + sizeof(struct reply_post_struct), GFP_KERNEL); + + if (!ioc->reply_post) { + ioc_err(ioc, "reply_post_free pool: kcalloc failed\n"); + return -ENOMEM; + } + ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", + &ioc->pdev->dev, sz, 16, 0); + if (!ioc->reply_post_free_dma_pool) { + ioc_err(ioc, "reply_post_free pool: dma_pool_create failed\n"); + return -ENOMEM; + } + i = 0; + do { + ioc->reply_post[i].reply_post_free = + dma_pool_zalloc(ioc->reply_post_free_dma_pool, + GFP_KERNEL, + &ioc->reply_post[i].reply_post_free_dma); + if (!ioc->reply_post[i].reply_post_free) { + ioc_err(ioc, "reply_post_free pool: dma_pool_alloc failed\n"); + return -ENOMEM; + } + dinitprintk(ioc, + ioc_info(ioc, "reply post free pool (0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n", + ioc->reply_post[i].reply_post_free, + ioc->reply_post_queue_depth, + 8, sz / 1024)); + dinitprintk(ioc, + ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n", + (u64)ioc->reply_post[i].reply_post_free_dma)); + + } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); + return 0; +} + +/** * _base_allocate_memory_pools - allocate start of day memory pools * @ioc: per adapter object * @@ -5112,49 +5161,15 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize, ioc->chains_needed_per_io); - /* reply post queue, 16 byte align */ reply_post_free_sz = ioc->reply_post_queue_depth * sizeof(Mpi2DefaultReplyDescriptor_t); - sz = reply_post_free_sz; if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) sz *= ioc->reply_queue_count; - - ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? - (ioc->reply_queue_count):1, - sizeof(struct reply_post_struct), GFP_KERNEL); - - if (!ioc->reply_post) { - ioc_err(ioc, "reply_post_free pool: kcalloc failed\n"); - goto out; - } - ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", - &ioc->pdev->dev, sz, 16, 0); - if (!ioc->reply_post_free_dma_pool) { - ioc_err(ioc, "reply_post_free pool: dma_pool_create failed\n"); + if (base_alloc_rdpq_dma_pool(ioc, sz)) goto out; - } - i = 0; - do { - ioc->reply_post[i].reply_post_free = - dma_pool_zalloc(ioc->reply_post_free_dma_pool, - GFP_KERNEL, - &ioc->reply_post[i].reply_post_free_dma); - if (!ioc->reply_post[i].reply_post_free) { - ioc_err(ioc, "reply_post_free pool: dma_pool_alloc failed\n"); - goto out; - } - dinitprintk(ioc, - ioc_info(ioc, "reply post free pool (0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n", - ioc->reply_post[i].reply_post_free, - ioc->reply_post_queue_depth, - 8, sz / 1024)); - dinitprintk(ioc, - ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n", - (u64)ioc->reply_post[i].reply_post_free_dma)); - total_sz += sz; - } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); + total_sz += sz; ioc->scsiio_depth = ioc->hba_queue_depth - ioc->hi_priority_depth - ioc->internal_depth; @@ -5167,7 +5182,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) ioc_info(ioc, "scsi host: can_queue depth (%d)\n", ioc->shost->can_queue)); - /* contiguous pool for request and chains, 16 byte align, one extra " * "frame for smid=0 */ From patchwork Tue Feb 11 10:18:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11375153 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F39CA1580 for ; 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Tue, 11 Feb 2020 02:18:46 -0800 (PST) From: suganath-prabu.subramani@broadcom.com To: linux-scsi@vger.kernel.org Cc: sreekanth.reddy@broadcom.com, kashyap.desai@broadcom.com, sathya.prakash@broadcom.com, martin.petersen@oracle.com, Suganath Prabu S Subject: [PATCH 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4g region Date: Tue, 11 Feb 2020 05:18:12 -0500 Message-Id: <1581416293-41610-5-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581416293-41610-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1581416293-41610-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Suganath Prabu S For INVADER_SERIES each set of 8 reply queues (0 - 7, 8 - 15,..)and VENTURA_SERIES each set of 16 reply queues (0 - 15, 16 - 31,..)should be within 4 GB boundary.Driver uses limitation of VENTURA_SERIES to manage INVADER_SERIES as well. So here driver is allocating the DMA able memory for RDPQ's accordingly. For RDPQ buffers, driver creates two separate pci pool. "reply_post_free_dma_pool" and "reply_post_free_dma_pool_align" First driver tries allocating memory from the pool "reply_post_free_dma_pool", if the requested allocation are within same 4gb region then proceeds for next allocations. If not, allocates from reply_post_free_dma_pool_align which is size aligned and if success, it will always meet same 4gb region requirement Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c | 167 ++++++++++++++++++++++++++---------- drivers/scsi/mpt3sas/mpt3sas_base.h | 3 + 2 files changed, 123 insertions(+), 47 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 8739310..7d10dd8 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -4814,8 +4814,8 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) { int i = 0; int j = 0; + int dma_alloc_count = 0; struct chain_tracker *ct; - struct reply_post_struct *rps; dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); @@ -4857,29 +4857,35 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) } if (ioc->reply_post) { - do { - rps = &ioc->reply_post[i]; - if (rps->reply_post_free) { - dma_pool_free( - ioc->reply_post_free_dma_pool, - rps->reply_post_free, - rps->reply_post_free_dma); - dexitprintk(ioc, - ioc_info(ioc, "reply_post_free_pool(0x%p): free\n", - rps->reply_post_free)); - rps->reply_post_free = NULL; + dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count, + RDPQ_MAX_INDEX_IN_ONE_CHUNK); + for (i = 0; i < ioc->reply_queue_count; i++) { + if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0 + && dma_alloc_count) { + if (ioc->reply_post[i].reply_post_free) { + pci_pool_free( + ioc->reply_post[i].dma_pool, + ioc->reply_post[i].reply_post_free, + ioc->reply_post[i].reply_post_free_dma); + dexitprintk(ioc, ioc_info(ioc, + "reply_post_free_pool(0x%p): free\n", + ioc->reply_post[i].reply_post_free)); + ioc->reply_post[i].reply_post_free = + NULL; + } + --dma_alloc_count; } - } while (ioc->rdpq_array_enable && - (++i < ioc->reply_queue_count)); + } + dma_pool_destroy(ioc->reply_post_free_dma_pool); + dma_pool_destroy(ioc->reply_post_free_dma_pool_align); if (ioc->reply_post_free_array && ioc->rdpq_array_enable) { dma_pool_free(ioc->reply_post_free_array_dma_pool, - ioc->reply_post_free_array, - ioc->reply_post_free_array_dma); + ioc->reply_post_free_array, + ioc->reply_post_free_array_dma); ioc->reply_post_free_array = NULL; } dma_pool_destroy(ioc->reply_post_free_array_dma_pool); - dma_pool_destroy(ioc->reply_post_free_dma_pool); kfree(ioc->reply_post); } @@ -4955,42 +4961,108 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz) static int base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz) { - int i; + int i = 0; + u32 dma_alloc_count = 0; + int reply_post_free_sz = ioc->reply_post_queue_depth * + sizeof(Mpi2DefaultReplyDescriptor_t); ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? - (ioc->reply_queue_count):1, - sizeof(struct reply_post_struct), GFP_KERNEL); - + (ioc->reply_queue_count):1, + sizeof(struct reply_post_struct), GFP_KERNEL); if (!ioc->reply_post) { ioc_err(ioc, "reply_post_free pool: kcalloc failed\n"); return -ENOMEM; } - ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", - &ioc->pdev->dev, sz, 16, 0); - if (!ioc->reply_post_free_dma_pool) { + /* + * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and + * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should + * be within 4GB boundary and also reply queues in a set must have same + * upper 32-bits in their memory address. so here driver is allocating + * the DMA'able memory for reply queues according. + * Driver uses limitation of + * VENTURA_SERIES to manage INVADER_SERIES as well. + */ + dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count, + RDPQ_MAX_INDEX_IN_ONE_CHUNK); + ioc->reply_post_free_dma_pool = + dma_pool_create("reply_post_free pool", + &ioc->pdev->dev, sz, 16, 0); + ioc->reply_post_free_dma_pool_align = + dma_pool_create("reply_post_free pool", + &ioc->pdev->dev, sz, roundup_pow_of_two(sz), 0); + if (!ioc->reply_post_free_dma_pool || + !ioc->reply_post_free_dma_pool_align) { ioc_err(ioc, "reply_post_free pool: dma_pool_create failed\n"); return -ENOMEM; } - i = 0; - do { - ioc->reply_post[i].reply_post_free = - dma_pool_zalloc(ioc->reply_post_free_dma_pool, - GFP_KERNEL, - &ioc->reply_post[i].reply_post_free_dma); - if (!ioc->reply_post[i].reply_post_free) { - ioc_err(ioc, "reply_post_free pool: dma_pool_alloc failed\n"); - return -ENOMEM; - } - dinitprintk(ioc, - ioc_info(ioc, "reply post free pool (0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n", - ioc->reply_post[i].reply_post_free, - ioc->reply_post_queue_depth, - 8, sz / 1024)); - dinitprintk(ioc, - ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n", - (u64)ioc->reply_post[i].reply_post_free_dma)); + for (i = 0; i < ioc->reply_queue_count; i++) { + if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) { + ioc->reply_post[i].reply_post_free = + dma_pool_alloc(ioc->reply_post_free_dma_pool, + GFP_KERNEL, + &ioc->reply_post[i].reply_post_free_dma); + if (!ioc->reply_post[i].reply_post_free) { + ioc_err(ioc, "reply_post_free pool: " + "dma_pool_alloc failed\n"); + return -ENOMEM; + } + /* reply desc pool requires to be in same 4 gb region. + * Below function will check this. + * In case of failure, new pci pool will be created with updated + * alignment. + * For RDPQ buffers, driver allocates two separate pci pool. + * Alignment will be used such a way that next allocation if + * success, will always meet same 4gb region requirement. + * Flag dma_pool keeps track of each buffers pool, + * It will help driver while freeing the resources. + */ + if (!mpt3sas_check_same_4gb_region( + (long)ioc->reply_post[i].reply_post_free, sz)) { + dinitprintk(ioc, + ioc_err(ioc, "bad Replypost free pool(0x%p)" + "reply_post_free_dma = (0x%llx)\n", + ioc->reply_post[i].reply_post_free, + (unsigned long long) + ioc->reply_post[i].reply_post_free_dma)); + + pci_pool_free(ioc->reply_post_free_dma_pool, + ioc->reply_post[i].reply_post_free, + ioc->reply_post[i].reply_post_free_dma); + + ioc->reply_post[i].reply_post_free = NULL; + ioc->reply_post[i].reply_post_free_dma = 0; + //Retry with modified alignment + ioc->reply_post[i].reply_post_free = + dma_pool_alloc( + ioc->reply_post_free_dma_pool_align, + GFP_KERNEL, + &ioc->reply_post[i].reply_post_free_dma); + if (!ioc->reply_post[i].reply_post_free) { + ioc_err(ioc, "reply_post_free pool: " + "pci_pool_alloc failed\n"); + return -ENOMEM; + } + ioc->reply_post[i].dma_pool = + ioc->reply_post_free_dma_pool_align; + } else + ioc->reply_post[i].dma_pool = + ioc->reply_post_free_dma_pool; + memset(ioc->reply_post[i].reply_post_free, 0, + RDPQ_MAX_INDEX_IN_ONE_CHUNK * + reply_post_free_sz); + dma_alloc_count--; - } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); + } else { + ioc->reply_post[i].reply_post_free = + (Mpi2ReplyDescriptorsUnion_t *) + ((long)ioc->reply_post[i-1].reply_post_free + + reply_post_free_sz); + ioc->reply_post[i].reply_post_free_dma = + (dma_addr_t) + (ioc->reply_post[i-1].reply_post_free_dma + + reply_post_free_sz); + } + } return 0; } @@ -5008,6 +5080,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) u16 chains_needed_per_io; u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz; u32 retry_sz; + u32 rdpq_sz = 0; u16 max_request_credit, nvme_blocks_needed; unsigned short sg_tablesize; u16 sge_size; @@ -5164,12 +5237,12 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) /* reply post queue, 16 byte align */ reply_post_free_sz = ioc->reply_post_queue_depth * sizeof(Mpi2DefaultReplyDescriptor_t); - sz = reply_post_free_sz; + rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK; if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) - sz *= ioc->reply_queue_count; - if (base_alloc_rdpq_dma_pool(ioc, sz)) + rdpq_sz = reply_post_free_sz * ioc->reply_queue_count; + if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz)) goto out; - total_sz += sz; + total_sz += rdpq_sz; ioc->scsiio_depth = ioc->hba_queue_depth - ioc->hi_priority_depth - ioc->internal_depth; diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index caae040..30ca583 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -367,6 +367,7 @@ struct mpt3sas_nvme_cmd { #define MPT3SAS_HIGH_IOPS_REPLY_QUEUES 8 #define MPT3SAS_HIGH_IOPS_BATCH_COUNT 16 #define MPT3SAS_GEN35_MAX_MSIX_QUEUES 128 +#define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16 /* OEM Specific Flags will come from OEM specific header files */ struct Mpi2ManufacturingPage10_t { @@ -1006,6 +1007,7 @@ struct mpt3sas_port_facts { struct reply_post_struct { Mpi2ReplyDescriptorsUnion_t *reply_post_free; dma_addr_t reply_post_free_dma; + struct dma_pool *dma_pool; }; typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc); @@ -1423,6 +1425,7 @@ struct MPT3SAS_ADAPTER { u8 rdpq_array_enable; u8 rdpq_array_enable_assigned; struct dma_pool *reply_post_free_dma_pool; + struct dma_pool *reply_post_free_dma_pool_align; struct dma_pool *reply_post_free_array_dma_pool; Mpi2IOCInitRDPQArrayEntry *reply_post_free_array; dma_addr_t reply_post_free_array_dma; From patchwork Tue Feb 11 10:18:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11375155 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 32510921 for ; Tue, 11 Feb 2020 10:18:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 11AEC2086A for ; Tue, 11 Feb 2020 10:18:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="LhiRP6FA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728252AbgBKKSw (ORCPT ); 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Tue, 11 Feb 2020 02:18:49 -0800 (PST) Received: from dhcp-10-123-20-55.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id f65sm3058895wmf.29.2020.02.11.02.18.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Feb 2020 02:18:49 -0800 (PST) From: suganath-prabu.subramani@broadcom.com To: linux-scsi@vger.kernel.org Cc: sreekanth.reddy@broadcom.com, kashyap.desai@broadcom.com, sathya.prakash@broadcom.com, martin.petersen@oracle.com, Suganath Prabu S Subject: [PATCH 5/5] mpt3sas: Update version to 33.101.00.00 Date: Tue, 11 Feb 2020 05:18:13 -0500 Message-Id: <1581416293-41610-6-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581416293-41610-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1581416293-41610-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Suganath Prabu S Update driver version from 33.100.00.00 to 33.101.00.00 Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index 30ca583..25f1701 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -76,9 +76,9 @@ #define MPT3SAS_DRIVER_NAME "mpt3sas" #define MPT3SAS_AUTHOR "Avago Technologies " #define MPT3SAS_DESCRIPTION "LSI MPT Fusion SAS 3.0 Device Driver" -#define MPT3SAS_DRIVER_VERSION "33.100.00.00" +#define MPT3SAS_DRIVER_VERSION "33.101.00.00" #define MPT3SAS_MAJOR_VERSION 33 -#define MPT3SAS_MINOR_VERSION 100 +#define MPT3SAS_MINOR_VERSION 101 #define MPT3SAS_BUILD_VERSION 0 #define MPT3SAS_RELEASE_VERSION 00