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X-Microsoft-Antispam-Message-Info: UF2mqi8ZpodRKMfOWx6ZI7D5ypeW88corTV92tC72xQEn8jpUeS/Vq+idCPGV8p+o+jQXEWD7+/XNYWrVZiohGW+IHT2rTg/LgFjwwV6CTSGqI8LfMngtc9dTx5T4zP3lLNt/wX5g1oIdLHihgunwz7pwrWpVXfxcLGhK7YEzyUz+S8CvxqErxN1tNIAoa+AvE0Ga2vE4ymRboyc16VgB84mo3tZl4G2txYD+IADyiwxSuB7Y4oy8UGT4239A2TfkeH7ErQ1h/zPMagN2yqUQfBqtNzT0Q/iQHBlRkf70TpisLrWwvJLoFWsJf2XUIEzkM0A4aX+04uZWw6qX90fERJ4pTI2GtL6sfqhwN2xKDQblWo0w4UQ5rM0MJ5WlYcwOtj7R11raRDL/mGHGZoKy93pKh+4ykfuLM6iALJ/AUdUJQf++BkG669AyTHJp0uzS6lxTbdkRSKsP0fQgC4MTfeQL8O7J9sQfNLVuvfE66yPaYFVp3o0TsCtGWLG+jQ/6/Tefhk56cLxUTpbyuVEdPHZKr2Fg7ELMLwSLeAkl/g= X-MS-Exchange-AntiSpam-MessageData: FkhKncoWkJSTDcyE58gDTwqYyQYldRNWhbZonIFtWil1mQwuYisQRqUV5icAYdmF9zp/mK6W/db2o2H2MMsGcRaksrHaATAd7vUJTk3c2O63DItp0v35ESUn5ogK2NvcM7YssE93Uf3QQBSjTlD1ow== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4fd45836-a755-4c3c-3af5-08d7afb4b1b1 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2020 12:11:30.9089 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: oB3ueQ1swwOc2cF5tXT1nMuuLIQ2/Em96lqFi6u0CUsD9b7nheEi1jXXYPaL3aVO5zPqnBJkUQMiQUPeFjIdgg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4026 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200212_041136_713068_6570331E X-CRM114-Status: GOOD ( 16.56 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.22.86 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [40.107.22.86 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DDR perf driver now only supports free running counter, add stop counter support which would be compabile to free running counter, since i.MX8MP is not free running. Add spinlock for counter value update and clear. Signed-off-by: Joakim Zhang --- drivers/perf/fsl_imx8_ddr_perf.c | 69 ++++++++++++++++++++++++-------- 1 file changed, 52 insertions(+), 17 deletions(-) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 95dca2cb5265..0a029715ca6c 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #define COUNTER_CNTL 0x0 @@ -82,6 +83,7 @@ struct ddr_pmu { const struct fsl_ddr_devtype_data *devtype_data; int irq; int id; + spinlock_t lock; }; enum ddr_perf_filter_capabilities { @@ -368,16 +370,20 @@ static void ddr_perf_event_update(struct perf_event *event) struct hw_perf_event *hwc = &event->hw; u64 delta, prev_raw_count, new_raw_count; int counter = hwc->idx; + unsigned long flags; - do { - prev_raw_count = local64_read(&hwc->prev_count); - new_raw_count = ddr_perf_read_counter(pmu, counter); - } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - new_raw_count) != prev_raw_count); + spin_lock_irqsave(&pmu->lock, flags); + + prev_raw_count = local64_read(&hwc->prev_count); + new_raw_count = ddr_perf_read_counter(pmu, counter); delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; local64_add(delta, &event->count); + local64_set(&hwc->prev_count, new_raw_count); + + spin_unlock_irqrestore(&pmu->lock, flags); + } static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, @@ -402,6 +408,15 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, } } +static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter) +{ + int val; + + val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL); + + return val & CNTL_OVER ? true : false; +} + static void ddr_perf_event_start(struct perf_event *event, int flags) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); @@ -532,9 +547,9 @@ static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, static irqreturn_t ddr_perf_irq_handler(int irq, void *p) { - int i; + int i, ret; struct ddr_pmu *pmu = (struct ddr_pmu *) p; - struct perf_event *event, *cycle_event = NULL; + struct perf_event *event; /* all counter will stop if cycle counter disabled */ ddr_perf_counter_enable(pmu, @@ -544,12 +559,7 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p) /* * When the cycle counter overflows, all counters are stopped, * and an IRQ is raised. If any other counter overflows, it - * continues counting, and no IRQ is raised. - * - * Cycles occur at least 4 times as often as other events, so we - * can update all events on a cycle counter overflow and not - * lose events. - * + * will stop and no IRQ is raised. */ for (i = 0; i < NUM_COUNTERS; i++) { @@ -559,17 +569,41 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p) event = pmu->events[i]; ddr_perf_event_update(event); + } + + spin_lock(&pmu->lock); - if (event->hw.idx == EVENT_CYCLES_COUNTER) - cycle_event = event; + for (i = 0; i < NUM_COUNTERS; i++) { + if (!pmu->events[i]) + continue; + + if (i == EVENT_CYCLES_COUNTER) + continue; + + event = pmu->events[i]; + + /* check non-cycle counters overflow */ + ret = ddr_perf_counter_overflow(pmu, event->hw.idx); + if (ret) + dev_warn(pmu->dev, "Counter%d (not cycle counter) overflow happened, data incorrect!\n", i); + + /* clear non-cycle counters */ + ddr_perf_counter_enable(pmu, event->attr.config, event->hw.idx, true); + + /* update the prev_conter */ + local64_set(&event->hw.prev_count, 0); } + if (pmu->events[EVENT_CYCLES_ID]) + local64_set(&pmu->events[EVENT_CYCLES_ID]->hw.prev_count, 0); + + /* enable cycle counter to start all counters */ ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID, EVENT_CYCLES_COUNTER, true); - if (cycle_event) - ddr_perf_event_update(cycle_event); + + spin_unlock(&pmu->lock); return IRQ_HANDLED; } @@ -617,6 +651,7 @@ static int ddr_perf_probe(struct platform_device *pdev) num = ddr_perf_init(pmu, base, &pdev->dev); platform_set_drvdata(pdev, pmu); + spin_lock_init(&pmu->lock); name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", num);