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bh=68dCE8AAJ7ks0wme6FIZwJzv+K1DwC/CeEghUvOZQm8=; b=H3J4oTJBA1O1HIY7E/zWpPvqS+T3fyFDVvw51S8Sr7TCF6idkw0AxO6TST4oE737Ii JX6vuashaewkwzrRA7AhNUgMk1Wkv9jBTJhjdXo6zx8Dai9yMkGNV3b7XyzsR7q+HuE5 qh8i0L0cVxZGNdWUk8zAQ1XSYYoa0HD4OznRxu2clCvoOwSezl4gkFLcKKh6eQBG484E NPMPaNuLpW1+eqesmb7jsDvkIEzMJCSeFtwTgNQgCFwgGYBkXddfO/t7+x68B2EJWljd Fo75051LucvLkn8Qwrd/79m5C+/IvYzKw05nY4fk7rdBQv6FR8jDx2LOUtsjEq5h7SUz rgQA== X-Gm-Message-State: ABuFfojU7T0tTxsPLyTdkFPjg1DsKttA4dYoTN99e4DF/tpYwOdjPW0/ l3VWcYfxaN+/rmGxyQKbfwU= X-Google-Smtp-Source: ACcGV60uKXiUiI+N+LKuITTXmlWXjpbfGwyrmtNNbScHDTZrVF1Vqp/cHy3qLLrKpNye0YV9/iKmBA== X-Received: by 2002:a37:e20a:: with SMTP id g10-v6mr9910556qki.45.1538088381308; Thu, 27 Sep 2018 15:46:21 -0700 (PDT) Received: from localhost ([2601:184:4780:7861:6268:7a0b:50be:cebc]) by smtp.gmail.com with ESMTPSA id 23-v6sm1969465qkn.11.2018.09.27.15.46.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Sep 2018 15:46:20 -0700 (PDT) From: Rob Clark To: iommu@lists.linux-foundation.org, Will Deacon , Robin Murphy , linux-arm-kernel@lists.infradead.org Subject: [PATCH] iommu: arm-smmu: Set SCTLR.HUPCF bit Date: Thu, 27 Sep 2018 18:46:07 -0400 Message-Id: <20180927224609.19515-1-robdclark@gmail.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180927_154653_086076_CC8F0E50 X-CRM114-Status: GOOD ( 14.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, Rob Clark , freedreno@lists.freedesktop.org, Joerg Roedel , linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We seem to need to set either this or CFCFG (stall), otherwise gpu faults trigger problems with other in-flight transactions from the GPU causing CP errors, etc. In the ARM SMMU spec, the 'Hit under previous context fault' bit is described as: '0' - Stall or terminate subsequent transactions in the presence of an outstanding context fault '1' - Process all subsequent transactions independently of any outstanding context fault. Since we don't enable CFCFG (stall) the behavior of terminating other transactions makes sense. And is probably not what we want (and definately not what we want for GPU). Signed-off-by: Rob Clark --- So I hit this issue a long time back on 820 (msm8996) and at the time I solved it with a patch that enabled CFCFG. And it resurfaced more recently on sdm845. But at the time CFCFG was rejected, iirc because of concern that it would cause problems on other non-qcom arm smmu implementations. And I think I forgot to send this version of the solution. If enabling HUPCF is anticipated to cause problems on other ARM SMMU implementations, I think I can come up with a variant of this patch which conditionally enables it for snapdragon. Either way, I'd really like to get some variant of this fix merged (and probably it would be a good idea for stable kernel branches too), since current behaviour with the GPU means faults turn into a fantastic cascade of fail. drivers/iommu/arm-smmu-regs.h | 1 + drivers/iommu/arm-smmu.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h index a1226e4ab5f8..2291925eb800 100644 --- a/drivers/iommu/arm-smmu-regs.h +++ b/drivers/iommu/arm-smmu-regs.h @@ -178,6 +178,7 @@ enum arm_smmu_s2cr_privcfg { #define ARM_SMMU_CB_ATSR 0x8f0 #define SCTLR_S1_ASIDPNE (1 << 12) +#define SCTLR_HUPCF (1 << 8) #define SCTLR_CFCFG (1 << 7) #define SCTLR_CFIE (1 << 6) #define SCTLR_CFRE (1 << 5) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index f7a96bcf94a6..47ffc9aade72 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -713,9 +713,9 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE | SCTLR_M; if (stage1) reg |= SCTLR_S1_ASIDPNE; + reg |= SCTLR_HUPCF; if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) reg |= SCTLR_E; - writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); }