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Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH 1/3] arm_gic: Mask the un-supported priority bits Date: Fri, 14 Feb 2020 18:46:50 +0530 Message-Id: <1581686212-9625-2-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581686212-9625-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1581686212-9625-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(39860400002)(346002)(136003)(376002)(396003)(199004)(189003)(70586007)(4326008)(110136005)(70206006)(316002)(2906002)(42186006)(336012)(356004)(6666004)(426003)(5660300002)(26005)(186003)(6266002)(2616005)(81166006)(478600001)(8676002)(81156014)(8936002)(36756003); DIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR02MB6044; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; A:1; MX:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 476c6e60-7bdb-4891-5607-08d7b150c47e X-MS-TrafficTypeDiagnostic: DM6PR02MB6044: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:392; X-Forefront-PRVS: 03137AC81E X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YlejLYiRkUVK3ZBOItsWqMXZCEwNVQiGD0LR8kz7ipa4wWWDTFZ3+quUcAw+IbBQ7A84my1Q7hNqlVLp8tTCjEsEC9x1Z+aBRYmJlDvY/bd2Xdex7u/MoY1MHyweiZ61MIT2KpMh1BPGSir6UJ7T2M3QtqeXbMfoW+hl6su4bVut0V4RNdbGINdkRp/QXZg/52Z2J9VZzSYP4gS5PjR0zlaLBGzRM3U+/fIc66GHa9bwYUB2cQiyHTTWZDMjHvfxxjx4Nquawq3614nCFzhH78FgvaiIylZzzV2xG64aXMqJO6DzMHFYzd+iGndMLghE1dEQLLg46No0ZuFkHp9tdNJIqQabQTvVTvd+2WK15ARdqYejJUHafv17btkzYimH8FY7/s94DtyFEpxeT4EnWq/ZUXriRu/SJ8BsHehdlRwqcRI4l3vKfk5/6ol6f97S X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2020 13:21:14.6597 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 476c6e60-7bdb-4891-5607-08d7b150c47e X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6044 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.220.66 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Priority bits implemented in arm-gic can 8 to 4, un-implemented bits are read as zeros(RAZ). Signed-off-by: Sai Pavan Boddu --- hw/intc/arm_gic.c | 9 ++++++--- hw/intc/arm_gic_common.c | 1 + include/hw/intc/arm_gic_common.h | 1 + 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 1d7da7b..8875330 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -43,6 +43,9 @@ } \ } while (0) +#define UMASK(n) \ + ((((1 << n) - 1) << (8 - n)) & 0xFF) + static const uint8_t gic_id_11mpcore[] = { 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; @@ -652,9 +655,9 @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, } if (irq < GIC_INTERNAL) { - s->priority1[irq][cpu] = val; + s->priority1[irq][cpu] = val & UMASK(s->n_prio_bits) ; } else { - s->priority2[(irq) - GIC_INTERNAL] = val; + s->priority2[(irq) - GIC_INTERNAL] = val & UMASK(s->n_prio_bits); } } @@ -684,7 +687,7 @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, return; } } - s->priority_mask[cpu] = pmask; + s->priority_mask[cpu] = pmask & UMASK(s->n_prio_bits); } static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index e6c4fe7..e4668c7 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -357,6 +357,7 @@ static Property arm_gic_common_properties[] = { DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0), /* True if the GIC should implement the virtualization extensions */ DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0), + DEFINE_PROP_UINT32("num-prio-bits", GICState, n_prio_bits, 8), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index b5585fe..6e0d6b8 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -96,6 +96,7 @@ typedef struct GICState { uint16_t priority_mask[GIC_NCPU_VCPU]; uint16_t running_priority[GIC_NCPU_VCPU]; uint16_t current_pending[GIC_NCPU_VCPU]; + uint32_t n_prio_bits; /* If we present the GICv2 without security extensions to a guest, * the guest can configure the GICC_CTLR to configure group 1 binary point From patchwork Fri Feb 14 13:16:51 2020 Content-Type: text/plain; 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Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH 2/3] cpu/a9mpcore: Add num priority bits property Date: Fri, 14 Feb 2020 18:46:51 +0530 Message-Id: <1581686212-9625-3-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581686212-9625-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1581686212-9625-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(396003)(136003)(346002)(376002)(39850400004)(189003)(199004)(478600001)(110136005)(2616005)(26005)(6266002)(186003)(4326008)(336012)(316002)(70206006)(70586007)(81166006)(81156014)(8676002)(42186006)(8936002)(36756003)(356004)(6666004)(5660300002)(2906002)(426003)(42866002); DIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR02MB5549; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; MX:1; A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 22ea4f00-23ac-4881-a674-08d7b150c558 X-MS-TrafficTypeDiagnostic: SN6PR02MB5549: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:119; X-Forefront-PRVS: 03137AC81E X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VHPJDShSk0EN6pRR0KRrRp/l6pi1KEugsTvhsRSL9wsDmvL2KyAzLQ2o13RKpTB1iFIsPehx0mnVMgm/9/TFUs4ATgiLD/7X7Fro/pMCAfivNIXfSEhIgFTu+D/topFqnoQLkHupTbFcDGDvhZNO5jhgRjUt2D6m8abVWa20m7qRZis8mO6KC7UfDAoCSksGV78VGKnygQmNjUi6vg9ci3MF1KczBr3/E39h2oh0ZfsWHPT287UzaBhU9gNnFrH++33Ns9QMcCcKHqw9fIk3q7qxmLmvWhoqizYOzdHXzC5miaSF/OguiplhXOB2/X29toXkDnCQdkiKwVsHKHl40Lb2iBHSTz9wBrpqSEW7mnDBIwp/gLLwXI6kMbk4a1hCiHo94jUwjCvP1g/eOPsbXtjtHhd+CM8vQufPtMX4kZNZBNzB9p+72Vj7wgycuZ4Ti8yjnnh+rGrT8MTnLOa+YcCli/3Ps95qsUnSTsXvS9M= X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2020 13:21:16.0894 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22ea4f00-23ac-4881-a674-08d7b150c558 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5549 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.92.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Set number of priority bits property of gic as guided by machine configuration. Signed-off-by: Sai Pavan Boddu --- hw/cpu/a9mpcore.c | 2 ++ include/hw/cpu/a9mpcore.h | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 1f8bc8a..eb1e752 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -68,6 +68,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-prio-bits", s->n_prio_bits); /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. @@ -167,6 +168,7 @@ static Property a9mp_priv_properties[] = { * Other boards may differ and should set this property appropriately. */ DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), + DEFINE_PROP_UINT32("num-priority-bits", A9MPPrivState, n_prio_bits, 8), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h index 5d67ca2..4f146bd 100644 --- a/include/hw/cpu/a9mpcore.h +++ b/include/hw/cpu/a9mpcore.h @@ -28,6 +28,7 @@ typedef struct A9MPPrivState { uint32_t num_cpu; MemoryRegion container; uint32_t num_irq; + uint32_t n_prio_bits; A9SCUState scu; GICState gic; From patchwork Fri Feb 14 13:16:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Pavan Boddu X-Patchwork-Id: 11382263 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 927DB92A for ; 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Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH 3/3] arm/xilinx_zynq: Set number of priority bits Date: Fri, 14 Feb 2020 18:46:52 +0530 Message-Id: <1581686212-9625-4-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581686212-9625-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1581686212-9625-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(376002)(136003)(396003)(39850400004)(346002)(189003)(199004)(478600001)(4744005)(5660300002)(110136005)(36756003)(42186006)(316002)(6666004)(356004)(26005)(2906002)(186003)(2616005)(426003)(336012)(6266002)(4326008)(8676002)(81166006)(70586007)(81156014)(70206006)(8936002); DIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR02MB5452; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; MX:1; A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d48e064d-89f1-4933-105e-08d7b150c605 X-MS-TrafficTypeDiagnostic: DM6PR02MB5452: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:854; X-Forefront-PRVS: 03137AC81E X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cVeyM3/9/2w2bst//edilmt+gVRX6bWTZut9NNryIthck2+UwIH9HLj9v9OSpBZ4I74Qne7IxGkPCAAw660FQm5t4rLxDXfPHphtDfY2H3pTD6v0WbV8s1eNMngu4MyFs3El8ul6hwK9w8RMywxN2DakRfOCmKaO2B2/23a1uPU23io8w7EfOXODpP2sUyep25hYsGJpVPvqUlXy0OPx+DEQvzy11j5O52wLmGhG/s0x/3nnE+/4qA5DfFxyBelU7zEKledAVVe9dYBShpRzn48maox9TxjRPhxB1uLFZX7u8VRKvSHgF58ayciCwTQ6XeZHFSg1QMlzMzsreehgh42z2m+N4uJ8vPaFcxXgGlBOd6fdEPwRiFoH0Gktmlf6qy73naaRYkYXAkJbOBIhszG2FX5cA5+G1WjzpFxk5k3YfoOllTrInVJk9MLYANrw X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2020 13:21:17.2203 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d48e064d-89f1-4933-105e-08d7b150c605 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5452 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.68.89 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Arm GIC in Zynq SOC implements 5 priority bits i.e bits 7..3. Signed-off-by: Sai Pavan Boddu --- hw/arm/xilinx_zynq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3a0fa5b..7aa43ad 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -214,6 +214,7 @@ static void zynq_init(MachineState *machine) dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", 1); + qdev_prop_set_uint32(dev, "num-priority-bits", 5); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);