From patchwork Wed Feb 19 10:05:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 11390895 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 78A32109A for ; Wed, 19 Feb 2020 10:05:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4828021D56 for ; Wed, 19 Feb 2020 10:05:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zHgvSM9C" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726604AbgBSKFv (ORCPT ); Wed, 19 Feb 2020 05:05:51 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:40541 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726270AbgBSKFu (ORCPT ); Wed, 19 Feb 2020 05:05:50 -0500 Received: by mail-lj1-f193.google.com with SMTP id n18so26387142ljo.7 for ; Wed, 19 Feb 2020 02:05:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=9ex0WUr4F2ykNAf/zHRS2tfhIPnCxChpfveEhtUGkE0=; b=zHgvSM9CWvZNU8ODajadg6jZoZu9I9pM8v7X+PLxpLoQTcpd+p86aAb+pT1GJ8O8kr jnMRWQ7KF/kcg7+AR7mMs4lKVphHwGUEW1O6yoZAzyDuhv5B+zaJAH4bbIBCXYOjMHZ0 AZakDmJDFII1L8ZG8fgsa+wFYd4mxhLOfqvjNDYTgJ8MoGJh0uHLCv9T7EWJd4Ea0da1 Xwxpp14HJvQlCmD0eiDMsgmfoQiZVqdoyPyzHCNUUzFQWp+VyQrP3UmnOLQyVGRfZabR hwR7w+TxFgAEOm5BfYx5pToPWIB8UpW4txFgfhwj5V9R2aqGTT0d0fLKP89aJ2ukZkQt 1zSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=9ex0WUr4F2ykNAf/zHRS2tfhIPnCxChpfveEhtUGkE0=; b=PFVK/E4lo1MkJxrTF3EOCUJobCsC8mXnjtVWw3bt5dlLV1G7Q6zQED6w5HXzHYOGXL cK6pHqgoKB8jnW44Yn4hJd+hwKR089vfSJOdRnZnfdIl5/q2bslZSbEBaepm3HHyARUa FI12sXPrLp/cd0+ozJmj/NSnIUhDm4mzepzDYBb+pvxTpaGMydn1PguWFy1akptUzuXh db0IpucJVCykbGLJ2C8yT+uZjjarQ6dGPvUoaZMHHHMWqe+17iDwvHt1ZLpnvsc+0Ko+ B+f9KkzYBFKwlBzlfcE2DJw1wSALpjebBcL5XBOK4QulPkQeD8OavojPn7IwwdP7KhAV aIdg== X-Gm-Message-State: APjAAAWJFZmAiy6aciWGTre8Q1fEApKTVyr1CzBF7PwODWR80HL618Rr S0cUoPGg0JKia8w/5BUfuthyiGiEUNk= X-Google-Smtp-Source: APXvYqwaCKy7oDhbeUTUddmog8SqP+85G8xRkYZCus5ifHqXA/JQPPz7quKLDtwjJrb8W/sW1ted5A== X-Received: by 2002:a2e:9b12:: with SMTP id u18mr15590604lji.274.1582106748043; Wed, 19 Feb 2020 02:05:48 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id r2sm1079982lff.63.2020.02.19.02.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Feb 2020 02:05:47 -0800 (PST) From: Linus Walleij To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Linus Walleij , devicetree@vger.kernel.org, Rob Herring Subject: [PATCH 1/3 v2] dt-bindings: clock: Create YAML schema for ICST clocks Date: Wed, 19 Feb 2020 11:05:41 +0100 Message-Id: <20200219100543.78424-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The ICST clocks used in the ARM Integrator, Versatile and RealView platforms are updated to use YAML schema, and two new ICST clocks used by the Integrator IM-PD1 logical module are added in the process. Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Add a literal | to preserve formatting in the bindings - Collect Rob's review tag --- .../bindings/clock/arm,syscon-icst.yaml | 102 ++++++++++++++++++ .../bindings/clock/arm-integrator.txt | 34 ------ .../bindings/clock/arm-syscon-icst.txt | 70 ------------ 3 files changed, 102 insertions(+), 104 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml delete mode 100644 Documentation/devicetree/bindings/clock/arm-integrator.txt delete mode 100644 Documentation/devicetree/bindings/clock/arm-syscon-icst.txt diff --git a/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml new file mode 100644 index 000000000000..06c4d84e8c3d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM System Conctroller ICST Clocks + +maintainers: + - Linus Walleij + +description: The ICS525 and ICS307 oscillators are produced by Integrated + Devices Technology (IDT). ARM integrated these oscillators deeply into their + reference designs by adding special control registers that manage such + oscillators to their system controllers. + + The various ARM system controllers contain logic to serialize and initialize + an ICST clock request after a write to the 32 bit register at an offset + into the system controller. Furthermore, to even be able to alter one of + these frequencies, the system controller must first be unlocked by + writing a special token to another offset in the system controller. + + Some ARM hardware contain special versions of the serial interface that only + connects the low 8 bits of the VDW (missing one bit), hardwires RDW to + different values and sometimes also hardwire the output divider. They + therefore have special compatible strings as per this table (the OD value is + the value on the pins, not the resulting output divider). + + In the core modules and logic tiles, the ICST is a configurable clock fed + from a 24 MHz clock on the motherboard (usually the main crystal) used for + generating e.g. video clocks. It is located on the core module and there is + only one of these. This clock node must be a subnode of the core module. + + Hardware variant RDW OD VDW + + Integrator/AP 22 1 Bit 8 0, rest variable + integratorap-cm + + Integrator/AP 46 3 Bit 8 0, rest variable + integratorap-sys + + Integrator/AP 22 or 1 17 or (33 or 25 MHz) + integratorap-pci 14 1 14 + + Integrator/CP 22 variable Bit 8 0, rest variable + integratorcp-cm-core + + Integrator/CP 22 variable Bit 8 0, rest variable + integratorcp-cm-mem + + The ICST oscillator must be provided inside a system controller node. + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - arm,syscon-icst525 + - arm,syscon-icst307 + - arm,syscon-icst525-integratorap-cm + - arm,syscon-icst525-integratorap-sys + - arm,syscon-icst525-integratorap-pci + - arm,syscon-icst525-integratorcp-cm-core + - arm,syscon-icst525-integratorcp-cm-mem + - arm,integrator-cm-auxosc + - arm,versatile-cm-auxosc + - arm,impd-vco1 + - arm,impd-vco2 + + clocks: + description: Parent clock for the ICST VCO + maxItems: 1 + + clock-output-names: + maxItems: 1 + + lock-offset: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Offset to the unlocking register for the oscillator + + vco-offset: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Offset to the VCO register for the oscillator + +required: + - "#clock-cells" + - compatible + - clocks + +examples: + - | + vco1: clock@00 { + compatible = "arm,impd1-vco1"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x00>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/arm-integrator.txt b/Documentation/devicetree/bindings/clock/arm-integrator.txt deleted file mode 100644 index 11f5f95f571b..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-integrator.txt +++ /dev/null @@ -1,34 +0,0 @@ -Clock bindings for ARM Integrator and Versatile Core Module clocks - -Auxiliary Oscillator Clock - -This is a configurable clock fed from a 24 MHz chrystal, -used for generating e.g. video clocks. It is located on the -core module and there is only one of these. - -This clock node *must* be a subnode of the core module, since -it obtains the base address for it's address range from its -parent node. - - -Required properties: -- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc" -- #clock-cells: must be <0> - -Optional properties: -- clocks: parent clock(s) - -Example: - -core-module@10000000 { - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - auxosc: cm_aux_osc@25M { - #clock-cells = <0>; - compatible = "arm,integrator-cm-auxosc"; - clocks = <&xtal24mhz>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt deleted file mode 100644 index 4cd81742038f..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt +++ /dev/null @@ -1,70 +0,0 @@ -ARM System Controller ICST clocks - -The ICS525 and ICS307 oscillators are produced by Integrated Devices -Technology (IDT). ARM integrated these oscillators deeply into their -reference designs by adding special control registers that manage such -oscillators to their system controllers. - -The various ARM system controllers contain logic to serialize and initialize -an ICST clock request after a write to the 32 bit register at an offset -into the system controller. Furthermore, to even be able to alter one of -these frequencies, the system controller must first be unlocked by -writing a special token to another offset in the system controller. - -Some ARM hardware contain special versions of the serial interface that only -connects the low 8 bits of the VDW (missing one bit), hardwires RDW to -different values and sometimes also hardwire the output divider. They -therefore have special compatible strings as per this table (the OD value is -the value on the pins, not the resulting output divider): - -Hardware variant: RDW OD VDW - -Integrator/AP 22 1 Bit 8 0, rest variable -integratorap-cm - -Integrator/AP 46 3 Bit 8 0, rest variable -integratorap-sys - -Integrator/AP 22 or 1 17 or (33 or 25 MHz) -integratorap-pci 14 1 14 - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-core - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-mem - -The ICST oscillator must be provided inside a system controller node. - -Required properties: -- compatible: must be one of - "arm,syscon-icst525" - "arm,syscon-icst307" - "arm,syscon-icst525-integratorap-cm" - "arm,syscon-icst525-integratorap-sys" - "arm,syscon-icst525-integratorap-pci" - "arm,syscon-icst525-integratorcp-cm-core" - "arm,syscon-icst525-integratorcp-cm-mem" -- lock-offset: the offset address into the system controller where the - unlocking register is located -- vco-offset: the offset address into the system controller where the - ICST control register is located (even 32 bit address) -- #clock-cells: must be <0> -- clocks: parent clock, since the ICST needs a parent clock to derive its - frequency from, this attribute is compulsory. - -Example: - -syscon: syscon@10000000 { - compatible = "syscon"; - reg = <0x10000000 0x1000>; - - oscclk0: osc0@c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0c>; - clocks = <&xtal24mhz>; - }; - (...) -}; From patchwork Wed Feb 19 10:05:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 11390897 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A4FC17E0 for ; Wed, 19 Feb 2020 10:05:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1BF5524658 for ; Wed, 19 Feb 2020 10:05:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="z47iOBio" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726609AbgBSKFv (ORCPT ); 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Wed, 19 Feb 2020 02:05:49 -0800 (PST) From: Linus Walleij To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Linus Walleij Subject: [PATCH 2/3 v2] clk: versatile: Export icst_clk_setup() Date: Wed, 19 Feb 2020 11:05:42 +0100 Message-Id: <20200219100543.78424-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219100543.78424-1-linus.walleij@linaro.org> References: <20200219100543.78424-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Export this clock setup method so we can register the IM-PD1 clocks with common code in the next step. Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - New patch to reuse the machinery for properly probing device tree clocks using clk_hw etc. --- drivers/clk/versatile/clk-icst.c | 25 +++++++------------------ drivers/clk/versatile/clk-icst.h | 21 +++++++++++++++++++++ 2 files changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c index fe686f77787f..692be2fd9261 100644 --- a/drivers/clk/versatile/clk-icst.c +++ b/drivers/clk/versatile/clk-icst.c @@ -33,18 +33,6 @@ #define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8) -/** - * enum icst_control_type - the type of ICST control register - */ -enum icst_control_type { - ICST_VERSATILE, /* The standard type, all control bits available */ - ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */ - ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */ - ICST_INTEGRATOR_AP_PCI, /* Odd bit pattern storage */ - ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */ - ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */ -}; - /** * struct clk_icst - ICST VCO clock wrapper * @hw: corresponding clock hardware entry @@ -344,12 +332,12 @@ static const struct clk_ops icst_ops = { .set_rate = icst_set_rate, }; -static struct clk *icst_clk_setup(struct device *dev, - const struct clk_icst_desc *desc, - const char *name, - const char *parent_name, - struct regmap *map, - enum icst_control_type ctype) +struct clk *icst_clk_setup(struct device *dev, + const struct clk_icst_desc *desc, + const char *name, + const char *parent_name, + struct regmap *map, + enum icst_control_type ctype) { struct clk *clk; struct clk_icst *icst; @@ -386,6 +374,7 @@ static struct clk *icst_clk_setup(struct device *dev, return clk; } +EXPORT_SYMBOL_GPL(icst_clk_setup); struct clk *icst_clk_register(struct device *dev, const struct clk_icst_desc *desc, diff --git a/drivers/clk/versatile/clk-icst.h b/drivers/clk/versatile/clk-icst.h index e36ca1a20e90..1206f008c11a 100644 --- a/drivers/clk/versatile/clk-icst.h +++ b/drivers/clk/versatile/clk-icst.h @@ -1,4 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0 */ +struct regmap; + +/** + * enum icst_control_type - the type of ICST control register + */ +enum icst_control_type { + ICST_VERSATILE, /* The standard type, all control bits available */ + ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */ + ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */ + ICST_INTEGRATOR_AP_PCI, /* Odd bit pattern storage */ + ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */ + ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */ +}; + /** * struct clk_icst_desc - descriptor for the ICST VCO * @params: ICST parameters @@ -17,3 +31,10 @@ struct clk *icst_clk_register(struct device *dev, const char *name, const char *parent_name, void __iomem *base); + +struct clk *icst_clk_setup(struct device *dev, + const struct clk_icst_desc *desc, + const char *name, + const char *parent_name, + struct regmap *map, + enum icst_control_type ctype); From patchwork Wed Feb 19 10:05:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 11390899 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4274D92A for ; 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Wed, 19 Feb 2020 02:05:51 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id r2sm1079982lff.63.2020.02.19.02.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Feb 2020 02:05:50 -0800 (PST) From: Linus Walleij To: Michael Turquette , Stephen Boyd Cc: linux-clk@vger.kernel.org, Linus Walleij Subject: [PATCH 3/3 v2] clk: versatile: Add device tree probing for IM-PD1 clocks Date: Wed, 19 Feb 2020 11:05:43 +0100 Message-Id: <20200219100543.78424-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200219100543.78424-1-linus.walleij@linaro.org> References: <20200219100543.78424-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org As we want to move these clocks over to probe from the device tree we add a device tree probing path. The old platform data path will be deleted once we have the device tree overall code in place. Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Drop some __init tagging - Provide MODULE_DEVICE_TABLE() - Rewrote to use the same method with regmap as clk-icst.c - The reuse of clk-icst.c makes the clock probe using hw and then it needs no special handling for clock output names. --- drivers/clk/versatile/clk-icst.h | 1 + drivers/clk/versatile/clk-impd1.c | 79 +++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/drivers/clk/versatile/clk-icst.h b/drivers/clk/versatile/clk-icst.h index 1206f008c11a..1a119ef11066 100644 --- a/drivers/clk/versatile/clk-icst.h +++ b/drivers/clk/versatile/clk-icst.h @@ -11,6 +11,7 @@ enum icst_control_type { ICST_INTEGRATOR_AP_PCI, /* Odd bit pattern storage */ ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */ ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */ + ICST_INTEGRATOR_IM_PD1, /* Like the Versatile, all control bits */ }; /** diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c index 1991f15a5db9..b05da8516d4c 100644 --- a/drivers/clk/versatile/clk-impd1.c +++ b/drivers/clk/versatile/clk-impd1.c @@ -7,7 +7,11 @@ #include #include #include +#include #include +#include +#include +#include #include "icst.h" #include "clk-icst.h" @@ -175,3 +179,78 @@ void integrator_impd1_clk_exit(unsigned int id) kfree(imc->pclkname); } EXPORT_SYMBOL_GPL(integrator_impd1_clk_exit); + +static int integrator_impd1_clk_spawn(struct device *dev, + struct device_node *parent, + struct device_node *np) +{ + struct regmap *map; + struct clk *clk = ERR_PTR(-EINVAL); + const char *name = np->name; + const char *parent_name; + const struct clk_icst_desc *desc; + int ret; + + map = syscon_node_to_regmap(parent); + if (IS_ERR(map)) { + pr_err("no regmap for syscon IM-PD1 ICST clock parent\n"); + return PTR_ERR(map); + } + + if (of_device_is_compatible(np, "arm,impd1-vco1")) { + desc = &impd1_icst1_desc; + } else if (of_device_is_compatible(np, "arm,impd1-vco2")) { + desc = &impd1_icst2_desc; + } else { + dev_err(dev, "not a clock node %s\n", name); + return -ENODEV; + } + + parent_name = of_clk_get_parent_name(np, 0); + clk = icst_clk_setup(NULL, desc, name, parent_name, map, + ICST_INTEGRATOR_IM_PD1); + if (!IS_ERR(clk)) { + of_clk_add_provider(np, of_clk_src_simple_get, clk); + ret = 0; + } else { + dev_err(dev, "error setting up IM-PD1 ICST clock\n"); + ret = PTR_ERR(clk); + } + + return ret; +} + +static int integrator_impd1_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *child; + int ret = 0; + + for_each_available_child_of_node(np, child) { + ret = integrator_impd1_clk_spawn(dev, np, child); + if (ret) + break; + } + + return ret; +} + +static const struct of_device_id impd1_syscon_match[] = { + { .compatible = "arm,im-pd1-syscon", }, + {} +}; +MODULE_DEVICE_TABLE(of, impd1_syscon_match); + +static struct platform_driver impd1_clk_driver = { + .driver = { + .name = "impd1-clk", + .of_match_table = impd1_syscon_match, + }, + .probe = integrator_impd1_clk_probe, +}; +builtin_platform_driver(impd1_clk_driver); + +MODULE_AUTHOR("Linus Walleij "); +MODULE_DESCRIPTION("Arm IM-PD1 module clock driver"); +MODULE_LICENSE("GPL v2");