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Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH v3 1/3] arm_gic: Mask the un-supported priority bits Date: Mon, 24 Feb 2020 15:09:22 +0530 Message-Id: <1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582537164-764-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1582537164-764-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(39860400002)(136003)(376002)(346002)(396003)(199004)(189003)(81156014)(2616005)(8676002)(5660300002)(336012)(81166006)(478600001)(42186006)(426003)(8936002)(110136005)(4326008)(316002)(356004)(2906002)(26005)(6666004)(186003)(70586007)(70206006)(6266002)(36756003)(42866002); DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR02MB2454; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; A:1; MX:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a9196654-731c-4439-e1e8-08d7b90e1d3a X-MS-TrafficTypeDiagnostic: CY4PR02MB2454: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:663; X-Forefront-PRVS: 032334F434 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qPRZY/UVoHSxOllNXxJ3e8de+jy48DfvwzuObViOxB30ITgcoBoWurwmqvx+AiV+ukFAVmy7QIS6YUu3hczkhkoXxHk/ks8nLW4EDHK7FaXP5blBbj5YoYUy5ZZI5u7mi2/n7I4hdYNzQHceSn+FUWxAyln8k61vp64w1VKqDCbuoajcl3GZ/mpOG5NEJ1lx8W1byVcxLhpKX0EBaXJQhFfrib7EjbfN7Lvss6bmOoDGOjgjsBmYp7IDQOHYoqOgrDjQoY3F1yFL9/c6E7YVkQ2VNlYELOK/SRXjOghbxp5+I/JWPY0W2mVuZJsel+wWRjmZ4LSmbebg4rWk9eGIQjYxCLzctrxapcxRSi52w/30eOja+Vqtghv+ucw/dsP8+a8k2d2jGNy7GF9/78mXyQy/FtTzpsItFOXAi89QM0EoqiEN0yydC9e+cRDchq2N9BohCalj2cQfpFOS1Wlyvf4dNmZz9ue+MyuSJU/1YJqEhMmdvW7N5L1rBn8W6Jh/ X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2020 09:44:16.4871 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9196654-731c-4439-e1e8-08d7b90e1d3a X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2454 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 40.107.236.80 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Priority bits implemented in arm-gic can be 8 to 4, un-implemented bits are read as zeros(RAZ). Signed-off-by: Sai Pavan Boddu Suggested-by: Peter Maydell --- hw/intc/arm_gic.c | 33 +++++++++++++++++++++++++++++++-- hw/intc/arm_gic_common.c | 1 + include/hw/intc/arm_gic.h | 2 ++ include/hw/intc/arm_gic_common.h | 1 + 4 files changed, 35 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 1d7da7b..c60dc6b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -641,6 +641,23 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) return ret; } +static uint32_t gic_fullprio_mask(GICState *s, int cpu) +{ + /* + * Return a mask word which clears the unimplemented priority + * bits from a priority value for an interrupt. (Not to be + * confused with the group priority, whose mask depends on BPR.) + */ + int priBits; + + if (gic_is_vcpu(cpu)) { + priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS; + } else { + priBits = s->n_prio_bits; + } + return ~0U << (8 - priBits); +} + void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, MemTxAttrs attrs) { @@ -651,6 +668,8 @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, val = 0x80 | (val >> 1); /* Non-secure view */ } + val &= gic_fullprio_mask(s, cpu); + if (irq < GIC_INTERNAL) { s->priority1[irq][cpu] = val; } else { @@ -669,7 +688,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, } prio = (prio << 1) & 0xff; /* Non-secure view */ } - return prio; + return prio & gic_fullprio_mask(s, cpu); } static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, @@ -684,7 +703,7 @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, return; } } - s->priority_mask[cpu] = pmask; + s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu); } static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) @@ -2055,6 +2074,16 @@ static void arm_gic_realize(DeviceState *dev, Error **errp) return; } + if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS || + (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS : + s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) { + error_setg(errp, "num-priority-bits cannot be greater than %d" + " or less than %d", GIC_MAX_PRIORITY_BITS, + s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS : + GIC_MIN_PRIORITY_BITS); + return; + } + /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if * enabled, virtualization extensions related interfaces (main virtual * interface (s->vifaceiomem[0]) and virtual CPU interface). diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index e6c4fe7..7b44d56 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -357,6 +357,7 @@ static Property arm_gic_common_properties[] = { DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0), /* True if the GIC should implement the virtualization extensions */ DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0), + DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index ed703a1..303b974 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -68,6 +68,8 @@ /* Number of SGI target-list bits */ #define GIC_TARGETLIST_BITS 8 +#define GIC_MAX_PRIORITY_BITS 8 +#define GIC_MIN_PRIORITY_BITS 4 #define TYPE_ARM_GIC "arm_gic" #define ARM_GIC(obj) \ diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index b5585fe..6e0d6b8 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -96,6 +96,7 @@ typedef struct GICState { uint16_t priority_mask[GIC_NCPU_VCPU]; uint16_t running_priority[GIC_NCPU_VCPU]; uint16_t current_pending[GIC_NCPU_VCPU]; + uint32_t n_prio_bits; /* If we present the GICv2 without security extensions to a guest, * the guest can configure the GICC_CTLR to configure group 1 binary point From patchwork Mon Feb 24 09:39:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Pavan Boddu X-Patchwork-Id: 11400067 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 43C7D930 for ; Mon, 24 Feb 2020 09:45:04 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 199AB20836 for ; Mon, 24 Feb 2020 09:45:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="LpudzdZO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 199AB20836 Authentication-Results: mail.kernel.org; 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Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH v3 2/3] cpu/a9mpcore: Set number of GIC priority bits to 5 Date: Mon, 24 Feb 2020 15:09:23 +0530 Message-Id: <1582537164-764-3-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582537164-764-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1582537164-764-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(396003)(136003)(346002)(39860400002)(376002)(189003)(199004)(316002)(356004)(5660300002)(6666004)(2616005)(81166006)(8936002)(26005)(186003)(2906002)(336012)(426003)(6266002)(36756003)(4326008)(42186006)(110136005)(70206006)(70586007)(81156014)(8676002)(478600001); DIR:OUT; SFP:1101; SCL:1; SRVR:MW2PR02MB3820; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; MX:1; A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 02857715-7e0c-4869-3a74-08d7b90e1de0 X-MS-TrafficTypeDiagnostic: MW2PR02MB3820: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:161; X-Forefront-PRVS: 032334F434 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nQRW0BA+xBC4f7O7IJgwmxed3Go3kbYYW1iyiyJZ+Q8XmCZc1IwdjjVaYEJsJKfT4EZ/+5gH/3O/f6liIz6fyz+ktqmN8BzbzjgmRS8WLeyLRpaEUTNc5rboy9NOis7UsjgAYSVgDmRcrTscvk3Yh7PGMguFPFrEaz2i9HhjLTivd/5AYm29OIr/5PSCkuqq11/23EILlq+f8kJmnkS9x4wWNiRD9gyB7CN0m31mkT9jhkWqJocHj7IZLwQ7f2Pthgxtp7/Z1bKQjBD4nWYS0IGk62G7KX/WRH/jtx5pTlq7s/YhhWkJhsMa4iXVuyT1nRlQT3HbobrpNbADxdlG6kYe1fjMttcdGQYpiUGI4249qz0TfbG+Wro7WGOV8Ev/+KVmEMtDcIEPy0DcUtHNVExFYUBiukU4BdLPWaPo8gn/tex5LUNO0DDEiTqNWaDY X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2020 09:44:17.6314 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02857715-7e0c-4869-3a74-08d7b90e1de0 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR02MB3820 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 40.107.237.70 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" All A9 CPUs have a GIC with 5 bits of priority. Signed-off-by: Sai Pavan Boddu Suggested-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/cpu/a9mpcore.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 1f8bc8a..b4f6a7e 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -16,6 +16,8 @@ #include "hw/qdev-properties.h" #include "hw/core/cpu.h" +#define A9_GIC_NUM_PRIORITY_BITS 5 + static void a9mp_priv_set_irq(void *opaque, int irq, int level) { A9MPPrivState *s = (A9MPPrivState *)opaque; @@ -68,6 +70,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + A9_GIC_NUM_PRIORITY_BITS); /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. 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Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH v3 3/3] cpu/arm11mpcore: Set number of GIC priority bits to 4 Date: Mon, 24 Feb 2020 15:09:24 +0530 Message-Id: <1582537164-764-4-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582537164-764-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1582537164-764-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(396003)(346002)(136003)(376002)(39860400002)(199004)(189003)(316002)(110136005)(6266002)(8936002)(81156014)(42186006)(2906002)(426003)(36756003)(8676002)(2616005)(336012)(81166006)(478600001)(6666004)(356004)(5660300002)(26005)(70586007)(4326008)(70206006)(186003); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR02MB5941; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; A:1; MX:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: eccd0ca0-ea91-4f31-448e-08d7b90e1e4c X-MS-TrafficTypeDiagnostic: BYAPR02MB5941: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:78; X-Forefront-PRVS: 032334F434 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: itcAr0mLWVWDDCi/jJeIC99gnJppkAhIsKtOXFGX5Q7OxznIAbFd626oc49Ml86WC8q6DOx2dBax6Xb6UcXwR8zNQAALP2tm7oiLpDF8x+7x5Y7daSHxf0ZHZ16p406XYo7FjDkELWVYrDcCJik3aVGI1lT/5cYPCrJrN0dApJhZeQD6mUo+VRJcz9Qtj7LZSesaQvgvmtwCwNki1PTWMYVpT/vuIo6LoQa0iePKZ4vrLg6fbywT/VpqailLjahxATXK6DkWAnrUbQiRIAXX4o/stljpJvCU1JYblgjTkiyvZSn+KOTvel+TGt8Gmpn7f/SDmcjLuYKCVmLmQW1pJ1XhJYuWFSblc9v+a4z7dWz99eqi7jHz78eTJrdaGLu/pSjIJZ+kDgPVjGpMlyiuqECWTgxKz65EmqU5CnrTgGRndPoykkfTXeT3ji6XALCg X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2020 09:44:18.3928 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eccd0ca0-ea91-4f31-448e-08d7b90e1e4c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR02MB5941 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 40.107.244.73 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" ARM11MPCore GIC is implemented with 4 priority bits. Signed-off-by: Sai Pavan Boddu Suggested-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/cpu/arm11mpcore.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 2e3e87c..ab9fadb 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -15,6 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" +#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4 static void mpcore_priv_set_irq(void *opaque, int irq, int level) { @@ -86,6 +87,10 @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp) qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + ARM11MPCORE_NUM_GIC_PRIORITY_BITS); + + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err != NULL) { error_propagate(errp, err);