From patchwork Thu Feb 27 10:56:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11408289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 564101871 for ; Thu, 27 Feb 2020 10:57:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1F58C24696 for ; Thu, 27 Feb 2020 10:57:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="pVo0nxDf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728924AbgB0K5L (ORCPT ); Thu, 27 Feb 2020 05:57:11 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:26749 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728897AbgB0K5K (ORCPT ); Thu, 27 Feb 2020 05:57:10 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1582801029; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=omZC7DiNsaT1afZqvoRn1/oXnO2bPazwbX9RKy0OMso=; b=pVo0nxDfx68Iw49ujvwl2aASMcbHpjTEUwAxH1sEpUcSkkQlVWqlLv86Ra/ChgjSI7FlacK2 JqH9Tzr8D2gyXyvHxv8J4J0do6ZDBE2PDnMqjM3uBqpclscTBff14EM0WzrMpz4msQCbdIWk TH3Ul8Y6B7WHxUBmTp4kpVQsWTY= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e57a074.7f5dc307cdc0-smtp-out-n02; Thu, 27 Feb 2020 10:56:52 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id EE756C4479D; Thu, 27 Feb 2020 10:56:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.2 required=2.0 tests=ALL_TRUSTED,SPF_NONE, UPPERCASE_50_75,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8CFC6C447A2; Thu, 27 Feb 2020 10:56:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8CFC6C447A2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: robh+dt@kernel.org, georgi.djakov@linaro.org, evgreen@chromium.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, mark.rutland@arm.com, saravanak@google.com, viresh.kumar@linaro.org, okukatla@codeaurora.org, Sibi Sankar Subject: [PATCH v5 1/7] interconnect: qcom: Allow icc node to be used across icc providers Date: Thu, 27 Feb 2020 16:26:25 +0530 Message-Id: <20200227105632.15041-2-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200227105632.15041-1-sibis@codeaurora.org> References: <20200227105632.15041-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move the icc node ids to a common header, this will allow for referencing/linking of icc nodes to multiple icc providers on SDM845 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Evan Green --- drivers/interconnect/qcom/sdm845.c | 134 +-------------------------- drivers/interconnect/qcom/sdm845.h | 140 +++++++++++++++++++++++++++++ 2 files changed, 141 insertions(+), 133 deletions(-) create mode 100644 drivers/interconnect/qcom/sdm845.h diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index ab968afeee594..b013b80caa452 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -13,139 +13,7 @@ #include "bcm-voter.h" #include "icc-rpmh.h" - -enum { - SDM845_MASTER_A1NOC_CFG = 1, - SDM845_MASTER_BLSP_1, - SDM845_MASTER_TSIF, - SDM845_MASTER_SDCC_2, - SDM845_MASTER_SDCC_4, - SDM845_MASTER_UFS_CARD, - SDM845_MASTER_UFS_MEM, - SDM845_MASTER_PCIE_0, - SDM845_MASTER_A2NOC_CFG, - SDM845_MASTER_QDSS_BAM, - SDM845_MASTER_BLSP_2, - SDM845_MASTER_CNOC_A2NOC, - SDM845_MASTER_CRYPTO, - SDM845_MASTER_IPA, - SDM845_MASTER_PCIE_1, - SDM845_MASTER_QDSS_ETR, - SDM845_MASTER_USB3_0, - SDM845_MASTER_USB3_1, - SDM845_MASTER_CAMNOC_HF0_UNCOMP, - SDM845_MASTER_CAMNOC_HF1_UNCOMP, - SDM845_MASTER_CAMNOC_SF_UNCOMP, - SDM845_MASTER_SPDM, - SDM845_MASTER_TIC, - SDM845_MASTER_SNOC_CNOC, - SDM845_MASTER_QDSS_DAP, - SDM845_MASTER_CNOC_DC_NOC, - SDM845_MASTER_APPSS_PROC, - SDM845_MASTER_GNOC_CFG, - SDM845_MASTER_LLCC, - SDM845_MASTER_TCU_0, - SDM845_MASTER_MEM_NOC_CFG, - SDM845_MASTER_GNOC_MEM_NOC, - SDM845_MASTER_MNOC_HF_MEM_NOC, - SDM845_MASTER_MNOC_SF_MEM_NOC, - SDM845_MASTER_SNOC_GC_MEM_NOC, - SDM845_MASTER_SNOC_SF_MEM_NOC, - SDM845_MASTER_GFX3D, - SDM845_MASTER_CNOC_MNOC_CFG, - SDM845_MASTER_CAMNOC_HF0, - SDM845_MASTER_CAMNOC_HF1, - SDM845_MASTER_CAMNOC_SF, - SDM845_MASTER_MDP0, - SDM845_MASTER_MDP1, - SDM845_MASTER_ROTATOR, - SDM845_MASTER_VIDEO_P0, - SDM845_MASTER_VIDEO_P1, - SDM845_MASTER_VIDEO_PROC, - SDM845_MASTER_SNOC_CFG, - SDM845_MASTER_A1NOC_SNOC, - SDM845_MASTER_A2NOC_SNOC, - SDM845_MASTER_GNOC_SNOC, - SDM845_MASTER_MEM_NOC_SNOC, - SDM845_MASTER_ANOC_PCIE_SNOC, - SDM845_MASTER_PIMEM, - SDM845_MASTER_GIC, - SDM845_SLAVE_A1NOC_SNOC, - SDM845_SLAVE_SERVICE_A1NOC, - SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, - SDM845_SLAVE_A2NOC_SNOC, - SDM845_SLAVE_ANOC_PCIE_SNOC, - SDM845_SLAVE_SERVICE_A2NOC, - SDM845_SLAVE_CAMNOC_UNCOMP, - SDM845_SLAVE_A1NOC_CFG, - SDM845_SLAVE_A2NOC_CFG, - SDM845_SLAVE_AOP, - SDM845_SLAVE_AOSS, - SDM845_SLAVE_CAMERA_CFG, - SDM845_SLAVE_CLK_CTL, - SDM845_SLAVE_CDSP_CFG, - SDM845_SLAVE_RBCPR_CX_CFG, - SDM845_SLAVE_CRYPTO_0_CFG, - SDM845_SLAVE_DCC_CFG, - SDM845_SLAVE_CNOC_DDRSS, - SDM845_SLAVE_DISPLAY_CFG, - SDM845_SLAVE_GLM, - SDM845_SLAVE_GFX3D_CFG, - SDM845_SLAVE_IMEM_CFG, - SDM845_SLAVE_IPA_CFG, - SDM845_SLAVE_CNOC_MNOC_CFG, - SDM845_SLAVE_PCIE_0_CFG, - SDM845_SLAVE_PCIE_1_CFG, - SDM845_SLAVE_PDM, - SDM845_SLAVE_SOUTH_PHY_CFG, - SDM845_SLAVE_PIMEM_CFG, - SDM845_SLAVE_PRNG, - SDM845_SLAVE_QDSS_CFG, - SDM845_SLAVE_BLSP_2, - SDM845_SLAVE_BLSP_1, - SDM845_SLAVE_SDCC_2, - SDM845_SLAVE_SDCC_4, - SDM845_SLAVE_SNOC_CFG, - SDM845_SLAVE_SPDM_WRAPPER, - SDM845_SLAVE_SPSS_CFG, - SDM845_SLAVE_TCSR, - SDM845_SLAVE_TLMM_NORTH, - SDM845_SLAVE_TLMM_SOUTH, - SDM845_SLAVE_TSIF, - SDM845_SLAVE_UFS_CARD_CFG, - SDM845_SLAVE_UFS_MEM_CFG, - SDM845_SLAVE_USB3_0, - SDM845_SLAVE_USB3_1, - SDM845_SLAVE_VENUS_CFG, - SDM845_SLAVE_VSENSE_CTRL_CFG, - SDM845_SLAVE_CNOC_A2NOC, - SDM845_SLAVE_SERVICE_CNOC, - SDM845_SLAVE_LLCC_CFG, - SDM845_SLAVE_MEM_NOC_CFG, - SDM845_SLAVE_GNOC_SNOC, - SDM845_SLAVE_GNOC_MEM_NOC, - SDM845_SLAVE_SERVICE_GNOC, - SDM845_SLAVE_EBI1, - SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, - SDM845_SLAVE_MEM_NOC_GNOC, - SDM845_SLAVE_LLCC, - SDM845_SLAVE_MEM_NOC_SNOC, - SDM845_SLAVE_SERVICE_MEM_NOC, - SDM845_SLAVE_MNOC_SF_MEM_NOC, - SDM845_SLAVE_MNOC_HF_MEM_NOC, - SDM845_SLAVE_SERVICE_MNOC, - SDM845_SLAVE_APPSS, - SDM845_SLAVE_SNOC_CNOC, - SDM845_SLAVE_SNOC_MEM_NOC_GC, - SDM845_SLAVE_SNOC_MEM_NOC_SF, - SDM845_SLAVE_IMEM, - SDM845_SLAVE_PCIE_0, - SDM845_SLAVE_PCIE_1, - SDM845_SLAVE_PIMEM, - SDM845_SLAVE_SERVICE_SNOC, - SDM845_SLAVE_QDSS_STM, - SDM845_SLAVE_TCU -}; +#include "sdm845.h" DEFINE_QNODE(qhm_a1noc_cfg, SDM845_MASTER_A1NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A1NOC); DEFINE_QNODE(qhm_qup1, SDM845_MASTER_BLSP_1, 1, 4, SDM845_SLAVE_A1NOC_SNOC); diff --git a/drivers/interconnect/qcom/sdm845.h b/drivers/interconnect/qcom/sdm845.h new file mode 100644 index 0000000000000..bc7e425ce9852 --- /dev/null +++ b/drivers/interconnect/qcom/sdm845.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ +#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ + +#define SDM845_MASTER_A1NOC_CFG 1 +#define SDM845_MASTER_BLSP_1 2 +#define SDM845_MASTER_TSIF 3 +#define SDM845_MASTER_SDCC_2 4 +#define SDM845_MASTER_SDCC_4 5 +#define SDM845_MASTER_UFS_CARD 6 +#define SDM845_MASTER_UFS_MEM 7 +#define SDM845_MASTER_PCIE_0 8 +#define SDM845_MASTER_A2NOC_CFG 9 +#define SDM845_MASTER_QDSS_BAM 10 +#define SDM845_MASTER_BLSP_2 11 +#define SDM845_MASTER_CNOC_A2NOC 12 +#define SDM845_MASTER_CRYPTO 13 +#define SDM845_MASTER_IPA 14 +#define SDM845_MASTER_PCIE_1 15 +#define SDM845_MASTER_QDSS_ETR 16 +#define SDM845_MASTER_USB3_0 17 +#define SDM845_MASTER_USB3_1 18 +#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19 +#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20 +#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21 +#define SDM845_MASTER_SPDM 22 +#define SDM845_MASTER_TIC 23 +#define SDM845_MASTER_SNOC_CNOC 24 +#define SDM845_MASTER_QDSS_DAP 25 +#define SDM845_MASTER_CNOC_DC_NOC 26 +#define SDM845_MASTER_APPSS_PROC 27 +#define SDM845_MASTER_GNOC_CFG 28 +#define SDM845_MASTER_LLCC 29 +#define SDM845_MASTER_TCU_0 30 +#define SDM845_MASTER_MEM_NOC_CFG 31 +#define SDM845_MASTER_GNOC_MEM_NOC 32 +#define SDM845_MASTER_MNOC_HF_MEM_NOC 33 +#define SDM845_MASTER_MNOC_SF_MEM_NOC 34 +#define SDM845_MASTER_SNOC_GC_MEM_NOC 35 +#define SDM845_MASTER_SNOC_SF_MEM_NOC 36 +#define SDM845_MASTER_GFX3D 37 +#define SDM845_MASTER_CNOC_MNOC_CFG 38 +#define SDM845_MASTER_CAMNOC_HF0 39 +#define SDM845_MASTER_CAMNOC_HF1 40 +#define SDM845_MASTER_CAMNOC_SF 41 +#define SDM845_MASTER_MDP0 42 +#define SDM845_MASTER_MDP1 43 +#define SDM845_MASTER_ROTATOR 44 +#define SDM845_MASTER_VIDEO_P0 45 +#define SDM845_MASTER_VIDEO_P1 46 +#define SDM845_MASTER_VIDEO_PROC 47 +#define SDM845_MASTER_SNOC_CFG 48 +#define SDM845_MASTER_A1NOC_SNOC 49 +#define SDM845_MASTER_A2NOC_SNOC 50 +#define SDM845_MASTER_GNOC_SNOC 51 +#define SDM845_MASTER_MEM_NOC_SNOC 52 +#define SDM845_MASTER_ANOC_PCIE_SNOC 53 +#define SDM845_MASTER_PIMEM 54 +#define SDM845_MASTER_GIC 55 +#define SDM845_SLAVE_A1NOC_SNOC 56 +#define SDM845_SLAVE_SERVICE_A1NOC 57 +#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58 +#define SDM845_SLAVE_A2NOC_SNOC 59 +#define SDM845_SLAVE_ANOC_PCIE_SNOC 60 +#define SDM845_SLAVE_SERVICE_A2NOC 61 +#define SDM845_SLAVE_CAMNOC_UNCOMP 62 +#define SDM845_SLAVE_A1NOC_CFG 63 +#define SDM845_SLAVE_A2NOC_CFG 64 +#define SDM845_SLAVE_AOP 65 +#define SDM845_SLAVE_AOSS 66 +#define SDM845_SLAVE_CAMERA_CFG 67 +#define SDM845_SLAVE_CLK_CTL 68 +#define SDM845_SLAVE_CDSP_CFG 69 +#define SDM845_SLAVE_RBCPR_CX_CFG 70 +#define SDM845_SLAVE_CRYPTO_0_CFG 71 +#define SDM845_SLAVE_DCC_CFG 72 +#define SDM845_SLAVE_CNOC_DDRSS 73 +#define SDM845_SLAVE_DISPLAY_CFG 74 +#define SDM845_SLAVE_GLM 75 +#define SDM845_SLAVE_GFX3D_CFG 76 +#define SDM845_SLAVE_IMEM_CFG 77 +#define SDM845_SLAVE_IPA_CFG 78 +#define SDM845_SLAVE_CNOC_MNOC_CFG 79 +#define SDM845_SLAVE_PCIE_0_CFG 80 +#define SDM845_SLAVE_PCIE_1_CFG 81 +#define SDM845_SLAVE_PDM 82 +#define SDM845_SLAVE_SOUTH_PHY_CFG 83 +#define SDM845_SLAVE_PIMEM_CFG 84 +#define SDM845_SLAVE_PRNG 85 +#define SDM845_SLAVE_QDSS_CFG 86 +#define SDM845_SLAVE_BLSP_2 87 +#define SDM845_SLAVE_BLSP_1 88 +#define SDM845_SLAVE_SDCC_2 89 +#define SDM845_SLAVE_SDCC_4 90 +#define SDM845_SLAVE_SNOC_CFG 91 +#define SDM845_SLAVE_SPDM_WRAPPER 92 +#define SDM845_SLAVE_SPSS_CFG 93 +#define SDM845_SLAVE_TCSR 94 +#define SDM845_SLAVE_TLMM_NORTH 95 +#define SDM845_SLAVE_TLMM_SOUTH 96 +#define SDM845_SLAVE_TSIF 97 +#define SDM845_SLAVE_UFS_CARD_CFG 98 +#define SDM845_SLAVE_UFS_MEM_CFG 99 +#define SDM845_SLAVE_USB3_0 100 +#define SDM845_SLAVE_USB3_1 101 +#define SDM845_SLAVE_VENUS_CFG 102 +#define SDM845_SLAVE_VSENSE_CTRL_CFG 103 +#define SDM845_SLAVE_CNOC_A2NOC 104 +#define SDM845_SLAVE_SERVICE_CNOC 105 +#define SDM845_SLAVE_LLCC_CFG 106 +#define SDM845_SLAVE_MEM_NOC_CFG 107 +#define SDM845_SLAVE_GNOC_SNOC 108 +#define SDM845_SLAVE_GNOC_MEM_NOC 109 +#define SDM845_SLAVE_SERVICE_GNOC 110 +#define SDM845_SLAVE_EBI1 111 +#define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112 +#define SDM845_SLAVE_MEM_NOC_GNOC 113 +#define SDM845_SLAVE_LLCC 114 +#define SDM845_SLAVE_MEM_NOC_SNOC 115 +#define SDM845_SLAVE_SERVICE_MEM_NOC 116 +#define SDM845_SLAVE_MNOC_SF_MEM_NOC 117 +#define SDM845_SLAVE_MNOC_HF_MEM_NOC 118 +#define SDM845_SLAVE_SERVICE_MNOC 119 +#define SDM845_SLAVE_APPSS 120 +#define SDM845_SLAVE_SNOC_CNOC 121 +#define SDM845_SLAVE_SNOC_MEM_NOC_GC 122 +#define SDM845_SLAVE_SNOC_MEM_NOC_SF 123 +#define SDM845_SLAVE_IMEM 124 +#define SDM845_SLAVE_PCIE_0 125 +#define SDM845_SLAVE_PCIE_1 126 +#define SDM845_SLAVE_PIMEM 127 +#define SDM845_SLAVE_SERVICE_SNOC 128 +#define SDM845_SLAVE_QDSS_STM 129 +#define SDM845_SLAVE_TCU 130 + +#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */ From patchwork Thu Feb 27 10:56:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11408287 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 68DF818E8 for ; Thu, 27 Feb 2020 10:56:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 47CE92469C for ; Thu, 27 Feb 2020 10:56:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="FND70Gqc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728844AbgB0K45 (ORCPT ); Thu, 27 Feb 2020 05:56:57 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:26749 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728898AbgB0K45 (ORCPT ); Thu, 27 Feb 2020 05:56:57 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1582801016; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=YsHjlonfTawc11k0NKFr1lH8SI4iq6HyNmIKXxEBAfQ=; b=FND70GqcnbBEWqGD5wk2KyVpNwAbd6IlNGtyFHCNLxJqXMA0Uo2s2gOwktMMFh7Zolcuw+nq B4rKEO1gXt1tMOpAo6c6cbjwwRppApJJEC5AJaGSU/0BDZNDTPd1vFrQmiDSflaPJT9tTNAo u0rMWRn9jHqAovHl7Sl1GtCcNjI= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e57a078.7fe2ee3ad8f0-smtp-out-n01; Thu, 27 Feb 2020 10:56:56 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id CA13CC4479D; Thu, 27 Feb 2020 10:56:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id F1C37C4479F; Thu, 27 Feb 2020 10:56:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org F1C37C4479F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: robh+dt@kernel.org, georgi.djakov@linaro.org, evgreen@chromium.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, mark.rutland@arm.com, saravanak@google.com, viresh.kumar@linaro.org, okukatla@codeaurora.org, Sibi Sankar , Rob Herring Subject: [PATCH v5 2/7] dt-bindings: interconnect: Add OSM L3 DT bindings Date: Thu, 27 Feb 2020 16:26:26 +0530 Message-Id: <20200227105632.15041-3-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200227105632.15041-1-sibis@codeaurora.org> References: <20200227105632.15041-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for Operating State Manager (OSM) L3 interconnect provider on SDM845 SoCs. Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar --- .../bindings/interconnect/qcom,osm-l3.yaml | 61 +++++++++++++++++++ .../dt-bindings/interconnect/qcom,osm-l3.h | 12 ++++ 2 files changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml create mode 100644 include/dt-bindings/interconnect/qcom,osm-l3.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file mode 100644 index 0000000000000..b4d46a1e92573 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider + +maintainers: + - Sibi Sankar + +description: + L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. + The OSM L3 interconnect provider aggregates the L3 bandwidth requests + from CPU/GPU and relays it to the OSM. + +properties: + compatible: + enum: + - qcom,sdm845-osm-l3 + + reg: + maxItems: 1 + + clocks: + items: + - description: xo clock + - description: alternate clock + + clock-names: + items: + - const: xo + - const: alternate + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + + #define GPLL0 165 + #define RPMH_CXO_CLK 0 + + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm845-osm-l3"; + reg = <0x17d41000 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h new file mode 100644 index 0000000000000..54858ff7674d7 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H + +#define MASTER_OSM_L3_APPS 0 +#define SLAVE_OSM_L3 1 + +#endif From patchwork Thu Feb 27 10:56:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11408297 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 227D01871 for ; Thu, 27 Feb 2020 10:57:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E431D24696 for ; Thu, 27 Feb 2020 10:57:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="MaMVW4g2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728976AbgB0K5T (ORCPT ); Thu, 27 Feb 2020 05:57:19 -0500 Received: from mail27.static.mailgun.info ([104.130.122.27]:56060 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728953AbgB0K5T (ORCPT ); Thu, 27 Feb 2020 05:57:19 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1582801038; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=MxQlZ4GTP7kLupOxgpFSaUSjW6GKWa9G/wpVdD/vcsQ=; b=MaMVW4g2XX25IwUwyR75wuLH0o94XNlJLzutCBOQOggKXLhB5+XF6BrBDBEnO75wMvYo/iYS raiUf/mfbinnS3IgYS8H1oybB/S0EfAa9q5TqCFFnS32KJZvNoiPVORDj33rif6mIv3caDah YeiDxRJhsveO1njkdDYGU6M/CvM= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e57a07f.7fee95e10228-smtp-out-n01; Thu, 27 Feb 2020 10:57:03 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 5388DC447AA; Thu, 27 Feb 2020 10:57:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9EFEAC447A0; Thu, 27 Feb 2020 10:56:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9EFEAC447A0 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: robh+dt@kernel.org, georgi.djakov@linaro.org, evgreen@chromium.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, mark.rutland@arm.com, saravanak@google.com, viresh.kumar@linaro.org, okukatla@codeaurora.org, Sibi Sankar Subject: [PATCH v5 3/7] interconnect: qcom: Add OSM L3 interconnect provider support Date: Thu, 27 Feb 2020 16:26:27 +0530 Message-Id: <20200227105632.15041-4-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200227105632.15041-1-sibis@codeaurora.org> References: <20200227105632.15041-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On some Qualcomm SoCs, Operating State Manager (OSM) controls the resources of scaling L3 caches. Add a driver to handle bandwidth requests to OSM L3 from CPU on SDM845 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Evan Green --- drivers/interconnect/qcom/Kconfig | 7 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/osm-l3.c | 261 +++++++++++++++++++++++++++++ drivers/interconnect/qcom/sdm845.h | 2 + 4 files changed, 272 insertions(+) create mode 100644 drivers/interconnect/qcom/osm-l3.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index c8e74b0038c49..35402376427f4 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -28,6 +28,13 @@ config INTERCONNECT_QCOM_MSM8974 This is a driver for the Qualcomm Network-on-Chip on msm8974-based platforms. +config INTERCONNECT_QCOM_OSM_L3 + tristate "Qualcomm OSM L3 interconnect driver" + depends on INTERCONNECT_QCOM || COMPILE_TEST + help + Say y here to support the Operating State Manager (OSM) interconnect + driver which controls the scaling of L3 caches on Qualcomm SoCs. + config INTERCONNECT_QCOM_QCS404 tristate "Qualcomm QCS404 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 532555812ef61..3a047fe6e45a2 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -3,6 +3,7 @@ icc-bcm-voter-objs := bcm-voter.o qnoc-msm8916-objs := msm8916.o qnoc-msm8974-objs := msm8974.o +icc-osm-l3-objs := osm-l3.o qnoc-qcs404-objs := qcs404.o icc-rpmh-obj := icc-rpmh.o qnoc-sc7180-objs := sc7180.o @@ -12,6 +13,7 @@ icc-smd-rpm-objs := smd-rpm.o obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o +obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c new file mode 100644 index 0000000000000..bbf8133195972 --- /dev/null +++ b/drivers/interconnect/qcom/osm-l3.c @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "sdm845.h" + +#define LUT_MAX_ENTRIES 40U +#define LUT_SRC GENMASK(31, 30) +#define LUT_L_VAL GENMASK(7, 0) +#define LUT_ROW_SIZE 32 +#define CLK_HW_DIV 2 + +/* Register offsets */ +#define REG_ENABLE 0x0 +#define REG_FREQ_LUT 0x110 +#define REG_PERF_STATE 0x920 + +#define OSM_L3_MAX_LINKS 1 + +#define to_qcom_provider(_provider) \ + container_of(_provider, struct qcom_osm_l3_icc_provider, provider) + +struct qcom_osm_l3_icc_provider { + void __iomem *base; + unsigned int max_state; + unsigned long lut_tables[LUT_MAX_ENTRIES]; + struct icc_provider provider; +}; + +/** + * struct qcom_icc_node - Qualcomm specific interconnect nodes + * @name: the node name used in debugfs + * @links: an array of nodes where we can go next while traversing + * @id: a unique node identifier + * @num_links: the total number of @links + * @buswidth: width of the interconnect between a node and the bus + */ +struct qcom_icc_node { + const char *name; + u16 links[OSM_L3_MAX_LINKS]; + u16 id; + u16 num_links; + u16 buswidth; +}; + +struct qcom_icc_desc { + struct qcom_icc_node **nodes; + size_t num_nodes; +}; + +#define DEFINE_QNODE(_name, _id, _buswidth, ...) \ + static struct qcom_icc_node _name = { \ + .name = #_name, \ + .id = _id, \ + .buswidth = _buswidth, \ + .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .links = { __VA_ARGS__ }, \ + } + +DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3); +DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16); + +static struct qcom_icc_node *sdm845_osm_l3_nodes[] = { + [MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3, + [SLAVE_OSM_L3] = &sdm845_osm_l3, +}; + +const static struct qcom_icc_desc sdm845_icc_osm_l3 = { + .nodes = sdm845_osm_l3_nodes, + .num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes), +}; + +static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct qcom_osm_l3_icc_provider *qp; + struct icc_provider *provider; + struct qcom_icc_node *qn; + struct icc_node *n; + unsigned int index; + u32 agg_peak = 0; + u32 agg_avg = 0; + u64 rate; + + qn = src->data; + provider = src->provider; + qp = to_qcom_provider(provider); + + list_for_each_entry(n, &provider->nodes, node_list) + provider->aggregate(n, 0, n->avg_bw, n->peak_bw, + &agg_avg, &agg_peak); + + rate = max(agg_avg, agg_peak); + rate = icc_units_to_bps(rate); + do_div(rate, qn->buswidth); + + for (index = 0; index < qp->max_state - 1; index++) { + if (qp->lut_tables[index] >= rate) + break; + } + + writel_relaxed(index, qp->base + REG_PERF_STATE); + + return 0; +} + +static int qcom_osm_l3_remove(struct platform_device *pdev) +{ + struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev); + + icc_nodes_remove(&qp->provider); + return icc_provider_del(&qp->provider); +} + +static int qcom_osm_l3_probe(struct platform_device *pdev) +{ + u32 info, src, lval, i, prev_freq = 0, freq; + static unsigned long hw_rate, xo_rate; + struct qcom_osm_l3_icc_provider *qp; + const struct qcom_icc_desc *desc; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct qcom_icc_node **qnodes; + struct icc_node *node; + size_t num_nodes; + struct clk *clk; + int ret; + + clk = clk_get(&pdev->dev, "xo"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + xo_rate = clk_get_rate(clk); + clk_put(clk); + + clk = clk_get(&pdev->dev, "alternate"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + hw_rate = clk_get_rate(clk) / CLK_HW_DIV; + clk_put(clk); + + qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); + if (!qp) + return -ENOMEM; + + qp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(qp->base)) + return PTR_ERR(qp->base); + + /* HW should be in enabled state to proceed */ + if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) { + dev_err(&pdev->dev, "error hardware not enabled\n"); + return -ENODEV; + } + + for (i = 0; i < LUT_MAX_ENTRIES; i++) { + info = readl_relaxed(qp->base + REG_FREQ_LUT + + i * LUT_ROW_SIZE); + src = FIELD_GET(LUT_SRC, info); + lval = FIELD_GET(LUT_L_VAL, info); + if (src) + freq = xo_rate * lval; + else + freq = hw_rate; + + /* Two of the same frequencies signify end of table */ + if (i > 0 && prev_freq == freq) + break; + + dev_dbg(&pdev->dev, "index=%d freq=%d\n", i, freq); + + qp->lut_tables[i] = freq; + prev_freq = freq; + } + qp->max_state = i; + + desc = device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + qnodes = desc->nodes; + num_nodes = desc->num_nodes; + + data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL); + if (!data) + return -ENOMEM; + + provider = &qp->provider; + provider->dev = &pdev->dev; + provider->set = qcom_icc_set; + provider->aggregate = icc_std_aggregate; + provider->xlate = of_icc_xlate_onecell; + INIT_LIST_HEAD(&provider->nodes); + provider->data = data; + + ret = icc_provider_add(provider); + if (ret) { + dev_err(&pdev->dev, "error adding interconnect provider\n"); + return ret; + } + + for (i = 0; i < num_nodes; i++) { + size_t j; + + node = icc_node_create(qnodes[i]->id); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + goto err; + } + + node->name = qnodes[i]->name; + node->data = qnodes[i]; + icc_node_add(node, provider); + + for (j = 0; j < qnodes[i]->num_links; j++) + icc_link_create(node, qnodes[i]->links[j]); + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + platform_set_drvdata(pdev, qp); + + return 0; +err: + icc_nodes_remove(provider); + icc_provider_del(provider); + + return ret; +} + +static const struct of_device_id osm_l3_of_match[] = { + { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, + { } +}; +MODULE_DEVICE_TABLE(of, osm_l3_of_match); + +static struct platform_driver osm_l3_driver = { + .probe = qcom_osm_l3_probe, + .remove = qcom_osm_l3_remove, + .driver = { + .name = "osm-l3", + .of_match_table = osm_l3_of_match, + }, +}; +module_platform_driver(osm_l3_driver); + +MODULE_DESCRIPTION("Qualcomm OSM L3 interconnect driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/sdm845.h b/drivers/interconnect/qcom/sdm845.h index bc7e425ce9852..776e9c2acb278 100644 --- a/drivers/interconnect/qcom/sdm845.h +++ b/drivers/interconnect/qcom/sdm845.h @@ -136,5 +136,7 @@ #define SDM845_SLAVE_SERVICE_SNOC 128 #define SDM845_SLAVE_QDSS_STM 129 #define SDM845_SLAVE_TCU 130 +#define SDM845_MASTER_OSM_L3_APPS 131 +#define SDM845_SLAVE_OSM_L3 132 #endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */ From patchwork Thu Feb 27 10:56:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11408291 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 444D71871 for ; Thu, 27 Feb 2020 10:57:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 22C8F24696 for ; Thu, 27 Feb 2020 10:57:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="d5cekuIQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728927AbgB0K5N (ORCPT ); Thu, 27 Feb 2020 05:57:13 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:17149 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728843AbgB0K5N (ORCPT ); Thu, 27 Feb 2020 05:57:13 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1582801033; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=X5xIANT3iyW2BZTix+SarL9AWfWO2GvM64RQz7gC52Y=; b=d5cekuIQHM/PgcGvBR80irwXv8OQZxu0iYlO0IJgF9w/jicM/NkoumW3397I5wWrR6VIVLHN 4DcOgTeynOiKMj6BvgITqv0M+dHmcxmXLLCBOgWdzE214zp8/871+ff8BeJgKB73vKo8+CYp tP6vIiAUW2pHa5GTWmbKUFFAp6U= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e57a082.7eff5beaa7a0-smtp-out-n02; Thu, 27 Feb 2020 10:57:06 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id BC85BC447A0; Thu, 27 Feb 2020 10:57:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 64E28C4479F; Thu, 27 Feb 2020 10:57:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 64E28C4479F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: robh+dt@kernel.org, georgi.djakov@linaro.org, evgreen@chromium.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, mark.rutland@arm.com, saravanak@google.com, viresh.kumar@linaro.org, okukatla@codeaurora.org, Sibi Sankar , Rob Herring Subject: [PATCH v5 4/7] dt-bindings: interconnect: Add OSM L3 DT binding on SC7180 Date: Thu, 27 Feb 2020 16:26:28 +0530 Message-Id: <20200227105632.15041-5-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200227105632.15041-1-sibis@codeaurora.org> References: <20200227105632.15041-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add OSM L3 interconnect provider binding on SC7180 SoCs. Acked-by: Rob Herring Signed-off-by: Sibi Sankar --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index b4d46a1e92573..91f70c9067d12 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - qcom,sc7180-osm-l3 - qcom,sdm845-osm-l3 reg: From patchwork Thu Feb 27 10:56:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11408293 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9DC231805 for ; Thu, 27 Feb 2020 10:57:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A12424696 for ; Thu, 27 Feb 2020 10:57:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="iVoPiNWx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728943AbgB0K5O (ORCPT ); Thu, 27 Feb 2020 05:57:14 -0500 Received: from mail27.static.mailgun.info ([104.130.122.27]:52864 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728897AbgB0K5O (ORCPT ); Thu, 27 Feb 2020 05:57:14 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1582801034; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=bWiblcEWScCJYEfbQMEzjMSpqvKdPVVjBFxBNYRuRKc=; b=iVoPiNWxqYoLKyufvvn+Lz6ri4QX5SunEEDJTWUN1kYocyqaI2d48ZYvPEqtdqgbm7mZkZDC wNcxW7qp124HDxzbDjO3qOIreu8ZYQdt8SfIXa7HyfG1SxYyHFqNuzaIiBtUxW+YPvwV/rNO sUDI4jEG+DIZf6vo/zPTX247OXA= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e57a086.7fee9b1a3d50-smtp-out-n01; Thu, 27 Feb 2020 10:57:10 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id E9DC3C447A9; Thu, 27 Feb 2020 10:57:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4C8F0C4479D; Thu, 27 Feb 2020 10:57:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4C8F0C4479D Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: robh+dt@kernel.org, georgi.djakov@linaro.org, evgreen@chromium.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, mark.rutland@arm.com, saravanak@google.com, viresh.kumar@linaro.org, okukatla@codeaurora.org, Sibi Sankar Subject: [PATCH v5 5/7] interconnect: qcom: Add OSM L3 support on SC7180 Date: Thu, 27 Feb 2020 16:26:29 +0530 Message-Id: <20200227105632.15041-6-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200227105632.15041-1-sibis@codeaurora.org> References: <20200227105632.15041-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add Operating State Manager (OSM) L3 interconnect provider support on SC7180 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Evan Green --- drivers/interconnect/qcom/osm-l3.c | 15 +++++++++++++++ drivers/interconnect/qcom/sc7180.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index bbf8133195972..a03c6d6833dfc 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -14,6 +14,7 @@ #include +#include "sc7180.h" #include "sdm845.h" #define LUT_MAX_ENTRIES 40U @@ -82,6 +83,19 @@ const static struct qcom_icc_desc sdm845_icc_osm_l3 = { .num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes), }; +DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3); +DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16); + +static struct qcom_icc_node *sc7180_osm_l3_nodes[] = { + [MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3, + [SLAVE_OSM_L3] = &sc7180_osm_l3, +}; + +const static struct qcom_icc_desc sc7180_icc_osm_l3 = { + .nodes = sc7180_osm_l3_nodes, + .num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes), +}; + static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) { struct qcom_osm_l3_icc_provider *qp; @@ -242,6 +256,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) } static const struct of_device_id osm_l3_of_match[] = { + { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 }, { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 }, { } }; diff --git a/drivers/interconnect/qcom/sc7180.h b/drivers/interconnect/qcom/sc7180.h index c2d8388bb8809..c6212a10c2f61 100644 --- a/drivers/interconnect/qcom/sc7180.h +++ b/drivers/interconnect/qcom/sc7180.h @@ -145,5 +145,7 @@ #define SC7180_SLAVE_SERVICE_SNOC 134 #define SC7180_SLAVE_QDSS_STM 135 #define SC7180_SLAVE_TCU 136 +#define SC7180_MASTER_OSM_L3_APPS 137 +#define SC7180_SLAVE_OSM_L3 138 #endif From patchwork Thu Feb 27 10:56:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11408295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 158251871 for ; Thu, 27 Feb 2020 10:57:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E821324696 for ; Thu, 27 Feb 2020 10:57:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="JsjLxqFt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728956AbgB0K5S (ORCPT ); Thu, 27 Feb 2020 05:57:18 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:17149 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728954AbgB0K5S (ORCPT ); Thu, 27 Feb 2020 05:57:18 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1582801037; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=sjA8xjgdSuzT+3bcqBAE9RgoMUeLbDLPxtAnZ/QtR2E=; b=JsjLxqFtT0u1JBCx/UXY15YuNnj2Ip45MOCbLje3DRmgjM0NkJ50OYSw4SWpgRv0WMN2aNUd lOdADz8/9jD6abzMO8BueWbst2qur7CbFxCKkYIqBUQQvfaQpCrOjtRCO49NH6O+987plNqH zjrGBmvV9jeyvb4belC8YJ6AU8Q= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e57a08d.7f8aa3e3c880-smtp-out-n02; Thu, 27 Feb 2020 10:57:17 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id BAF37C43383; Thu, 27 Feb 2020 10:57:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id CC45AC447A0; Thu, 27 Feb 2020 10:57:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CC45AC447A0 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: robh+dt@kernel.org, georgi.djakov@linaro.org, evgreen@chromium.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, mark.rutland@arm.com, saravanak@google.com, viresh.kumar@linaro.org, okukatla@codeaurora.org, Sibi Sankar Subject: [PATCH v5 6/7] arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider Date: Thu, 27 Feb 2020 16:26:30 +0530 Message-Id: <20200227105632.15041-7-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200227105632.15041-1-sibis@codeaurora.org> References: <20200227105632.15041-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add Operation State Manager (OSM) L3 interconnect provider on SDM845 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Evan Green Acked-by: Georgi Djakov --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index ae7d6617d8b87..8105532f6fbde 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -3323,6 +3324,16 @@ frame@17d10000 { }; }; + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm845-osm-l3"; + reg = <0 0x17d41000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@17d43000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; From patchwork Thu Feb 27 10:56:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11408299 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F330C14B4 for ; Thu, 27 Feb 2020 10:57:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D2750246AA for ; Thu, 27 Feb 2020 10:57:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="v3/xtEfp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728762AbgB0K5g (ORCPT ); Thu, 27 Feb 2020 05:57:36 -0500 Received: from mail27.static.mailgun.info ([104.130.122.27]:56060 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728874AbgB0K5g (ORCPT ); Thu, 27 Feb 2020 05:57:36 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1582801055; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=sM+W2Nc7DPEL6NoqIWgydj9LZlnUkC9GPD/SJlw3K2k=; b=v3/xtEfpypudOdC+9boxbhKfp4E6EsWxIWQkTHpHmlARyZqtsgsUXfN1hiTc0t+9BMMdVvLL gn0CiPC/lzJi+VPIgxQkQ85bv4PSWwHq/ZdpXLEDvaAPVo98zlePBCSsU08KmUOHo57QkE1g V4aBqaljdS1/aAPTbTjJ2Z1K1vs= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e57a091.7f8e7c2eea40-smtp-out-n02; Thu, 27 Feb 2020 10:57:21 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id F1259C447AB; Thu, 27 Feb 2020 10:57:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4D0B5C447A6; Thu, 27 Feb 2020 10:57:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4D0B5C447A6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: robh+dt@kernel.org, georgi.djakov@linaro.org, evgreen@chromium.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, mark.rutland@arm.com, saravanak@google.com, viresh.kumar@linaro.org, okukatla@codeaurora.org, Sibi Sankar Subject: [PATCH v5 7/7] arm64: dts: qcom: sc7180: Add OSM L3 interconnect provider Date: Thu, 27 Feb 2020 16:26:31 +0530 Message-Id: <20200227105632.15041-8-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200227105632.15041-1-sibis@codeaurora.org> References: <20200227105632.15041-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Evan Green Acked-by: Georgi Djakov --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3e28f340fa3e6..6997467608107 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -1578,6 +1579,16 @@ apps_bcm_voter: bcm_voter { }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,sc7180-osm-l3"; + reg = <0 0x18321000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18323000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;