From patchwork Thu Feb 27 18:21:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409397 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 807A618E8 for ; Thu, 27 Feb 2020 18:22:23 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 579BB246AE for ; Thu, 27 Feb 2020 18:22:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="VYNTlWHq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 579BB246AE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1477+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id hR3SYY1556264xUZtDIiStpo; Thu, 27 Feb 2020 10:22:23 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web11.137.1582827742765092675 for ; Thu, 27 Feb 2020 10:22:22 -0800 X-Received: by mail.kernel.org (Postfix) id 859C3246B7; Thu, 27 Feb 2020 18:22:22 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 4974B246B6; Thu, 27 Feb 2020 18:22:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4974B246B6 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 02B3830E; Thu, 27 Feb 2020 10:22:22 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 582313F73B; Thu, 27 Feb 2020 10:22:20 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 01/13] arm: dts: calxeda: Basic DT file fixes Date: Thu, 27 Feb 2020 18:21:58 +0000 Message-Id: <20200227182210.89512-2-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: GXfAQrSU4Jrs2vtxjWDycXVdx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827743; bh=TxrgHg1dKM6Bu6fZojyBUGgTbJSuhQtRhskvy3QvYJg=; h=Cc:Date:From:Reply-To:Subject:To; b=VYNTlWHq4vTnzWbPwcHplWLLBadiUc5NQ+cCWUzAh3zpGdmkR3IBocHB+hfqLpP0Gpu KfQuFeJYZL4UARXHh4td110j31sP6pwp6KnGyaUgPUCWhIsdkhnl1Wvvr1PZ1yXBgSf/K hE8atwPrOrkiB9jtog4WKS0wdy2fvwiOW/o= The .dts files for the Calxeda machines are quite old, so carry some sloppy mistakes that the DT schema checker will complain about. Fix those issues, they should not have any effect on functionality. Signed-off-by: Andre Przywara Reviewed-by: Rob Herring --- arch/arm/boot/dts/ecx-2000.dts | 3 --- arch/arm/boot/dts/highbank.dts | 7 ++----- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts index 5651ae6dc969..81eb382b4c23 100644 --- a/arch/arm/boot/dts/ecx-2000.dts +++ b/arch/arm/boot/dts/ecx-2000.dts @@ -13,7 +13,6 @@ compatible = "calxeda,ecx-2000"; #address-cells = <2>; #size-cells = <2>; - clock-ranges; cpus { #address-cells = <1>; @@ -83,8 +82,6 @@ intc: interrupt-controller@fff11000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; interrupt-controller; interrupts = <1 9 0xf04>; reg = <0xfff11000 0x1000>, diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index f4e4dca6f7e7..9e34d1bd7994 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -13,7 +13,6 @@ compatible = "calxeda,highbank"; #address-cells = <1>; #size-cells = <1>; - clock-ranges; cpus { #address-cells = <1>; @@ -96,7 +95,7 @@ }; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x00000000 0xff900000>; @@ -128,14 +127,12 @@ intc: interrupt-controller@fff11000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; interrupt-controller; reg = <0xfff11000 0x1000>, <0xfff10100 0x100>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xfff12000 0x1000>; interrupts = <0 70 4>; From patchwork Thu Feb 27 18:21:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409399 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67BD013A4 for ; Thu, 27 Feb 2020 18:22:25 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2A072246A9 for ; Thu, 27 Feb 2020 18:22:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="Mes0yKCF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2A072246A9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1478+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id NqpyYY1556264xpxuGoum4vx; Thu, 27 Feb 2020 10:22:25 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web11.138.1582827744598237919 for ; Thu, 27 Feb 2020 10:22:24 -0800 X-Received: by mail.kernel.org (Postfix) id 61DA1246AD; Thu, 27 Feb 2020 18:22:24 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 247F7246AA; Thu, 27 Feb 2020 18:22:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 247F7246AA X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D57E34B2; Thu, 27 Feb 2020 10:22:23 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3702D3F73B; Thu, 27 Feb 2020 10:22:22 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 02/13] arm: dts: calxeda: Provide UART clock Date: Thu, 27 Feb 2020 18:21:59 +0000 Message-Id: <20200227182210.89512-3-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: 4FPJdeyVo2jQDLsKfoUpBQgGx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827745; bh=BjZqYCK3fl4eTLU3nVjhnPB12PpY97URmLKn5A0yNIg=; h=Cc:Date:From:Reply-To:Subject:To; b=Mes0yKCF7IvJ/5WpOLfFduGQUbtPHS/++qvtUs62CdGoO6zz8U4ss4IqV0zOcig1KLv FniopqCh3bD5hezvW2lErqdNd9EScampCv77cCprSS2UubnU41WdBXzXk1VTpW3/yHjZ0 J7DL2Szb8ElDoi0Vqo3fX3hxc41ov1WbqvY= The PL011 UART binding requires two clocks to be named in a node. Add the second clock, which is the bus gate, that just gets enabled. Since this is a fixed clock anyway, it doesn't make any difference. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- arch/arm/boot/dts/ecx-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi index 66ee1d34f72b..f819e3328a9e 100644 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ b/arch/arm/boot/dts/ecx-common.dtsi @@ -114,8 +114,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xfff36000 0x1000>; interrupts = <0 20 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; + clocks = <&pclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; smic@fff3a000 { From patchwork Thu Feb 27 18:22:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409401 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2116D14D5 for ; Thu, 27 Feb 2020 18:22:27 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EB523246AA for ; Thu, 27 Feb 2020 18:22:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="h3x4MyK4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EB523246AA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1479+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id ixMCYY1556264xFicH3c7lhq; Thu, 27 Feb 2020 10:22:26 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web12.139.1582827746485661927 for ; Thu, 27 Feb 2020 10:22:26 -0800 X-Received: by mail.kernel.org (Postfix) id 44C9E246AE; Thu, 27 Feb 2020 18:22:26 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 055C82469C; Thu, 27 Feb 2020 18:22:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 055C82469C X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B2C191FB; Thu, 27 Feb 2020 10:22:25 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 155303F73B; Thu, 27 Feb 2020 10:22:23 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 03/13] arm: dts: calxeda: Fix interrupt grouping Date: Thu, 27 Feb 2020 18:22:00 +0000 Message-Id: <20200227182210.89512-4-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: Wy70TM6NoJpeYGHhiZKzTVlMx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827746; bh=YHI+nQmvne0roHr7w7lFMxL8EM3xOPE2ByTtTlpmjTM=; h=Cc:Date:From:Reply-To:Subject:To; b=h3x4MyK4aH5rp+wXCJ0MOpRLG/efEFD48fRK3oenieIIG7OxyfvVT7avdOwLFRVp1Or Z0Vg/N1z1cB8i3jEHB9YUPsS2uzvy4KDU/D1adk6npSKysM6+kJvGv2LowM4Mf9Ot2VHy FEnlUy6DKd9ctm8WxwAdyI4yKCmo+W0SPSg= Currently multiple interrupts for some devices are written as one array instead of using the DT grouping notation (<0 42 4>, <0 23 4>). This ends up in the same binary representation in the .dtb, but is semantically not equivalent. The yaml schema checks will stumble over this, so lets fix that first. I refrained from using the symbolic names for GIC_SPI/GIC_PPI and IRQ_TYPE_LEVEL_HIGH, mostly because it increases the delta between the original DTS files and the mainline versions, so it's just additional churn. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- arch/arm/boot/dts/ecx-2000.dts | 2 +- arch/arm/boot/dts/ecx-common.dtsi | 4 ++-- arch/arm/boot/dts/highbank.dts | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts index 81eb382b4c23..93cdd020637b 100644 --- a/arch/arm/boot/dts/ecx-2000.dts +++ b/arch/arm/boot/dts/ecx-2000.dts @@ -92,7 +92,7 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; + interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; }; }; }; diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi index f819e3328a9e..b7e74a357471 100644 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ b/arch/arm/boot/dts/ecx-common.dtsi @@ -202,14 +202,14 @@ ethernet@fff50000 { compatible = "calxeda,hb-xgmac"; reg = <0xfff50000 0x1000>; - interrupts = <0 77 4 0 78 4 0 79 4>; + interrupts = <0 77 4>, <0 78 4>, <0 79 4>; dma-coherent; }; ethernet@fff51000 { compatible = "calxeda,hb-xgmac"; reg = <0xfff51000 0x1000>; - interrupts = <0 80 4 0 81 4 0 82 4>; + interrupts = <0 80 4>, <0 81 4>, <0 82 4>; dma-coherent; }; diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index 9e34d1bd7994..b6b0225a769e 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -142,14 +142,14 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; + interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; }; sregs@fff3c200 { compatible = "calxeda,hb-sregs-l2-ecc"; reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; + interrupts = <0 71 4>, <0 72 4>; }; }; From patchwork Thu Feb 27 18:22:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409403 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05E0B1580 for ; Thu, 27 Feb 2020 18:22:29 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D2238246B4 for ; Thu, 27 Feb 2020 18:22:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="ubgOAmHq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D2238246B4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1483+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id 4IYiYY1556264xl6QVUq6Cv9; Thu, 27 Feb 2020 10:22:28 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web09.148.1582827748327055961 for ; Thu, 27 Feb 2020 10:22:28 -0800 X-Received: by mail.kernel.org (Postfix) id 23674246C2; Thu, 27 Feb 2020 18:22:28 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id D9F91246B4; Thu, 27 Feb 2020 18:22:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D9F91246B4 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 900A930E; Thu, 27 Feb 2020 10:22:27 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E69423F73B; Thu, 27 Feb 2020 10:22:25 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 04/13] arm: dts: calxeda: Group port-phys and sgpio-gpio items Date: Thu, 27 Feb 2020 18:22:01 +0000 Message-Id: <20200227182210.89512-5-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: 1grf6TebX9brbf1kzOzxfWprx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827748; bh=d0uc2YpDYlmBozqdn8g+0GfMpp00t+ROaBkDa6uMx38=; h=Cc:Date:From:Reply-To:Subject:To; b=ubgOAmHq2LoBQYEIxodehwisI0Ai1rUWsDJ1ZUK+ZxMjAWGOMThrkF7dn17ntZ0aLTw mb0h60yzo7aDVZrKjbWTwCPpKm2jxZSgW9GRhUlb4v6WvtGYzJhc0yU+mmnK4azMdiivN 6VDCoEUbD4TcWaMsSraNNBrP0pJdbe+XA0M= For proper bindings checks we need to properly group the port-phys and sgpio-gpio items, so that they match the expected number of items. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- arch/arm/boot/dts/ecx-common.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi index b7e74a357471..57a028a69373 100644 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ b/arch/arm/boot/dts/ecx-common.dtsi @@ -27,10 +27,11 @@ reg = <0xffe08000 0x10000>; interrupts = <0 83 4>; dma-coherent; - calxeda,port-phys = <&combophy5 0 &combophy0 0 - &combophy0 1 &combophy0 2 - &combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; + calxeda,port-phys = < &combophy5 0>, <&combophy0 0>, + <&combophy0 1>, <&combophy0 2>, + <&combophy0 3>; + calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, + <&gpioh 7 1>; calxeda,led-order = <4 0 1 2 3>; }; From patchwork Thu Feb 27 18:22:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409405 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3225013A4 for ; Thu, 27 Feb 2020 18:22:31 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 08FD2246A9 for ; Thu, 27 Feb 2020 18:22:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="WQbkQGDB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 08FD2246A9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1484+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id zyQaYY1556264xQx0C5HVFzV; Thu, 27 Feb 2020 10:22:30 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web12.143.1582827750548248776 for ; Thu, 27 Feb 2020 10:22:30 -0800 X-Received: by mail.kernel.org (Postfix) id 590A1246C0; Thu, 27 Feb 2020 18:22:30 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 0CB33246BD; Thu, 27 Feb 2020 18:22:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0CB33246BD X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BDE251FB; Thu, 27 Feb 2020 10:22:29 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C4B553F73B; Thu, 27 Feb 2020 10:22:27 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Subject: [PATCH v2 05/13] dt-bindings: clock: Convert Calxeda clock bindings to json-schema Date: Thu, 27 Feb 2020 18:22:02 +0000 Message-Id: <20200227182210.89512-6-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: CZrKK9AncR6YM7t42tgE3KD8x1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827750; bh=EMSDwbFDJodW6eWSjn+7fIV+AlzOTJ+KOuWIfvPWAOY=; h=Cc:Date:From:Reply-To:Subject:To; b=WQbkQGDBz+Mkh3xK5LajtJZbvUOWj4x0Wi+KJODLvxeWxOnUWhVmbnJcEDjRDvFF0pL HHhQMMngHsRnJ0QmHwEeeUV7Rm2AKnOmLcw7dcS/xDcj7DXwnlR7vMLLfeiFGVWbZ0SI4 PwM0tFph1ioj38LcS1WbvCAuSGWkEpNFj1k= Convert the Calxeda clock bindings to DT schema format using json-schema. This just covers the actual PLL and divider clock nodes. In the actual DTs they are somewhat unconnected (no ranges or bus compatible) children of the sregs node, but for the actual clock bindings this is not relevant. One oddity is that the addresses are relative to the parent node, without that being pronounced using a ranges property. But this is too late to fix now. Signed-off-by: Andre Przywara Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Acked-by: Stephen Boyd --- .../devicetree/bindings/clock/calxeda.txt | 17 ---- .../devicetree/bindings/clock/calxeda.yaml | 82 +++++++++++++++++++ 2 files changed, 82 insertions(+), 17 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/calxeda.txt create mode 100644 Documentation/devicetree/bindings/clock/calxeda.yaml diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt deleted file mode 100644 index 0a6ac1bdcda1..000000000000 --- a/Documentation/devicetree/bindings/clock/calxeda.txt +++ /dev/null @@ -1,17 +0,0 @@ -Device Tree Clock bindings for Calxeda highbank platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "calxeda,hb-pll-clock" - for a PLL clock - "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the - A9 clock. - "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock. - "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller. -- reg : shall be the control register offset from SYSREGs base for the clock. -- clocks : shall be the input parent clock phandle for the clock. This is - either an oscillator or a pll output. -- #clock-cells : from common clock binding; shall be set to 0. diff --git a/Documentation/devicetree/bindings/clock/calxeda.yaml b/Documentation/devicetree/bindings/clock/calxeda.yaml new file mode 100644 index 000000000000..39c8bf646205 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/calxeda.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/calxeda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device Tree Clock bindings for Calxeda highbank platform + +description: | + This binding covers the Calxeda SoC internal peripheral and bus clocks + as used by peripherals. The clocks live inside the "system register" + region of the SoC, so are typically presented as children of an + "hb-sregs" node. + +maintainers: + - Andre Przywara + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - calxeda,hb-pll-clock + - calxeda,hb-a9periph-clock + - calxeda,hb-a9bus-clock + - calxeda,hb-emmc-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - clocks + - reg + +additionalProperties: false + +examples: + - | + sregs@3fffc000 { + compatible = "calxeda,hb-sregs"; + reg = <0x3fffc000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333000>; + }; + + ddrpll: ddrpll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x108>; + }; + + a9pll: a9pll { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x100>; + }; + + a9periphclk: a9periphclk { + #clock-cells = <0>; + compatible = "calxeda,hb-a9periph-clock"; + clocks = <&a9pll>; + reg = <0x104>; + }; + }; + }; + +... From patchwork Thu Feb 27 18:22:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409407 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4A61214D5 for ; Thu, 27 Feb 2020 18:22:33 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 20DE4246A6 for ; Thu, 27 Feb 2020 18:22:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="lWRT4o+C" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 20DE4246A6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1485+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id H8uiYY1556264xtP1lugGI00; Thu, 27 Feb 2020 10:22:32 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web10.133.1582827752455945676 for ; Thu, 27 Feb 2020 10:22:32 -0800 X-Received: by mail.kernel.org (Postfix) id 4411F246CB; Thu, 27 Feb 2020 18:22:32 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id EDD40246A6; Thu, 27 Feb 2020 18:22:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EDD40246A6 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B79DB30E; Thu, 27 Feb 2020 10:22:31 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F24703F73B; Thu, 27 Feb 2020 10:22:29 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas , Jens Axboe Subject: [PATCH v2 06/13] dt-bindings: sata: Convert Calxeda SATA controller to json-schema Date: Thu, 27 Feb 2020 18:22:03 +0000 Message-Id: <20200227182210.89512-7-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: zGBQ3bQHH16pBlW68HGJBDdjx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827752; bh=Zqkj/RBV4iT63R5GTXi70z5/Bey6bc/B4q1XpAxEFD0=; h=Cc:Date:From:Reply-To:Subject:To; b=lWRT4o+C8Dn/9LZpryBCEYC+9pWtXNcN0HruWwXF2XNujiPL2EQ8IcoKtM91XnFtvL2 nwjuw255zE3IeHsUKAEeZ41+wBswspbs+Ush9QrzBmJFK7+G55a7BQEvohcD/VrIKkhu2 +D/ryTp2LQMO7DlnlDDZvf4rT1a9rEZ64RM= Convert the Calxeda Highbank SATA controller binding to DT schema format using json-schema. Signed-off-by: Andre Przywara Cc: Jens Axboe --- .../devicetree/bindings/ata/sata_highbank.txt | 44 --------- .../bindings/ata/sata_highbank.yaml | 95 +++++++++++++++++++ 2 files changed, 95 insertions(+), 44 deletions(-) delete mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.txt create mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.yaml diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt deleted file mode 100644 index aa83407cb7a4..000000000000 --- a/Documentation/devicetree/bindings/ata/sata_highbank.txt +++ /dev/null @@ -1,44 +0,0 @@ -* Calxeda AHCI SATA Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -The Calxeda SATA controller mostly conforms to the AHCI interface -with some special extensions to add functionality. -Each SATA controller should have its own node. - -Required properties: -- compatible : compatible list, contains "calxeda,hb-ahci" -- interrupts : -- reg : - -Optional properties: -- dma-coherent : Present if dma operations are coherent -- calxeda,port-phys : phandle-combophy and lane assignment, which maps each - SATA port to a combophy and a lane within that - combophy -- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off, - which indicates that the driver supports SGPIO - indicator lights using the indicated GPIOs -- calxeda,led-order : a u32 array that map port numbers to offsets within the - SGPIO bitstream. -- calxeda,tx-atten : a u32 array that contains TX attenuation override - codes, one per port. The upper 3 bytes are always - 0 and thus ignored. -- calxeda,pre-clocks : a u32 that indicates the number of additional clock - cycles to transmit before sending an SGPIO pattern -- calxeda,post-clocks: a u32 that indicates the number of additional clock - cycles to transmit after sending an SGPIO pattern - -Example: - sata@ffe08000 { - compatible = "calxeda,hb-ahci"; - reg = <0xffe08000 0x1000>; - interrupts = <115>; - dma-coherent; - calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1 - &combophy0 2 &combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; - calxeda,led-order = <4 0 1 2 3>; - calxeda,tx-atten = <0xff 22 0xff 0xff 23>; - calxeda,pre-clocks = <10>; - calxeda,post-clocks = <0>; - }; diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.yaml b/Documentation/devicetree/bindings/ata/sata_highbank.yaml new file mode 100644 index 000000000000..6dcf91e1bac0 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/sata_highbank.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/sata_highbank.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda AHCI SATA Controller + +description: | + The Calxeda SATA controller mostly conforms to the AHCI interface + with some special extensions to add functionality, to map GPIOs for + activity LEDs and for mapping the ComboPHYs. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: calxeda,hb-ahci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dma-coherent: true + + calxeda,pre-clocks: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Indicates the number of additional clock cycles to transmit before + sending an SGPIO pattern. + + calxeda,post-clocks: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Indicates the number of additional clock cycles to transmit after + sending an SGPIO pattern. + + calxeda,led-order: + description: Maps port numbers to offsets within the SGPIO bitstream. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - minItems: 1 + maxItems: 8 + + calxeda,port-phys: + description: | + phandle-combophy and lane assignment, which maps each SATA port to a + combophy and a lane within that combophy + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle-array + - minItems: 1 + maxItems: 8 + + calxeda,tx-atten: + description: | + Contains TX attenuation override codes, one per port. + The upper 24 bits of each entry are always 0 and thus ignored. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - minItems: 1 + maxItems: 8 + + calxeda,sgpio-gpio: + description: | + phandle-gpio bank, bit offset, and default on or off, which indicates + that the driver supports SGPIO indicator lights using the indicated + GPIOs. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sata@ffe08000 { + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x1000>; + interrupts = <115>; + dma-coherent; + calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1 + &combophy0 2 &combophy0 3>; + calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; + calxeda,led-order = <4 0 1 2 3>; + calxeda,tx-atten = <0xff 22 0xff 0xff 23>; + calxeda,pre-clocks = <10>; + calxeda,post-clocks = <0>; + }; + +... From patchwork Thu Feb 27 18:22:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409409 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2112614D5 for ; Thu, 27 Feb 2020 18:22:35 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EA666246B4 for ; Thu, 27 Feb 2020 18:22:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="rXpRYVXB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EA666246B4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1486+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id K9N2YY1556264xYHG9mGrXED; Thu, 27 Feb 2020 10:22:34 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web11.145.1582827754382233071 for ; Thu, 27 Feb 2020 10:22:34 -0800 X-Received: by mail.kernel.org (Postfix) id 2786C246CD; Thu, 27 Feb 2020 18:22:34 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id CCBF2246B4; Thu, 27 Feb 2020 18:22:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CCBF2246B4 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 966D61FB; Thu, 27 Feb 2020 10:22:33 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EBC5C3F73B; Thu, 27 Feb 2020 10:22:31 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 07/13] dt-bindings: net: Convert Calxeda Ethernet binding to json-schema Date: Thu, 27 Feb 2020 18:22:04 +0000 Message-Id: <20200227182210.89512-8-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: q0TcAxIHwq6bJtW6LTMHgv8Dx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827754; bh=+5OCEUL7bo78NQROBVHK7gGoOYfFsH2oeLhL9+ZKqy0=; h=Cc:Date:From:Reply-To:Subject:To; b=rXpRYVXBo5wPB9v4zX+qbgp/d+XsYquWe25if3otmTEW7IULaZF9OQl0hBoLEAyD84M mdQKVbj+TEq+UXxUKwB6kgfcaRSAlUhu9JgV0uM1RuB7tNxtxIIOhxhRaQhVJFgWe4R2B Ay3avTNW3fkqX2RfCaqmrl89J+GTYk4s4C0= Convert the Calxeda XGMAC Ethernet device binding to DT schema format using json-schema. Signed-off-by: Andre Przywara --- .../devicetree/bindings/net/calxeda-xgmac.txt | 18 ------- .../bindings/net/calxeda-xgmac.yaml | 49 +++++++++++++++++++ 2 files changed, 49 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/calxeda-xgmac.txt create mode 100644 Documentation/devicetree/bindings/net/calxeda-xgmac.yaml diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt deleted file mode 100644 index c8ae996bd8f2..000000000000 --- a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Calxeda Highbank 10Gb XGMAC Ethernet - -Required properties: -- compatible : Should be "calxeda,hb-xgmac" -- reg : Address and length of the register set for the device -- interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt. - The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt. - -Optional properties: -- dma-coherent : Present if dma operations are coherent - -Example: - -ethernet@fff50000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff50000 0x1000>; - interrupts = <0 77 4 0 78 4 0 79 4>; -}; diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.yaml b/Documentation/devicetree/bindings/net/calxeda-xgmac.yaml new file mode 100644 index 000000000000..a8c1f00cff0f --- /dev/null +++ b/Documentation/devicetree/bindings/net/calxeda-xgmac.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/calxeda-xgmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank 10Gb XGMAC Ethernet controller + +description: | + The Calxeda XGMAC Ethernet controllers are directly connected to the + internal machine "network fabric", which is set up, initialised and + managed by the firmware. So there are no PHY properties in this + binding. Switches in the fabric take care of routing and mapping the + traffic to external network ports. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: calxeda,hb-xgmac + + reg: + maxItems: 1 + + interrupts: + description: | + Can point to at most 3 xgmac interrupts. The 1st one is the main + interrupt, the 2nd one is used for power management. The optional + 3rd one is the low power state interrupt. + minItems: 2 + maxItems: 3 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + ethernet@fff50000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff50000 0x1000>; + interrupts = <0 77 4>, <0 78 4>, <0 79 4>; + }; From patchwork Thu Feb 27 18:22:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409411 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D3D4C13A4 for ; Thu, 27 Feb 2020 18:22:36 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AEA83246AD for ; Thu, 27 Feb 2020 18:22:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="Em8NmiU+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AEA83246AD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1487+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id Xx35YY1556264xL0gn6WBpo7; Thu, 27 Feb 2020 10:22:36 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web10.135.1582827756244246606 for ; Thu, 27 Feb 2020 10:22:36 -0800 X-Received: by mail.kernel.org (Postfix) id 0F846246BF; Thu, 27 Feb 2020 18:22:36 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id AF635246A6; Thu, 27 Feb 2020 18:22:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AF635246A6 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7828C30E; Thu, 27 Feb 2020 10:22:35 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CAC2A3F73B; Thu, 27 Feb 2020 10:22:33 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 08/13] dt-bindings: phy: Convert Calxeda ComboPHY binding to json-schema Date: Thu, 27 Feb 2020 18:22:05 +0000 Message-Id: <20200227182210.89512-9-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: Kg4AgHklZ0Kw6yTbbymAVmc6x1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827756; bh=tPSmwVI4J9Jldi6STzlHpMKLPtHVOfv2362HNKGkOR8=; h=Cc:Date:From:Reply-To:Subject:To; b=Em8NmiU+tzm2Ti9W4pzybOxbB+x87Lg5zW8Okkz2JJPbP2jiirLMyefOqOpv5Nt2bnB MpHe6kcoAUjFdcVBJJZ5uKrp8lwMoOAt0AwqERJlRq5SJ84a254b27wgacX3/iicaP196 6qLP6k17amJ4PslKYKFwiSgxEG4apYySv+c= Convert the Calxeda ComboPHY binding to DT schema format using json-schema. There is no driver in the Linux kernel matching the compatible string, but the nodes are parsed by the SATA driver, which links to them using its port-phys property. Signed-off-by: Andre Przywara --- .../bindings/phy/calxeda-combophy.txt | 17 ------- .../bindings/phy/calxeda-combophy.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 17 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/calxeda-combophy.txt create mode 100644 Documentation/devicetree/bindings/phy/calxeda-combophy.yaml diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.txt b/Documentation/devicetree/bindings/phy/calxeda-combophy.txt deleted file mode 100644 index 6622bdb2e8bc..000000000000 --- a/Documentation/devicetree/bindings/phy/calxeda-combophy.txt +++ /dev/null @@ -1,17 +0,0 @@ -Calxeda Highbank Combination Phys for SATA - -Properties: -- compatible : Should be "calxeda,hb-combophy" -- #phy-cells: Should be 1. -- reg : Address and size for Combination Phy registers. -- phydev: device ID for programming the combophy. - -Example: - - combophy5: combo-phy@fff5d000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff5d000 0x1000>; - phydev = <31>; - }; - diff --git a/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml new file mode 100644 index 000000000000..995d0efe280d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/calxeda-combophy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank Combination PHYs binding for SATA + +description: | + The Calxeda Combination PHYs connect the SoC to the internal fabric + and to SATA connectors. The PHYs support multiple protocols (SATA, + SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC + controller). + Programming the PHYs is typically handled by those device drivers, + not by a dedicated PHY driver. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: calxeda,hb-combophy + + '#phy-cells': + const: 1 + + reg: + maxItems: 1 + + phydev: + description: device ID for programming the ComboPHY. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - maximum: 31 + +required: + - compatible + - reg + - phydev + - '#phy-cells' + +additionalProperties: false + +examples: + - | + combophy5: combo-phy@fff5d000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff5d000 0x1000>; + phydev = <31>; + }; From patchwork Thu Feb 27 18:22:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409413 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D57CA14D5 for ; Thu, 27 Feb 2020 18:22:38 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ABED7246A6 for ; Thu, 27 Feb 2020 18:22:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="AHNJraCY" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ABED7246A6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1488+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id SLXjYY1556264xljl58a9f3L; Thu, 27 Feb 2020 10:22:38 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web11.147.1582827758006004530 for ; Thu, 27 Feb 2020 10:22:38 -0800 X-Received: by mail.kernel.org (Postfix) id CBAC2246B7; Thu, 27 Feb 2020 18:22:37 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 8DFA7246AE; Thu, 27 Feb 2020 18:22:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8DFA7246AE X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5816C1FB; Thu, 27 Feb 2020 10:22:37 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AC6113F73B; Thu, 27 Feb 2020 10:22:35 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 09/13] dt-bindings: arm: Convert Calxeda L2 cache controller to json-schema Date: Thu, 27 Feb 2020 18:22:06 +0000 Message-Id: <20200227182210.89512-10-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: NEZ0xsjlqtT49ZVcnQzUTxbkx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827758; bh=sHXL7WLU+uuCbD1A93sJ7YPdHV1mxYbTxLvxUcVzJ2Y=; h=Cc:Date:From:Reply-To:Subject:To; b=AHNJraCYgHg9dvWlK/h5cZovyy+iGIwYy4Ihraw+KzSYQTnb43n12QQA5XsXdZ4WKNw RyfFC0U4zGyV4my6ABAGcWE/CtvsaHxRj3nofNcrDnRVTdVz7ScOAbPSW2Q0bCoKfqE2Z 1nGvqV8funV/IMQvr+S3SUxIcMYh1ztsqrE= Convert the L2-ECC controller binding to DT schema format using json-schema. This is indented to be just used for error reporting. Signed-off-by: Andre Przywara --- .../devicetree/bindings/arm/calxeda/l2ecc.txt | 15 ------- .../bindings/arm/calxeda/l2ecc.yaml | 43 +++++++++++++++++++ 2 files changed, 43 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt create mode 100644 Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt deleted file mode 100644 index 94e642a33db0..000000000000 --- a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt +++ /dev/null @@ -1,15 +0,0 @@ -Calxeda Highbank L2 cache ECC - -Properties: -- compatible : Should be "calxeda,hb-sregs-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. - -Example: - - sregs@fff3c200 { - compatible = "calxeda,hb-sregs-l2-ecc"; - reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml new file mode 100644 index 000000000000..5481dd7216ba --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank L2 cache ECC + +description: | + Binding for the Calxeda Highbank L2 cache controller ECC device. + This does not cover the actual L2 cache controller control registers, + but just the error reporting functionality. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: "calxeda,hb-sregs-l2-ecc" + + reg: + maxItems: 1 + + interrupts: + description: | + Should be single bit error interrupt, then double bit error interrupt. + minItems: 2 + maxItems: 2 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4>, <0 72 4>; + }; From patchwork Thu Feb 27 18:22:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409415 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 75D4514D5 for ; Thu, 27 Feb 2020 18:22:40 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4CCCA246B4 for ; Thu, 27 Feb 2020 18:22:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="r20Z4zz/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4CCCA246B4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1489+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id hDOMYY1556264x0nNwxegyD3; Thu, 27 Feb 2020 10:22:40 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web09.151.1582827759871058380 for ; Thu, 27 Feb 2020 10:22:39 -0800 X-Received: by mail.kernel.org (Postfix) id A8DCE246AE; Thu, 27 Feb 2020 18:22:39 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 6BE53246A6; Thu, 27 Feb 2020 18:22:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6BE53246A6 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 36C2730E; Thu, 27 Feb 2020 10:22:39 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8C2B13F73B; Thu, 27 Feb 2020 10:22:37 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 10/13] dt-bindings: memory-controllers: Convert Calxeda DDR to json-schema Date: Thu, 27 Feb 2020 18:22:07 +0000 Message-Id: <20200227182210.89512-11-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: fpwD1zC4n84jm1FjhGyEQ0mmx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827760; bh=p/mlfq9Q4wKFtZQvlbqlEXgDXVXlp8Y8KAp3nU/TUXQ=; h=Cc:Date:From:Reply-To:Subject:To; b=r20Z4zz/XAmRnh/f2mjpDhsCTtOo1bFCGG71/O4S13bXwLjYUQLad8IxuGTZZYFKcdD q51oHKEsgWZG/c5qgBqJqfKNRbxDi/eos2XSwn88VRTi/FE+dMkiWe7bdLdlsF82wNFc5 CP/LnqZAlZeOCBoGnGh8ySx7yiAZRsHbUlw= Convert the Calxeda DDR memory controller binding to DT schema format using json-schema. Although this technically covers the whole DRAM controller, the intention to use it only for error reporting and mapping fault addresses to DRAM chips. Signed-off-by: Andre Przywara --- .../memory-controllers/calxeda-ddr-ctrlr.txt | 16 ------- .../memory-controllers/calxeda-ddr-ctrlr.yaml | 42 +++++++++++++++++++ 2 files changed, 42 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt deleted file mode 100644 index 049675944b78..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt +++ /dev/null @@ -1,16 +0,0 @@ -Calxeda DDR memory controller - -Properties: -- compatible : Should be: - - "calxeda,hb-ddr-ctrl" for ECX-1000 - - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000 -- reg : Address and size for DDR controller registers. -- interrupts : Interrupt for DDR controller. - -Example: - - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml new file mode 100644 index 000000000000..d9739501d61d --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda DDR memory controller binding + +description: | + The Calxeda DDR memory controller is initialised and programmed by the + firmware, but an OS might want to read its registers for error reporting + purposes and to learn about the DRAM topology. + +maintainers: + - Andre Przywara + +properties: + compatible: + enum: + - calxeda,hb-ddr-ctrl + - calxeda,ecx-2000-ddr-ctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; From patchwork Thu Feb 27 18:22:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409417 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CAB0113A4 for ; Thu, 27 Feb 2020 18:22:42 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A0DD4246AA for ; Thu, 27 Feb 2020 18:22:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="ALo9Zbs/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A0DD4246AA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1490+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id 11YCYY1556264xGBLulry4Wm; Thu, 27 Feb 2020 10:22:42 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web12.145.1582827762076816539 for ; Thu, 27 Feb 2020 10:22:42 -0800 X-Received: by mail.kernel.org (Postfix) id D0C2D246AF; Thu, 27 Feb 2020 18:22:41 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 808B0246A6; Thu, 27 Feb 2020 18:22:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 808B0246A6 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4ABD91FB; Thu, 27 Feb 2020 10:22:41 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6B5D83F73B; Thu, 27 Feb 2020 10:22:39 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas , Corey Minyard , openipmi-developer@lists.sourceforge.net Subject: [PATCH v2 11/13] dt-bindings: ipmi: Convert IPMI-SMIC bindings to json-schema Date: Thu, 27 Feb 2020 18:22:08 +0000 Message-Id: <20200227182210.89512-12-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: 141SAnNgde6PylLXcSGdZJYyx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827762; bh=DKFfevmq+Zi2eQP56jg8k54piw+WHV4uXPqyWcmgJmE=; h=Cc:Date:From:Reply-To:Subject:To; b=ALo9Zbs/etcieqalZyg26TPi1imvaw2AV/OAf7auO3De2B0gyNhyWihqyZqM6NmDtO6 8KBH+PLcurOoL4AgT4IIZ/K6RWE5Bgj6W2qsHXXtQIPIBuRH0SK2AOCBxoGKSTeYwm5ig XpeNA3PimtpB7qHDyB2+dQfvnrF8zJbgV1o= Convert the generic IPMI controller bindings to DT schema format using json-schema. I removed the formerly mandatory device-type property, since this is deprecated in the DT spec, except for the legacy CPU and memory nodes. Signed-off-by: Andre Przywara Cc: Corey Minyard Cc: openipmi-developer@lists.sourceforge.net --- .../devicetree/bindings/ipmi/ipmi-smic.txt | 25 --------- .../devicetree/bindings/ipmi/ipmi-smic.yaml | 56 +++++++++++++++++++ 2 files changed, 56 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/ipmi/ipmi-smic.txt create mode 100644 Documentation/devicetree/bindings/ipmi/ipmi-smic.yaml diff --git a/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt b/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt deleted file mode 100644 index d5f1a877ed3e..000000000000 --- a/Documentation/devicetree/bindings/ipmi/ipmi-smic.txt +++ /dev/null @@ -1,25 +0,0 @@ -IPMI device - -Required properties: -- compatible: should be one of ipmi-kcs, ipmi-smic, or ipmi-bt -- device_type: should be ipmi -- reg: Address and length of the register set for the device - -Optional properties: -- interrupts: The interrupt for the device. Without this the interface - is polled. -- reg-size - The size of the register. Defaults to 1 -- reg-spacing - The number of bytes between register starts. Defaults to 1 -- reg-shift - The amount to shift the registers to the right to get the data - into bit zero. - -Example: - -smic@fff3a000 { - compatible = "ipmi-smic"; - device_type = "ipmi"; - reg = <0xfff3a000 0x1000>; - interrupts = <0 24 4>; - reg-size = <4>; - reg-spacing = <4>; -}; diff --git a/Documentation/devicetree/bindings/ipmi/ipmi-smic.yaml b/Documentation/devicetree/bindings/ipmi/ipmi-smic.yaml new file mode 100644 index 000000000000..c859e0e959b9 --- /dev/null +++ b/Documentation/devicetree/bindings/ipmi/ipmi-smic.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ipmi/ipmi-smic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IPMI device bindings + +description: IPMI device bindings + +maintainers: + - Corey Minyard + +properties: + compatible: + enum: + - ipmi-kcs + - ipmi-smic + - ipmi-bt + + reg: + maxItems: 1 + + interrupts: + description: Interface is polled if this property is omitted. + maxItems: 1 + + reg-size: + description: The access width of the register in bytes. Defaults to 1. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 2, 4, 8] + + reg-spacing: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of bytes between register starts. Defaults to 1. + + reg-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The amount of bits to shift the register content to the right to get + the data into bit zero. + +required: + - compatible + - reg + +examples: + - | + smic@fff3a000 { + compatible = "ipmi-smic"; + reg = <0xfff3a000 0x1000>; + interrupts = <0 24 4>; + reg-size = <4>; + reg-spacing = <4>; + }; From patchwork Thu Feb 27 18:22:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409419 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F0C913A4 for ; Thu, 27 Feb 2020 18:22:44 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65CBE246A6 for ; Thu, 27 Feb 2020 18:22:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="qniw+Hjm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 65CBE246A6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1491+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id SpmrYY1556264xsawEQInD1x; Thu, 27 Feb 2020 10:22:44 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web10.137.1582827763985264082 for ; Thu, 27 Feb 2020 10:22:44 -0800 X-Received: by mail.kernel.org (Postfix) id C3438246AA; Thu, 27 Feb 2020 18:22:43 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 6D693246A6; Thu, 27 Feb 2020 18:22:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6D693246A6 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 290B530E; Thu, 27 Feb 2020 10:22:43 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7EA273F73B; Thu, 27 Feb 2020 10:22:41 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 12/13] dt-bindings: arm: Add Calxeda system registers json-schema binding Date: Thu, 27 Feb 2020 18:22:09 +0000 Message-Id: <20200227182210.89512-13-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: 9zPkPiBFMZus9JfkqpC6y2BBx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827764; bh=1ZSd3XDkqTPLhEYbu87bLYuogI88Y9ZLUfaMj63br6s=; h=Cc:Date:From:Reply-To:Subject:To; b=qniw+HjmganVIrxgC+XuNNHWg22+sa5n103ibs7K2dWGn9NcujCJa03BYfSoAIrmjl1 9b3sDDmtn6fglITGCf7IYJvrhu818yyXEsFs8FT6cV/nvAImPSWfQR6LiLFjeJ7ur/X6o NyeyoPx9+yTE73gjleq3P42sOZUp28Hd2gs= The Calxeda system registers are a collection of MMIO register controlling several more general aspects of the SoC. Beside for some power management tasks this node is also somewhat abused as the container for the clock nodes. Add a binding in DT schema format using json-schema. Signed-off-by: Andre Przywara --- .../bindings/arm/calxeda/hb-sregs.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml diff --git a/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml b/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml new file mode 100644 index 000000000000..4753e8dc5873 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda/hb-sregs.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank system registers + +description: | + The Calxeda Highbank system has a block of MMIO registers controlling + several generic system aspects. Those can be used to control some power + management, they also contain some gate and PLL clocks. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: calxeda,hb-sregs + + reg: + maxItems: 1 + + clocks: + type: object + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + sregs@fff3c000 { + compatible = "calxeda,hb-sregs"; + reg = <0xfff3c000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333000>; + }; + }; + }; From patchwork Thu Feb 27 18:22:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 11409421 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B71114D5 for ; Thu, 27 Feb 2020 18:22:46 +0000 (UTC) Received: from web01.groups.io (unknown [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2289A246B4 for ; Thu, 27 Feb 2020 18:22:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linux.kernel.org header.i=@linux.kernel.org header.b="gamkJvQB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2289A246B4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+26986+1492+1554929+3438807@linux.kernel.org X-Received: by 127.0.0.2 with SMTP id Chi1YY1556264xWKoQqSEfEU; Thu, 27 Feb 2020 10:22:45 -0800 X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web11.149.1582827765670776671 for ; Thu, 27 Feb 2020 10:22:45 -0800 X-Received: by mail.kernel.org (Postfix) id 7B06A246BD; Thu, 27 Feb 2020 18:22:45 +0000 (UTC) X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mail.kernel.org (Postfix) with ESMTP id 3D8A9246B4; Thu, 27 Feb 2020 18:22:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3D8A9246B4 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 071B04B2; Thu, 27 Feb 2020 10:22:45 -0800 (PST) X-Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5D25B3F73B; Thu, 27 Feb 2020 10:22:43 -0800 (PST) From: Andre Przywara To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Maxime Ripard , Robert Richter , soc@kernel.org, Jon Loeliger , Mark Langsdorf , Eric Auger , Will Deacon , Catalin Marinas Subject: [PATCH v2 13/13] MAINTAINERS: Update Calxeda Highbank maintainership Date: Thu, 27 Feb 2020 18:22:10 +0000 Message-Id: <20200227182210.89512-14-andre.przywara@arm.com> In-Reply-To: <20200227182210.89512-1-andre.przywara@arm.com> References: <20200227182210.89512-1-andre.przywara@arm.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org X-Gm-Message-State: Rv96frx3BJtvZetGinng14axx1554929AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1582827765; bh=0A9CXrPSJAktEYOItOnNZhB4FBgYQGQq1i3YsuBpdl0=; h=Cc:Date:From:Reply-To:Subject:To; b=gamkJvQBs4EIcW9IzL54sMN4RTThTxljjCsVY75jAZGvuATV+fa84HSDfSDrV8N/ut+ 579Jo272s1EDCbUI0SsfaL1XVzAxZ1h7TLaZtiPrlrl4bojleda3k6Nufvhv/6VQFtVzG olTcxASkG8hJ5k/dnlUTBwFZzXh+poQuhbk= Rob sees little point in maintaining the Calxeda architecture (early ARM 32-bit server) anymore. Since I have a machine sitting under my desk, change the maintainership to not lose support for that platform. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index c3800f3b5e6e..f488906a63d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1605,7 +1605,7 @@ F: Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt ARM/CALXEDA HIGHBANK ARCHITECTURE -M: Rob Herring +M: Andre Przywara L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-highbank/