From patchwork Sun Mar 1 17:04:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11414323 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6EFFC1395 for ; Sun, 1 Mar 2020 17:07:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 40F1C24680 for ; Sun, 1 Mar 2020 17:07:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MrrUNAFs" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 40F1C24680 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=roeck-us.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j8S3n-0000lE-Ei for patchwork-qemu-devel@patchwork.kernel.org; Sun, 01 Mar 2020 12:07:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56757) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j8S1S-0005sH-2s for qemu-devel@nongnu.org; Sun, 01 Mar 2020 12:04:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j8S1Q-0001j0-Hc for qemu-devel@nongnu.org; Sun, 01 Mar 2020 12:04:58 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:39619) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j8S1N-0001fA-FX; Sun, 01 Mar 2020 12:04:53 -0500 Received: by mail-pf1-x443.google.com with SMTP id l7so4349871pff.6; Sun, 01 Mar 2020 09:04:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z4+7AUJj5DR8ek0G/CYhlnGdnmdw4yeNw+orIpOPL7o=; b=MrrUNAFs9mPc3RsLAbzDqZiMJaE7bg5xrRD80AoCrcElI8lcdmHPeXScaVAFZL0M0I 7xH+r97J4naDOFgjWEHD5vUunZ6D2qijPPjtMkayMVa9t5xii6QYgKInGmpBXNTALGjB JTFMZosV0jl/kghobXpfm3qP+he2zNcb65OY4dBnlYV7udliRnVQaj2EF+kypfhbQJTd 0ipNQL2Ol5nfg6fetvPOoyDkVGbMaqftHzL2RBWF0WWcBcHPt3sZhFJmV2GyFypnS1mx 80Gehhtl+IA3ahCJWM9rTMivTQdENV9R6PxYegS+i7UTOH/y9SzBiEYcieEOmRe4tCFT JqEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Z4+7AUJj5DR8ek0G/CYhlnGdnmdw4yeNw+orIpOPL7o=; b=gWmVbdwoEZb3V5PNLflBdfkQyMdm4DQPTT4bGH/AK0kMY1LCRb851u4ZNCxBiV2WiR zfMWSUNaza2zf/IDAlTw0AfleTs0HW8p6tR3jQzA0qVqmjGYeFPDg3VHaYtWzDXtvCHN 6w45YVJHCmD2ncubDYK/lQwo587WyKh35IAzNnKlHhQ/vwxvt1ic9B057BxCSaP9lBb9 H6xjlji/ZG9Nub45Ug5E2w2X0aHj9GPLu8Nmo4OghIwTW3vOqSymI5VpejdRbJDMRj+W IAotY8OTysrM9W0KPEW81UxUwq0lQ4N/pkuUfI+nRKAPpLTbBluDDkAswO89AbbDTpHM Uw5Q== X-Gm-Message-State: APjAAAU24C/v7qSl9Njb3NMyBYPclN6P7UJ9yzCqPg8TKmsZYV9XgGg9 k/q4XLhtBZGbr353K2Vp+A8= X-Google-Smtp-Source: APXvYqxto5rk+muFC92nFVTkeQRc+QL59XNNZi75jRFEL/zjESJn+9CHkTyeUaxmjW1alwLiAtUkOQ== X-Received: by 2002:a62:e217:: with SMTP id a23mr14178565pfi.50.1583082292495; Sun, 01 Mar 2020 09:04:52 -0800 (PST) Received: from localhost ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id w1sm17855652pgr.4.2020.03.01.09.04.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 01 Mar 2020 09:04:52 -0800 (PST) From: Guenter Roeck To: Peter Maydell Subject: [PATCH 1/3] Add dummy i.MXS STMP register support Date: Sun, 1 Mar 2020 09:04:41 -0800 Message-Id: <20200301170443.12904-2-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200301170443.12904-1-linux@roeck-us.net> References: <20200301170443.12904-1-linux@roeck-us.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" STMP registers are registers with a specific register layout. When using this layout, a register is implemented as set of four: - The register itself - A register to set individual register bits - A register to reset individual register bits - A register to toggle individual register bits This register layout is used in various i.MXS SoCs. In some cases, bit 31 of a STMP register has special reset functionality. Setting the reset bit resets the chip or block and then sets bit 30. This functionality is common enough that the Linux kernel implements a library function to support it. This patch implements an STMP register as a special device called STMP device. An STMP device can be instantiated on top of an unimplemented device. Each instance implements a single register of this unimplemented device. In some cases, this is necessary and sufficient to be able to load a driver. The term "STMP" originates from the Linux kernel. Its origin and meaning is unknown to the author, but it seemed to make sense to use the same terminology here. Signed-off-by: Guenter Roeck --- hw/misc/Kconfig | 3 + hw/misc/Makefile.objs | 1 + hw/misc/stmp.c | 121 +++++++++++++++++++++++++++++++++++++++++ include/hw/misc/stmp.h | 47 ++++++++++++++++ 4 files changed, 172 insertions(+) create mode 100644 hw/misc/stmp.c create mode 100644 include/hw/misc/stmp.h diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index bdd77d8020..68af3f1e2a 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -123,6 +123,9 @@ config AUX bool select I2C +config STMP + bool + config UNIMP bool diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index da993f45b7..942653854c 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -9,6 +9,7 @@ common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o common-obj-$(CONFIG_EDU) += edu.o common-obj-$(CONFIG_PCA9552) += pca9552.o +common-obj-$(CONFIG_STMP) += stmp.o common-obj-$(CONFIG_UNIMP) += unimp.o common-obj-$(CONFIG_FW_CFG_DMA) += vmcoreinfo.o diff --git a/hw/misc/stmp.c b/hw/misc/stmp.c new file mode 100644 index 0000000000..eb909fccfe --- /dev/null +++ b/hw/misc/stmp.c @@ -0,0 +1,121 @@ +/* + * MXS "STMP" dummy device + * + * This is a dummy device which follows MXS "STMP" register layout. + * It's useful for stubbing out regions of an SoC or board + * map which correspond to devices that have not yet been + * implemented, yet require "STMP" device specific reset support. + * This is often sufficient to placate initial guest device + * driver probing such that the system will come up. + * + * Derived from "unimplemented" device code. + * Copyright Linaro Limited, 2017 + * Written by Peter Maydell + * + * Written by Guenter Roeck + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/misc/stmp.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" + +#define REG_VAL 0x0 +#define REG_SET 0x4 +#define REG_CLR 0x8 +#define REG_TOG 0xc + +#define STMP_MODULE_CLKGATE (1 << 30) +#define STMP_MODULE_SFTRST (1 << 31) + +static uint64_t stmp_read(void *opaque, hwaddr offset, unsigned size) +{ + StmpDeviceState *s = STMP_DEVICE(opaque); + + switch (offset) { + case REG_VAL: + return s->regval; + default: + return 0; + } +} + +static void stmp_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + StmpDeviceState *s = STMP_DEVICE(opaque); + + switch (offset) { + case REG_VAL: + s->regval = value; + break; + case REG_SET: + s->regval |= value; + if (s->have_reset && (value & STMP_MODULE_SFTRST)) { + s->regval |= STMP_MODULE_CLKGATE; + } + break; + case REG_CLR: + s->regval &= ~value; + break; + case REG_TOG: + s->regval ^= value; + break; + default: + break; + } +} + +static const MemoryRegionOps stmp_ops = { + .read = stmp_read, + .write = stmp_write, + .impl.min_access_size = 4, + .impl.max_access_size = 4, + .valid.min_access_size = 4, + .valid.max_access_size = 4, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void stmp_realize(DeviceState *dev, Error **errp) +{ + StmpDeviceState *s = STMP_DEVICE(dev); + + if (s->name == NULL) { + error_setg(errp, "property 'name' not specified"); + return; + } + + memory_region_init_io(&s->iomem, OBJECT(s), &stmp_ops, s, + s->name, 0x10); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); +} + +static Property stmp_properties[] = { + DEFINE_PROP_STRING("name", StmpDeviceState, name), + DEFINE_PROP_BOOL("have-reset", StmpDeviceState, have_reset, false), + DEFINE_PROP_END_OF_LIST(), +}; + +static void stmp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = stmp_realize; + device_class_set_props(dc, stmp_properties); +} + +static const TypeInfo stmp_info = { + .name = TYPE_STMP_DEVICE, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(StmpDeviceState), + .class_init = stmp_class_init, +}; + +static void stmp_register_types(void) +{ + type_register_static(&stmp_info); +} + +type_init(stmp_register_types) diff --git a/include/hw/misc/stmp.h b/include/hw/misc/stmp.h new file mode 100644 index 0000000000..941ceb25dd --- /dev/null +++ b/include/hw/misc/stmp.h @@ -0,0 +1,47 @@ +/* + * "Stmp" device + * + * Written by Guenter Roeck + */ + +#ifndef HW_MISC_STMP_H +#define HW_MISC_STMP_H + +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" + +#define TYPE_STMP_DEVICE "stmp-device" + +#define STMP_DEVICE(obj) \ + OBJECT_CHECK(StmpDeviceState, (obj), TYPE_STMP_DEVICE) + +typedef struct { + SysBusDevice parent_obj; + MemoryRegion iomem; + char *name; + bool have_reset; + uint32_t regval; +} StmpDeviceState; + +/** + * create_stmp_device: create and map a dummy device with STMP register layout + * @name: name of the device for debug logging + * @have_reset: True if the register has reset functionality + * @base: base address of the device's MMIO region + * + * This utility function creates and maps an instance of stmp-device, + * which is a dummy device which follows STMP register layout. + */ +static inline void create_stmp_device(const char *name, bool have_reset, + hwaddr base) +{ + DeviceState *dev = qdev_create(NULL, TYPE_STMP_DEVICE); + + qdev_prop_set_string(dev, "name", name); + qdev_prop_set_bit(dev, "have-reset", have_reset); + qdev_init_nofail(dev); + + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, 0); +} + +#endif From patchwork Sun Mar 1 17:04:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11414321 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1200F92A for ; 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Sun, 01 Mar 2020 09:04:53 -0800 (PST) From: Guenter Roeck To: Peter Maydell Subject: [PATCH 2/3] arm: fsl-imx6ul: Wire up USB controllers Date: Sun, 1 Mar 2020 09:04:42 -0800 Message-Id: <20200301170443.12904-3-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200301170443.12904-1-linux@roeck-us.net> References: <20200301170443.12904-1-linux@roeck-us.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" IMX6UL USB controllers are quite similar to IMX7 USB controllers. Wire them up the same way. The only real difference is that wiring up dummy phy devices is necessary to avoid phy reset timeouts in the Linux kernel. With this patch, the USB controllers on 'mcimx6ul-evk' are detected and can be used to boot the system. Signed-off-by: Guenter Roeck --- hw/arm/Kconfig | 1 + hw/arm/fsl-imx6ul.c | 35 +++++++++++++++++++++++++++++++++++ include/hw/arm/fsl-imx6ul.h | 7 +++++++ 3 files changed, 43 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 61635f52c4..d09b012c5a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -411,6 +411,7 @@ config FSL_IMX6UL select IMX_FEC select IMX_I2C select SDHCI + select STMP select UNIMP config MICROBIT diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index c405b68d1d..d2ee4cc846 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/arm/fsl-imx6ul.h" +#include "hw/misc/stmp.h" #include "hw/misc/unimp.h" #include "hw/boards.h" #include "sysemu/sysemu.h" @@ -133,6 +134,14 @@ static void fsl_imx6ul_init(Object *obj) TYPE_IMX_ENET); } + /* USB */ + for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { + snprintf(name, NAME_SIZE, "usb%d", i); + sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]), + TYPE_CHIPIDEA); + } + + /* * SDHCI */ @@ -456,6 +465,32 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_ENETn_TIMER_IRQ[i])); } + /* USB */ + for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { + static const int FSL_IMX6UL_USBn_IRQ[] = { + FSL_IMX6UL_USB2_IRQ, + FSL_IMX6UL_USB1_IRQ, + }; + + object_property_set_bool(OBJECT(&s->usb[i]), true, "realized", + &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, + FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, + qdev_get_gpio_in(DEVICE(&s->a7mpcore), + FSL_IMX6UL_USBn_IRQ[i])); + + } + create_unimplemented_device("usbmisc", FSL_IMX6UL_USBO2_USBMISC_ADDR, + 0x200); + create_unimplemented_device("usbphy1", FSL_IMX6UL_USBPHY1_ADDR, + FSL_IMX6UL_USBPHY1_SIZE); + create_stmp_device("usbphy1-stmp", true, FSL_IMX6UL_USBPHY1_ADDR + 0x30); + create_unimplemented_device("usbphy2", FSL_IMX6UL_USBPHY2_ADDR, + FSL_IMX6UL_USBPHY2_SIZE); + create_stmp_device("usbphy2-stmp", true, FSL_IMX6UL_USBPHY2_ADDR + 0x30); + /* * USDHC */ diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index eda389aec7..ae738bd5ea 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -34,6 +34,7 @@ #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" #include "hw/net/imx_fec.h" +#include "hw/usb/chipidea.h" #include "exec/memory.h" #include "cpu.h" @@ -54,6 +55,7 @@ enum FslIMX6ULConfiguration { FSL_IMX6UL_NUM_I2CS = 4, FSL_IMX6UL_NUM_ECSPIS = 4, FSL_IMX6UL_NUM_ADCS = 2, + FSL_IMX6UL_NUM_USBS = 2, }; typedef struct FslIMX6ULState { @@ -77,6 +79,7 @@ typedef struct FslIMX6ULState { IMXFECState eth[FSL_IMX6UL_NUM_ETHS]; SDHCIState usdhc[FSL_IMX6UL_NUM_USDHCS]; IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS]; + ChipideaState usb[FSL_IMX6UL_NUM_USBS]; MemoryRegion rom; MemoryRegion caam; MemoryRegion ocram; @@ -145,6 +148,10 @@ enum FslIMX6ULMemoryMap { FSL_IMX6UL_EPIT2_ADDR = 0x020D4000, FSL_IMX6UL_EPIT1_ADDR = 0x020D0000, FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000, + FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000, + FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024), + FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000, + FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024), FSL_IMX6UL_ANALOG_ADDR = 0x020C8000, FSL_IMX6UL_CCM_ADDR = 0x020C4000, FSL_IMX6UL_WDOG2_ADDR = 0x020C0000, From patchwork Sun Mar 1 17:04:43 2020 Content-Type: text/plain; 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Sun, 01 Mar 2020 09:04:55 -0800 (PST) From: Guenter Roeck To: Peter Maydell Subject: [PATCH 3/3] hw/arm/fsl-imx6: Wire up USB controllers Date: Sun, 1 Mar 2020 09:04:43 -0800 Message-Id: <20200301170443.12904-4-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200301170443.12904-1-linux@roeck-us.net> References: <20200301170443.12904-1-linux@roeck-us.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" With this patch, the USB controllers on 'sabrelite' are detected and can be used to boot the system. Signed-off-by: Guenter Roeck --- hw/arm/Kconfig | 2 ++ hw/arm/fsl-imx6.c | 36 ++++++++++++++++++++++++++++++++++++ include/hw/arm/fsl-imx6.h | 3 +++ 3 files changed, 41 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index d09b012c5a..5d12b0f686 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -361,6 +361,8 @@ config FSL_IMX6 select IMX_FEC select IMX_I2C select SDHCI + select STMP + select UNIMP config ASPEED_SOC bool diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index ecc62855f2..9a4a0eb35e 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -22,6 +22,8 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/arm/fsl-imx6.h" +#include "hw/misc/stmp.h" +#include "hw/misc/unimp.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "sysemu/sysemu.h" @@ -86,6 +88,12 @@ static void fsl_imx6_init(Object *obj) TYPE_IMX_USDHC); } + for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { + snprintf(name, NAME_SIZE, "usb%d", i); + sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]), + TYPE_CHIPIDEA); + } + for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { snprintf(name, NAME_SIZE, "spi%d", i + 1); sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]), @@ -349,6 +357,34 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) esdhc_table[i].irq)); } + /* USB */ + for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { + static const int FSL_IMX6_USBn_IRQ[] = { + FSL_IMX6_USB_OTG_IRQ, + FSL_IMX6_USB_HOST1_IRQ, + FSL_IMX6_USB_HOST2_IRQ, + FSL_IMX6_USB_HOST3_IRQ, + }; + + object_property_set_bool(OBJECT(&s->usb[i]), true, "realized", + &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, + FSL_IMX6_USBOH3_USB_ADDR + i * 0x200); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, + qdev_get_gpio_in(DEVICE(&s->a9mpcore), + FSL_IMX6_USBn_IRQ[i])); + + } + create_unimplemented_device("usbmisc", FSL_IMX6_USBOH3_USB_ADDR + 0x800, + 0x200); + create_unimplemented_device("usbphy1", FSL_IMX6_USBPHY1_ADDR, + FSL_IMX6_USBPHY1_SIZE); + create_stmp_device("usbphy1-stmp", true, FSL_IMX6_USBPHY1_ADDR + 0x30); + create_unimplemented_device("usbphy2", FSL_IMX6_USBPHY2_ADDR, + FSL_IMX6_USBPHY2_SIZE); + create_stmp_device("usbphy2-stmp", true, FSL_IMX6_USBPHY2_ADDR + 0x30); + /* Initialize all ECSPI */ for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { static const struct { diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 60eadccb42..a3d1f34598 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -30,6 +30,7 @@ #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" #include "hw/net/imx_fec.h" +#include "hw/usb/chipidea.h" #include "exec/memory.h" #include "cpu.h" @@ -44,6 +45,7 @@ #define FSL_IMX6_NUM_ESDHCS 4 #define FSL_IMX6_NUM_ECSPIS 5 #define FSL_IMX6_NUM_WDTS 2 +#define FSL_IMX6_NUM_USBS 4 typedef struct FslIMX6State { /*< private >*/ @@ -62,6 +64,7 @@ typedef struct FslIMX6State { SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS]; IMXSPIState spi[FSL_IMX6_NUM_ECSPIS]; IMX2WdtState wdt[FSL_IMX6_NUM_WDTS]; + ChipideaState usb[FSL_IMX6_NUM_USBS]; IMXFECState eth; MemoryRegion rom; MemoryRegion caam;