From patchwork Tue Mar 10 19:48:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 11430191 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6D6FB138D for ; Tue, 10 Mar 2020 19:49:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 364B921655 for ; Tue, 10 Mar 2020 19:49:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TMgpPbxw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727112AbgCJTta (ORCPT ); Tue, 10 Mar 2020 15:49:30 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:43033 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726545AbgCJTt3 (ORCPT ); Tue, 10 Mar 2020 15:49:29 -0400 Received: by mail-pf1-f194.google.com with SMTP id c144so6973584pfb.10; Tue, 10 Mar 2020 12:49:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x7SlQ0bsHgZszwUhHBadIYsQ2+v9rQS255Bp3qcZsTY=; b=TMgpPbxw0ko1PC3JxLulVtx+EOtLWWSi8eXOYfPX2GTCpCdg/2lBdl98IKRRz0wAl9 IoedTvSKkzCXBvqx5h1q3KndXz802MaIrSE9GolGUs+oSaC9vCe1dRkMUzq2axRyiJnX j+oXEAIEvIAKugR+isAITSQIptoiGEUUg3W7bjQJrqoHScpWtGRl/f2HSEN3u3/eWRDx ZkbrwCYemc7nuKSphAFtpDszAPf9sjlfhfRnnS1VNTNb/B4WuuxClKLMVnf96/w2CBFU Y2XKEeI/nwSLzWsq0Otj1JC28ETShWQNQuHb/V6u9uAmFkZASm/IaXpqIKYzDrPqqAY5 SzbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x7SlQ0bsHgZszwUhHBadIYsQ2+v9rQS255Bp3qcZsTY=; b=symvPdsC2NFHNooUAwKkVT1Lzlj9kIXuCatfudc3eymBQJtfz7MAQlkDfZh4CaS2B+ co5FThAzOfWBElZQOd4ZKpMeYMjLqsfpK0csCmoHzhxxSXO3sCJUkgKyyI5gkURIcGZn XrxGMSmRV3XGxo/oUDsXNTU1GftUw4/2pd52HE+TQJtV1ImDUOvlRsqMmJP/whue+CFW MXqdTV88Qh7RvdTnoO2bT09fYiGSUeX79zZ5MUY6WMqIgZ5L0NsFT795/IkQNQKFTf8j 2E9A2EKB2w8DSxgPCyhaECeqriliQVppucmx11ZN8JrMBrNrL/2SlPn0c2RmyNyY42yp d8YA== X-Gm-Message-State: ANhLgQ2VJ1t6GUtMUXJIxaDzYWrS7cy3JEExgXVVuxBJ3IkbbHSgEgqU oao9HAZf0rgDRggPddzAvlMNrnjE X-Google-Smtp-Source: ADFU+vsX0s58xHBrZiNWhQNZ4+BYI9nXUKflY0WKkor13fnLHK+tPp5d03Uw5SXrCIjLbznhdB/0EA== X-Received: by 2002:a62:880f:: with SMTP id l15mr3796070pfd.218.1583869768082; Tue, 10 Mar 2020 12:49:28 -0700 (PDT) Received: from localhost.localdomain ([45.114.62.228]) by smtp.gmail.com with ESMTPSA id d19sm3784490pfd.82.2020.03.10.12.49.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 12:49:27 -0700 (PDT) From: Anand Moon To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Kukjin Kim , Krzysztof Kozlowski , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Felipe Balbi , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Rob Herring Subject: [PATCHv3 1/5] devicetree: bindings: exynos: Add new compatible for Exynos5420 dwc3 clocks support Date: Tue, 10 Mar 2020 19:48:50 +0000 Message-Id: <20200310194854.831-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200310194854.831-1-linux.amoon@gmail.com> References: <20200310194854.831-1-linux.amoon@gmail.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add the new compatible string for Exynos5422 DWC3 to support enable/disable of core and suspend clk by DWC3 driver. Also updated the clock names for compatible samsung,exynos5420-dwusb3. Acked-by: Rob Herring Signed-off-by: Anand Moon --- Documentation/devicetree/bindings/usb/exynos-usb.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt index 6aae1544f240..220f729ac8eb 100644 --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt @@ -69,7 +69,9 @@ DWC3 Required properties: - compatible: should be one of the following - "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on - Exynos5250/5420. + Exynos5250. + "samsung,exynos5420-dwusb3": for USB 3.0 DWC3 controller on + Exynos5420. "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on Exynos5433. "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7. @@ -82,6 +84,7 @@ Required properties: Following clock names shall be provided for different compatibles: - samsung,exynos5250-dwusb3: "usbdrd30", + - samsung,exynos5420-dwusb3: "usbdrd30", "usbdrd30_susp_clk", - samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk", "phyclk", - samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk", From patchwork Tue Mar 10 19:48:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 11430203 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EFA24924 for ; Tue, 10 Mar 2020 19:49:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BC0B721D7E for ; Tue, 10 Mar 2020 19:49:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rhryD9cR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727520AbgCJTte (ORCPT ); Tue, 10 Mar 2020 15:49:34 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:40790 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726545AbgCJTte (ORCPT ); Tue, 10 Mar 2020 15:49:34 -0400 Received: by mail-pg1-f195.google.com with SMTP id t24so6781003pgj.7; Tue, 10 Mar 2020 12:49:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BlRRGob7J72IN5GyJz6pdMyom8cMcGq7qyRKyuALUpg=; b=rhryD9cRP9JWGlYM8BmlNtISu5pjR9nG0ynqwsbi6rIQ85sDJW03idDEW23s+vAirS WMX7E0seO5cpkiDSidLDDQJ/p/IdhM6inTTy9NNR6PHYvav6Jl5Ewuosa+e7jVL54r8p N3TT6tp9tBm9wlWi/XGfiWkyyUSYqm4nyzeYzEKfybMl6Fy/hV40g5/UwrTfg2fHW3Qx XoTkiIPQ7RVeP2dpTVuzBRhxGGtBR7QEZZAEPQ5B6Dsz9UfDSQS+m7PrF7/NajedMuOO XEIFHu0sY/dWoqSsCr1cY8IDT79KmBbVkAeJZqVMGSjVA9RaKBeHxaonyE0DH7vbFFhc bo/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BlRRGob7J72IN5GyJz6pdMyom8cMcGq7qyRKyuALUpg=; b=JmWQaSAkOJuyaxmAFNeeYfEryEcy3dTqHp1hRiiyPh2XIcu0QhYxl+k5h5k3qUnXso uEvJFJ4HTUyrV5EC/AnBV/CCJisL4vO1qEToSpMlD3QfdaOB/YEYYYr16S2i1ReqPvZ8 F2mTW6Bnof5ZoxUybLkHfkLH0LS2CAcv7K0J+TyaRt/8Q2awhpWBPtS+0CwZtD5ZzQ55 VehxljqRPz4SkxKDR9UElvtOkZembf+94RzO6lPgItnC599Bo5Qyvvda2//T2MqroRtt imYMyLl1Onzl3EFWF55rMSeZ1Ulva8wvKcR4vbUqfJLX1QveBKBFF+ywl/L5BMCK2tdJ ShOA== X-Gm-Message-State: ANhLgQ2IhxOGRi3Z5KU1V6zpXy67uIKPw1/rwzSI3Pbr6bt/hHhf7cuq 3iYm3sA8J7UM/uGC5v60bI6RY2Yt X-Google-Smtp-Source: ADFU+vtmfAWTjZEtzSy0EMp+kn2zIUsbV2u8IvW/1uuQblViS/0RtEbYS8Ss0AIaLMQ1+5H/3oUNAQ== X-Received: by 2002:a63:fe58:: with SMTP id x24mr19572503pgj.170.1583869773118; Tue, 10 Mar 2020 12:49:33 -0700 (PDT) Received: from localhost.localdomain ([45.114.62.228]) by smtp.gmail.com with ESMTPSA id d19sm3784490pfd.82.2020.03.10.12.49.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 12:49:32 -0700 (PDT) From: Anand Moon To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Kukjin Kim , Krzysztof Kozlowski , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Felipe Balbi , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd Subject: [PATCHv3 2/5] ARM: dts: exynos: Add missing usbdrd3 suspend clk Date: Tue, 10 Mar 2020 19:48:51 +0000 Message-Id: <20200310194854.831-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200310194854.831-1-linux.amoon@gmail.com> References: <20200310194854.831-1-linux.amoon@gmail.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add new compatible strings for USBDRD3 for adding missing suspend clk, exynos5422 usbdrd3 support two clk USBD300 and SCLK_USBD300, so add missing suspemd_clk for Exynos542x DWC3 nodes. Signed-off-by: Anand Moon --- fix the commit message --- arch/arm/boot/dts/exynos5410.dtsi | 8 ++++---- arch/arm/boot/dts/exynos5420.dtsi | 8 ++++---- arch/arm/boot/dts/exynos54xx.dtsi | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 2eab80bf5f3a..19845dcd528f 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -396,8 +396,8 @@ &trng { }; &usbdrd3_0 { - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>; + clock-names = "usbdrd30", "usbdrd30_susp_clk"; }; &usbdrd_phy0 { @@ -407,8 +407,8 @@ &usbdrd_phy0 { }; &usbdrd3_1 { - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>; + clock-names = "usbdrd30", "usbdrd30_susp_clk"; }; &usbdrd_dwc3_1 { diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b672080e7469..bd505256a223 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -1372,8 +1372,8 @@ &trng { }; &usbdrd3_0 { - clocks = <&clock CLK_USBD300>; - clock-names = "usbdrd30"; + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>; + clock-names = "usbdrd30", "usbdrd30_susp_clk"; }; &usbdrd_phy0 { @@ -1383,8 +1383,8 @@ &usbdrd_phy0 { }; &usbdrd3_1 { - clocks = <&clock CLK_USBD301>; - clock-names = "usbdrd30"; + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>; + clock-names = "usbdrd30", "usbdrd30_susp_clk"; }; &usbdrd_dwc3_1 { diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 8aa5117e58ce..0aac6255de5d 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -143,7 +143,7 @@ hsi2c_7: i2c@12cd0000 { }; usbdrd3_0: usb3-0 { - compatible = "samsung,exynos5250-dwusb3"; + compatible = "samsung,exynos5420-dwusb3"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -165,7 +165,7 @@ usbdrd_phy0: phy@12100000 { }; usbdrd3_1: usb3-1 { - compatible = "samsung,exynos5250-dwusb3"; + compatible = "samsung,exynos5420-dwusb3"; #address-cells = <1>; #size-cells = <1>; ranges; From patchwork Tue Mar 10 19:48:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 11430207 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 235A517D5 for ; Tue, 10 Mar 2020 19:49:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF84C208E4 for ; Tue, 10 Mar 2020 19:49:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EV6ESjvM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727558AbgCJTtl (ORCPT ); Tue, 10 Mar 2020 15:49:41 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:42870 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726545AbgCJTtl (ORCPT ); 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Tue, 10 Mar 2020 12:49:38 -0700 (PDT) Received: from localhost.localdomain ([45.114.62.228]) by smtp.gmail.com with ESMTPSA id d19sm3784490pfd.82.2020.03.10.12.49.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 12:49:37 -0700 (PDT) From: Anand Moon To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Kukjin Kim , Krzysztof Kozlowski , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Felipe Balbi , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd Subject: [PATCHv3 3/5] ARM: dts: exynos: Add FSYS power domain to Exynos542x USB nodes Date: Tue, 10 Mar 2020 19:48:52 +0000 Message-Id: <20200310194854.831-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200310194854.831-1-linux.amoon@gmail.com> References: <20200310194854.831-1-linux.amoon@gmail.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add a power domain FSYS for USB 3.0 and USB 2.0 and pdma nodes present on Exynos542x/5800 SoCs. Signed-off-by: Anand Moon --- New patch in this series. --- arch/arm/boot/dts/exynos5420.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index bd505256a223..4046b669b105 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -396,6 +396,13 @@ msc_pd: power-domain@10044120 { label = "MSC"; }; + fsys_pd: power-domain@10044140 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10044140 0x20>; + #power-domain-cells = <0>; + label = "FSYS"; + }; + pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13400000 0x1000>; @@ -461,6 +468,7 @@ pdma0: pdma@121a0000 { #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + power-domains = <&fsys_pd>; }; pdma1: pdma@121b0000 { @@ -472,6 +480,7 @@ pdma1: pdma@121b0000 { #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + power-domains = <&fsys_pd>; }; mdma0: mdma@10800000 { @@ -1374,17 +1383,20 @@ &trng { &usbdrd3_0 { clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>; clock-names = "usbdrd30", "usbdrd30_susp_clk"; + power-domains = <&fsys_pd>; }; &usbdrd_phy0 { clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; clock-names = "phy", "ref"; samsung,pmu-syscon = <&pmu_system_controller>; + power-domains = <&fsys_pd>; }; &usbdrd3_1 { clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>; clock-names = "usbdrd30", "usbdrd30_susp_clk"; + power-domains = <&fsys_pd>; }; &usbdrd_dwc3_1 { @@ -1395,16 +1407,19 @@ &usbdrd_phy1 { clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; clock-names = "phy", "ref"; samsung,pmu-syscon = <&pmu_system_controller>; + power-domains = <&fsys_pd>; }; &usbhost1 { clocks = <&clock CLK_USBH20>; clock-names = "usbhost"; + power-domains = <&fsys_pd>; }; &usbhost2 { clocks = <&clock CLK_USBH20>; clock-names = "usbhost"; + power-domains = <&fsys_pd>; }; &usb2_phy { @@ -1412,6 +1427,7 @@ &usb2_phy { clock-names = "phy", "ref"; samsung,sysreg-phandle = <&sysreg_system_controller>; samsung,pmureg-phandle = <&pmu_system_controller>; + power-domains = <&fsys_pd>; }; &watchdog { From patchwork Tue Mar 10 19:48:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 11430215 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1779D138D for ; Tue, 10 Mar 2020 19:49:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D4A0421D7E for ; Tue, 10 Mar 2020 19:49:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ryl8SeA+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727582AbgCJTtq (ORCPT ); Tue, 10 Mar 2020 15:49:46 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:45622 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726545AbgCJTtp (ORCPT ); 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Tue, 10 Mar 2020 12:49:43 -0700 (PDT) Received: from localhost.localdomain ([45.114.62.228]) by smtp.gmail.com with ESMTPSA id d19sm3784490pfd.82.2020.03.10.12.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 12:49:42 -0700 (PDT) From: Anand Moon To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Kukjin Kim , Krzysztof Kozlowski , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Felipe Balbi , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd Subject: [PATCHv3 4/5] usb: dwc3: exynos: Add support for Exynos5422 suspend clk Date: Tue, 10 Mar 2020 19:48:53 +0000 Message-Id: <20200310194854.831-5-linux.amoon@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200310194854.831-1-linux.amoon@gmail.com> References: <20200310194854.831-1-linux.amoon@gmail.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos5422 DWC3 module support two clk USBD300 and SCLK_USBD300 so add missing code to enable/disable code and suspend clk, for this add a new compatible samsung,exynos5420-dwusb3 to help configure dwc3 code and dwc3 suspend clock. Suspend clock controls the PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition. Signed-off-by: Anand Moon --- drivers/usb/dwc3/dwc3-exynos.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c index 90bb022737da..48b68b6f0dc8 100644 --- a/drivers/usb/dwc3/dwc3-exynos.c +++ b/drivers/usb/dwc3/dwc3-exynos.c @@ -162,6 +162,12 @@ static const struct dwc3_exynos_driverdata exynos5250_drvdata = { .suspend_clk_idx = -1, }; +static const struct dwc3_exynos_driverdata exynos5420_drvdata = { + .clk_names = { "usbdrd30", "usbdrd30_susp_clk"}, + .num_clks = 2, + .suspend_clk_idx = 1, +}; + static const struct dwc3_exynos_driverdata exynos5433_drvdata = { .clk_names = { "aclk", "susp_clk", "pipe_pclk", "phyclk" }, .num_clks = 4, @@ -178,6 +184,9 @@ static const struct of_device_id exynos_dwc3_match[] = { { .compatible = "samsung,exynos5250-dwusb3", .data = &exynos5250_drvdata, + }, { + .compatible = "samsung,exynos5420-dwusb3", + .data = &exynos5420_drvdata, }, { .compatible = "samsung,exynos5433-dwusb3", .data = &exynos5433_drvdata, From patchwork Tue Mar 10 19:48:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 11430219 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AAE2718E8 for ; Tue, 10 Mar 2020 19:49:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 73928222D9 for ; Tue, 10 Mar 2020 19:49:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QxA1mfJN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727610AbgCJTtu (ORCPT ); Tue, 10 Mar 2020 15:49:50 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:36940 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726545AbgCJTtt (ORCPT ); Tue, 10 Mar 2020 15:49:49 -0400 Received: by mail-pl1-f196.google.com with SMTP id f16so3710759plj.4; Tue, 10 Mar 2020 12:49:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z9ZKe9DPK55G94wFxazjpOuNWkVTtqx7CppQ9HO6NqY=; b=QxA1mfJNuNo101umOeAqQ1YfnCfKPylu4nJIhD8ICZb+kA1lQjLgkrzbxjk25h9SQr pZ5PkAaIlTsqDsvLkgZqL3tlvvp1XW9cPNAyB78bh/rEsJurcqd5DWeG30lDAWmR39Ad uW7KbxfzTH4jlBTd0WHwYTYPNKorO5VQDSD4WM6EKOJZ9tIt3gq3Lq/jWHo2sQ/r/y+A DhW3HSUJ0GFiNByu57by+d8FfdQSqK2BDl3J4+4tGoo0iMBayPuPQlUu9G4ljDYR0c3S VZV0FovHyoTyzy2UMcwIU/SDGBlzJh2RwIVQYo9kTDPW0n2g3u8GRg7K4BwXTRIaLJrj rgnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z9ZKe9DPK55G94wFxazjpOuNWkVTtqx7CppQ9HO6NqY=; b=ozCrQqrN4rAO42l8Q7jg0MTW7TFwwswtHOoIrpk0TbOO/9R2jjsp44FGpeoX98vAkD k7a2Rm+xFur1et9prLkU1YbXAK/bFwUiWlD9Ouegj49qXTQQLrxPLhGZPsHjYDRL/z1/ 8EPEoqckzebsIQb3SB5TW6HwugohFMvf1TSj/mQkOFs6LJGau4dEz1YKR23VtN3t1Oz/ U+M4NhKcUhDsNhsUtSwFIRXQ+x5Sjqd0CWrHKSParN8H3qRfVRIG79N/lJMLZHZU+a/b 7g7QrS57hGJ+msSSKLTM3Dt+DcgOWvgfnAslvtNlojeY5gIjCB5pVlayNH0WD3d9JysD 1oRQ== X-Gm-Message-State: ANhLgQ3SuP0am/RHAy1YkmPHyAhcF7k/i2SA2cvOiuvLr6/VijVn6EAO AwYiZ+VpH7fwKSncboSSnuICXkNi X-Google-Smtp-Source: ADFU+vttShOB0et+FIE14Un1vRU7k4VYoJ6iz35zEx98edQYoJE8W2h24Jqu/B/zyrxKywi6Kqvs+A== X-Received: by 2002:a17:902:9b95:: with SMTP id y21mr8418083plp.101.1583869788247; Tue, 10 Mar 2020 12:49:48 -0700 (PDT) Received: from localhost.localdomain ([45.114.62.228]) by smtp.gmail.com with ESMTPSA id d19sm3784490pfd.82.2020.03.10.12.49.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 12:49:47 -0700 (PDT) From: Anand Moon To: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Kukjin Kim , Krzysztof Kozlowski , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Felipe Balbi , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd Subject: [PATCHv3 5/5] clk: samsung: exynos542x: Move FSYS subsystem clocks to its sub-CMU Date: Tue, 10 Mar 2020 19:48:54 +0000 Message-Id: <20200310194854.831-6-linux.amoon@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200310194854.831-1-linux.amoon@gmail.com> References: <20200310194854.831-1-linux.amoon@gmail.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org FSYS power domain support usbdrd3, pdma and usb2 power gaiting, hence move FSYS clk setting to sub-CMU block to support power domain on/off sequences for device nodes. Signed-off-by: Anand Moon --- New patch in the series --- drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++------- 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index c9e5a1fb6653..6c4c47dfcdce 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), - /* USB3.0 */ - DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), - DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), - DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), - DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), - /* MMC */ DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), @@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { /* FSYS Block */ GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), - GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), - GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), @@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), GATE(CLK_SROMC, "sromc", "aclk200_fsys2", GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), - GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), - GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), - GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), @@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ }; +/* USB3.0 */ +static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = { + DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), + DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), + DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), + DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), +}; + +static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = { + GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), + GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), + GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), + GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), + GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), +}; + +static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = { + { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */ + { SRC_TOP3, 0, BIT(24) }, /* SW_MUX_PCLK_200_FSYS_SEL */ + { SRC_TOP3, 0, BIT(28) }, /* SW_MUX_ACLK_200_FSYS_SEL */ +}; + static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = { GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, CLK_SET_RATE_PARENT, 0), @@ -1376,12 +1387,23 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = { .pd_name = "MAU", }; +static const struct exynos5_subcmu_info exynos5x_fsys_subcmu = { + .div_clks = exynos5x_fsys_div_clks, + .nr_div_clks = ARRAY_SIZE(exynos5x_fsys_div_clks), + .gate_clks = exynos5x_fsys_gate_clks, + .nr_gate_clks = ARRAY_SIZE(exynos5x_fsys_gate_clks), + .suspend_regs = exynos5x_fsys_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(exynos5x_fsys_suspend_regs), + .pd_name = "FSYS", +}; + static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { &exynos5x_disp_subcmu, &exynos5x_gsc_subcmu, &exynos5x_g3d_subcmu, &exynos5x_mfc_subcmu, &exynos5x_mscl_subcmu, + &exynos5x_fsys_subcmu, }; static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { @@ -1391,6 +1413,7 @@ static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { &exynos5x_mfc_subcmu, &exynos5x_mscl_subcmu, &exynos5800_mau_subcmu, + &exynos5x_fsys_subcmu, }; static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {