From patchwork Wed Mar 11 15:47:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11432007 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C0A01392 for ; Wed, 11 Mar 2020 15:44:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2BC94206F7 for ; Wed, 11 Mar 2020 15:44:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="XwZt0epa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730020AbgCKPoq (ORCPT ); Wed, 11 Mar 2020 11:44:46 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:15042 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730084AbgCKPoq (ORCPT ); Wed, 11 Mar 2020 11:44:46 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 11 Mar 2020 08:43:14 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 11 Mar 2020 08:44:45 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 11 Mar 2020 08:44:45 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 11 Mar 2020 15:44:44 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 11 Mar 2020 15:44:44 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.232]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 11 Mar 2020 08:44:44 -0700 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , Subject: [PATCH v2 1/2] sdhci: tegra: Implement Tegra specific set_timeout callback Date: Wed, 11 Mar 2020 08:47:54 -0700 Message-ID: <1583941675-9884-1-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1583941394; bh=3TyCKOUEa+ZZzPxPPgj5u5wAYNCe+MYCECoIl/e8ZLs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:Content-Type; b=XwZt0epaa0LqHQLVK6GUCGw5hNKoBEHv0flyVu7com3kh1JzvFkV+nrYbUdrkwD6G n453xOBDNzhdRroNvYIvyxAQWRU71XQ25QNY3O5TUp62kXCfLiV3jRJxfije75fZ47 tsw9cDmluLMcMzKKVTp7ZNdWPo5Dv2TFDkPBbRqBtOAQe8vwMHxozyhz5Trfc8Wd4k DxK66eKgKeq3GKZZIMpB8uihZwexORsDT4hEwX5dZQdT/xhL+EG6Mh8VEoyX4LJ6RB nPyJOlKnv+bC2IFs8y2lH9h6//siq7eNSfaO2bTTfNShL7wLOH38fL5VDsDcZQ2Qq7 ldXB2348ZT3gQ== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Tegra host supports HW busy detection and timeouts based on the count programmed in SDHCI_TIMEOUT_CONTROL register and max busy timeout it supports is 11s in finite busy wait mode. Some operations like SLEEP_AWAKE, ERASE and flush cache through SWITCH commands take longer than 11s and Tegra host supports infinite HW busy wait mode where HW waits forever till the card is busy without HW timeout. This patch implements Tegra specific set_timeout sdhci_ops to allow switching between finite and infinite HW busy detection wait modes based on the device command expected operation time. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a25c3a4..fa8f6a4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -45,6 +45,7 @@ #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 +#define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0) #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 @@ -1227,6 +1228,34 @@ static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) return 0; } +static void tegra_sdhci_set_timeout(struct sdhci_host *host, + struct mmc_command *cmd) +{ + u32 val; + + /* + * HW busy detection timeout is based on programmed data timeout + * counter and maximum supported timeout is 11s which may not be + * enough for long operations like cache flush, sleep awake, erase. + * + * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows + * host controller to wait for busy state until the card is busy + * without HW timeout. + * + * So, use infinite busy wait mode for operations that may take + * more than maximum HW busy timeout of 11s otherwise use finite + * busy wait mode. + */ + val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); + if (cmd && cmd->busy_timeout >= 11 * HZ) + val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; + else + val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; + sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL); + + __sdhci_set_timeout(host, cmd); +} + static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { .write_l = tegra_cqhci_writel, .enable = sdhci_tegra_cqe_enable, @@ -1366,6 +1395,7 @@ static const struct sdhci_ops tegra210_sdhci_ops = { .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, .voltage_switch = tegra_sdhci_voltage_switch, .get_max_clock = tegra_sdhci_get_max_clock, + .set_timeout = tegra_sdhci_set_timeout, }; static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { @@ -1403,6 +1433,7 @@ static const struct sdhci_ops tegra186_sdhci_ops = { .voltage_switch = tegra_sdhci_voltage_switch, .get_max_clock = tegra_sdhci_get_max_clock, .irq = sdhci_tegra_cqhci_irq, + .set_timeout = tegra_sdhci_set_timeout, }; static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { From patchwork Wed Mar 11 15:47:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11432005 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69BC51392 for ; Wed, 11 Mar 2020 15:44:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 58BE5206F1 for ; Wed, 11 Mar 2020 15:44:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="hkTby4UT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730097AbgCKPor (ORCPT ); Wed, 11 Mar 2020 11:44:47 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:6057 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729988AbgCKPoq (ORCPT ); Wed, 11 Mar 2020 11:44:46 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 11 Mar 2020 08:44:32 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 11 Mar 2020 08:44:45 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 11 Mar 2020 08:44:45 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 11 Mar 2020 15:44:45 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 11 Mar 2020 15:44:45 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.232]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 11 Mar 2020 08:44:45 -0700 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , Subject: [PATCH v2 2/2] sdhci: tegra: Enable MMC_CAP_WAIT_WHILE_BUSY host capability Date: Wed, 11 Mar 2020 08:47:55 -0700 Message-ID: <1583941675-9884-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1583941675-9884-1-git-send-email-skomatineni@nvidia.com> References: <1583941675-9884-1-git-send-email-skomatineni@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1583941472; bh=WQbMCJ65f2TyXJ8ZQ5LpK0swY2bTxKhl2kWonRDVGlg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=hkTby4UTOPzILHAEceijMzbErmsugOXxjJC5qw2ukJwZYQUd20PtJhyz+5MnMGYF6 9e+W1QbQEKtV48GQAG6jprUnbh6mqYZkDBTxejnaCPHuVtKHYBJVResGq+IutvNpMm gotjtBTep3zDq8p/bzMFkBnNpmEjEE8Ev3amB4VBFe+VuFsCari5tjEfrU1JRhUO3y KvrCWZaaqvaScgkOzwiBnZd5GM9LP0Z39lw4IIUjaPs4t9yjJlGS2GyOrkI/atiFln q2/AkvHV5euF7d69m+lHpcIIiG6nuJCRiVRMAmQAbkrR2nEPmGsucbi65F9dbnShVB L5Ia7XqIB6+nA== Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Tegra sdhci host supports HW busy detection of the device busy signaling over data0 lane. So, this patch enables host capability MMC_CAP_wAIT_WHILE_BUSY. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index fa8f6a4..1c381f8 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1580,6 +1580,8 @@ static int sdhci_tegra_probe(struct platform_device *pdev) if (rc) goto err_parse_dt; + host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; + if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) host->mmc->caps |= MMC_CAP_1_8V_DDR;