From patchwork Thu Mar 12 00:34:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 11433081 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 038786CA for ; Thu, 12 Mar 2020 00:35:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96188206B1 for ; Thu, 12 Mar 2020 00:35:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="xddIzZal" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 96188206B1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:60038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCBpF-0004zb-Jg for patchwork-qemu-devel@patchwork.kernel.org; Wed, 11 Mar 2020 20:35:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54247) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCBoP-0003eB-Tt for qemu-devel@nongnu.org; Wed, 11 Mar 2020 20:34:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCBoO-0002rV-JR for qemu-devel@nongnu.org; Wed, 11 Mar 2020 20:34:57 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:53775) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jCBoO-0002pI-Dm for qemu-devel@nongnu.org; Wed, 11 Mar 2020 20:34:56 -0400 Received: by mail-wm1-x342.google.com with SMTP id 25so4215263wmk.3 for ; Wed, 11 Mar 2020 17:34:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rXYfzcBdKI5ubAvqSEIb2KdH42aC5HB1minn7mytn4g=; b=xddIzZalQNmm/l4Gy0NEAYwaXcrL17gpkIXF++rfjqb/ruGOmFVAKecoP++D7PRuvL cAvRDXQO9Xrg+CDrABN5YPbFnDe3rz3lOHwHiXznBXEiNJbIxoTlSZUAtfwd9vbA/TT9 wsiobf57P7AdMTK4ZQkUA+KGjWxL248jgcjVX9ytdV37ENRv3shVAjaNextivR/QvmC6 KttoeU/6CMZG+wP48unX91J7j3EH680Jo9GuHk8BPe8R0qfwZfvMl04M3Sqiz776AuQG ue83r06V738R0wgVtwy4xO3sXNK81O3SK3Y4okSHrYkmM3ky38at0vNHUE9hWxBitJKl 0PGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rXYfzcBdKI5ubAvqSEIb2KdH42aC5HB1minn7mytn4g=; b=cK8RH55f+t5gemuoekQavRnFDR9HcwgeV3j51vXGgkSYtll02wzQerDUtfiRKjkM59 W7P3oG+aAsR73lnh0I4WiDU2ZQE3zeNYYdz3dBMEIUUYdCYUEMYN2DoJr/8iDTentzr7 L7/cy+MtsiiXrY0VAKsVNJAi8Nv3uaU9P436RR9rUVXL5sDWH6G/Sn4sWeI1AooqTJ7i 2b4tdvASG6Mw4LN6VcgCmd7I/hhuPGjZyYZPwUX6VUysvoZUP14yQC4OX2A+nJM7kaez dFNdPvWZxjBor8XU9Fvd/vwdAyrLXPHOjUZhGeXBY7PC2u+hNB9Yx2L8E7OKO1MsNO2P n7Ig== X-Gm-Message-State: ANhLgQ2KnSdHxhWqIqtzEq8AcXq1FKxsKaDEjwCsGA+uyjWpX4guNmv6 8iQ0TUaq/DMgs5f8w7cJE5UyWOZl2oc= X-Google-Smtp-Source: ADFU+vuOAzDFJuWFD/k+vg7UekR3WmJcRhllQB3RzppJIXyq8+JOmDdDnFIoAxQkCYoPOsWO4dsmog== X-Received: by 2002:a7b:c458:: with SMTP id l24mr1273688wmi.120.1583973295268; Wed, 11 Mar 2020 17:34:55 -0700 (PDT) Received: from moi-limbo-9350.home (host86-139-146-66.range86-139.btcentralplus.com. [86.139.146.66]) by smtp.gmail.com with ESMTPSA id o5sm10909988wmb.8.2020.03.11.17.34.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 17:34:54 -0700 (PDT) From: Beata Michalska To: qemu-devel@nongnu.org Subject: [PATCH v3 1/2] target/arm: kvm: Inject events at the last stage of sync Date: Thu, 12 Mar 2020 00:34:00 +0000 Message-Id: <20200312003401.29017-2-beata.michalska@linaro.org> In-Reply-To: <20200312003401.29017-1-beata.michalska@linaro.org> References: <20200312003401.29017-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, Christoffer.Dall@arm.com, qemu-arm@nongnu.org, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified. As such this should be the last step of sync to avoid potential overwriting of whatever changes KVM might have done. Signed-off-by: Beata Michalska Reviewed-by: Andrew Jones --- target/arm/kvm32.c | 15 ++++++++++----- target/arm/kvm64.c | 15 ++++++++++----- 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f703c4f..f271181 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -409,17 +409,22 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } - ret = kvm_put_vcpu_events(cpu); - if (ret) { - return ret; - } - write_cpustate_to_list(cpu, true); if (!write_list_to_kvmstate(cpu, level)) { return EINVAL; } + /* + * Setting VCPU events should be triggered after syncing the registers + * to avoid overwriting potential changes made by KVM upon calling + * KVM_SET_VCPU_EVENTS ioctl + */ + ret = kvm_put_vcpu_events(cpu); + if (ret) { + return ret; + } + kvm_arm_sync_mpstate_to_kvm(cpu); return ret; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 93ba144..be5b31c 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1094,17 +1094,22 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } - ret = kvm_put_vcpu_events(cpu); - if (ret) { - return ret; - } - write_cpustate_to_list(cpu, true); if (!write_list_to_kvmstate(cpu, level)) { return -EINVAL; } + /* + * Setting VCPU events should be triggered after syncing the registers + * to avoid overwriting potential changes made by KVM upon calling + * KVM_SET_VCPU_EVENTS ioctl + */ + ret = kvm_put_vcpu_events(cpu); + if (ret) { + return ret; + } + kvm_arm_sync_mpstate_to_kvm(cpu); return ret; From patchwork Thu Mar 12 00:34:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 11433083 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1436292A for ; Thu, 12 Mar 2020 00:36:04 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A75FB206B1 for ; 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[86.139.146.66]) by smtp.gmail.com with ESMTPSA id o5sm10909988wmb.8.2020.03.11.17.35.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2020 17:35:01 -0700 (PDT) From: Beata Michalska To: qemu-devel@nongnu.org Subject: [PATCH v3 2/2] target/arm: kvm: Handle DABT with no valid ISS Date: Thu, 12 Mar 2020 00:34:01 +0000 Message-Id: <20200312003401.29017-3-beata.michalska@linaro.org> In-Reply-To: <20200312003401.29017-1-beata.michalska@linaro.org> References: <20200312003401.29017-1-beata.michalska@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, Christoffer.Dall@arm.com, qemu-arm@nongnu.org, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" On ARMv7 & ARMv8 some load/store instructions might trigger a data abort exception with no valid ISS info to be decoded. The lack of decode info makes it at least tricky to emulate those instruction which is one of the (many) reasons why KVM will not even try to do so. Add support for handling those by requesting KVM to inject external dabt into the quest. Signed-off-by: Beata Michalska --- target/arm/cpu.h | 3 ++ target/arm/kvm.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm32.c | 26 +++++++++++++++++ target/arm/kvm64.c | 36 +++++++++++++++++++++++ target/arm/kvm_arm.h | 22 ++++++++++++++ 5 files changed, 168 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4ffd991..45fdd2e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -560,6 +560,9 @@ typedef struct CPUARMState { uint64_t esr; } serror; + uint8_t ext_dabt_pending:1; /* Request for injecting ext DABT */ + uint8_t ext_dabt_raised:1; /* Tracking/verifying injection of ext DABT */ + /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ uint32_t irq_line_state; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 85860e6..8b7b708 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -39,6 +39,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; +static bool cap_has_inject_ext_dabt; static ARMHostCPUFeatures arm_host_cpu_features; @@ -244,6 +245,16 @@ int kvm_arch_init(MachineState *ms, KVMState *s) ret = -EINVAL; } + if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) { + if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) { + warn_report("Failed to enable DABT NISV cap"); + } else { + /* Set status for supporting the external dabt injection */ + cap_has_inject_ext_dabt = kvm_check_extension(s, + KVM_CAP_ARM_INJECT_EXT_DABT); + } + } + return ret; } @@ -703,9 +714,20 @@ int kvm_put_vcpu_events(ARMCPU *cpu) events.exception.serror_esr = env->serror.esr; } + if (cap_has_inject_ext_dabt) { + events.exception.ext_dabt_pending = env->ext_dabt_pending; + } + ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); if (ret) { error_report("failed to put vcpu events"); + } else if (env->ext_dabt_pending) { + /* + * Mark that the external DABT has been injected, + * if one has been requested + */ + env->ext_dabt_raised = env->ext_dabt_pending; + env->ext_dabt_pending = 0; } return ret; @@ -737,6 +759,30 @@ int kvm_get_vcpu_events(ARMCPU *cpu) void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + if (unlikely(env->ext_dabt_raised)) { + /* + * Verifying that the ext DABT has been properly injected, + * otherwise risking indefinitely re-running the faulting instruction + * Covering a very narrow case for kernels 5.5..5.5.4 + * when injected abort was misconfigured to be + * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) + */ + if (!arm_feature(env, ARM_FEATURE_AARCH64) && + unlikely(kvm_arm_verify_ext_dabt_pending(cs))) { + + error_report("Data abort exception with no valid ISS generated by " + "guest memory access. KVM unable to emulate faulting " + "instruction. Failed to inject an external data abort " + "into the guest."); + abort(); + } + /* Clear the status */ + env->ext_dabt_raised = 0; + } + } MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) @@ -819,6 +865,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) ret = EXCP_DEBUG; } /* otherwise return to guest */ break; + case KVM_EXIT_ARM_NISV: + /* External DABT with no valid iss to decode */ + ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss, + run->arm_nisv.fault_ipa); + break; default: qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", __func__, run->exit_reason); @@ -953,3 +1004,33 @@ int kvm_arch_msi_data_to_gsi(uint32_t data) { return (data - 32) & 0xffff; } + +int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, + uint64_t fault_ipa) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + /* + * ISS [23:14] is invalid so there is a limited info + * on what has just happened so the only *useful* thing that can + * be retrieved from ISS is WnR & DFSC (though in some cases WnR + * might be less of a value as well) + */ + + /* + * Set pending ext dabt and trigger SET_EVENTS so that + * KVM can inject the abort + */ + if (cap_has_inject_ext_dabt) { + kvm_cpu_synchronize_state(cs); + env->ext_dabt_pending = 1; + } else { + error_report("Data abort exception triggered by guest memory access " + "at physical address: 0x" TARGET_FMT_lx, + (target_ulong)fault_ipa); + error_printf("KVM unable to emulate faulting instruction.\n"); + } + + return cap_has_inject_ext_dabt ? 0 : -1; +} diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f271181..4795a7d 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -564,3 +564,29 @@ void kvm_arm_pmu_init(CPUState *cs) { qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); } + + +#define ARM_REG_DFSR ARM_CP15_REG32(0, 5, 0, 0) +#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2) + +#define DFSR_FSC(v) (((v) >> 6 | (v)) & 0x1F) +#define DFSC_EXTABT(lpae) (lpae) ? 0x10 : 0x08 + +int kvm_arm_verify_ext_dabt_pending(CPUState *cs) +{ + uint32_t dfsr_val; + + if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) { + + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + uint32_t ttbcr; + int lpae = 0; + + if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) { + lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE); + } + return DFSR_FSC(dfsr_val) != DFSC_EXTABT(lpae); + } + return 1; +} diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index be5b31c..2f8ffc6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1430,3 +1430,39 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) return false; } + + +#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) +#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) + +#define ESR_DFSC(aarch64, v) \ + ((aarch64) ? ((v) & 0x3F) \ + : (((v) >> 6 | (v)) & 0x1F)) + +#define ESR_DFSC_EXTABT(aarch64, lpae) \ + ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) + +int kvm_arm_verify_ext_dabt_pending(CPUState *cs) +{ + uint64_t dfsr_val; + + if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); + int lpae = 0; + + if (!aarch64_mode) { + + uint64_t ttbcr; + + if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { + lpae = arm_feature(env, ARM_FEATURE_LPAE) + && (ttbcr & TTBCR_EAE); + } + } + return ESR_DFSC(aarch64_mode, dfsr_val) != + ESR_DFSC_EXTABT(aarch64_mode, lpae) ; + } + return 1; +} diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index ae9e075..777c9bf 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -450,6 +450,28 @@ struct kvm_guest_debug_arch; void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); /** + * kvm_arm_handle_dabt_nisv + * @cs: CPUState + * @esr_iss: ISS encoding (limited) for the exception from Data Abort + * ISV bit set to '0b0' -> no valid instruction syndrome + * @fault_ipa: faulting address for the synch data abort + * + * Returns: 0 if the exception has been handled + */ +int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, + uint64_t fault_ipa); + +/** + * kvm_arm_verify_ext_dabt_pending + * @cs: CPUState + * + * Verify the fault status code wrt the Ext DABT injection + * + * Returns: 0 if the fault status code is as expected, non-zero otherwise + */ +int kvm_arm_verify_ext_dabt_pending(CPUState *cs); + +/** * its_class_name: * * Return the ITS class name to use depending on whether KVM acceleration