From patchwork Thu Mar 12 13:31:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11434229 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95FF492C for ; Thu, 12 Mar 2020 13:31:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 725C7206FA for ; Thu, 12 Mar 2020 13:31:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="BJ0XuBYV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727386AbgCLNbi (ORCPT ); Thu, 12 Mar 2020 09:31:38 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:39992 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726571AbgCLNbh (ORCPT ); Thu, 12 Mar 2020 09:31:37 -0400 Received: by mail-wr1-f66.google.com with SMTP id f3so493588wrw.7 for ; Thu, 12 Mar 2020 06:31:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MQB/nJ2X838Fvt+sBkmGr/0pMCoouvYo1EdeUXM4YMQ=; b=BJ0XuBYV3ToSPW3UIl6Isc2lumsrYzXzC9pIKP6HzoLx2m5H8VgaPnkaYEyU3nSSyY 1tLzCAypjVjCczuqqKDKV1kSM0jlkColhbhQeyFQVhbrpWHVd+cqIdpfBucm5Cs8CUNT g2JsfKMI1p2KNINJQGW/uTtMsJczcoyPXXZnlpjb8lmdv/EKBNzm0oLEWDR+wc3cC7Qf DMCctXTjXci5kB54gBeQKBFgYHiFdJuJ8DwI2USTDOz+pcXtLVEBQNuo9vJANXAlIU0c /cnYnC4QN9G/AkoiOE6XME3Ja/GQJj1cvbdw9h8QOh351jbLfIus+wLy4M2iFBemZPwy BIKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MQB/nJ2X838Fvt+sBkmGr/0pMCoouvYo1EdeUXM4YMQ=; b=RjUSrusjL/hzXVxUgyCgRdzQ3Rrkp5loVT+b1mFlASqlhWm3hRLTGXi7612Kcm6hU9 8bCtZrctICDcLvArKR5EZkRv6i7XSxPsxowXmWVEeZjClKz6t9Xd5xhB0DzUxNZXnqpq 9+W5/juUbJ4QUU4tyRu2WRVAgJ3CxBuzJqcp9y0vH5ctbhwa8q4JIii+oi5KepIG5upf 9Ma2j6270FJkkvFe1uGGtfcxWZ8lrLIaWf1j+SIgPaiAhiUMezX05U4TDz4zBuETeM88 vtbWQK0DoJfHkp986Db4lWUS9VVhXutroulh66FxVCPUBnXRct0CghrRSYFkg9fNsTuP HFUQ== X-Gm-Message-State: ANhLgQ0z5WJAPv7GSnyPFn1n01zLU6Jd9Z9v7AHLSq/nCGQ+8obj+17X Aw6rQezko+DWlEUtEMd0eZIBeA== X-Google-Smtp-Source: ADFU+vttYTaI+DCiNmB1UvQy1EL7nMlpTXWyEiRnY5WHDphDcEObnDSPJFvd3uSrVxGbrKBpFiiYCQ== X-Received: by 2002:a5d:6703:: with SMTP id o3mr101991wru.137.1584019895265; Thu, 12 Mar 2020 06:31:35 -0700 (PDT) Received: from bender.baylibre.local (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id m21sm12242885wmi.27.2020.03.12.06.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 06:31:34 -0700 (PDT) From: Neil Armstrong To: broonie@kernel.org Cc: Neil Armstrong , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/9] spi: meson-spicc: remove unused variables Date: Thu, 12 Mar 2020 14:31:23 +0100 Message-Id: <20200312133131.26430-2-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200312133131.26430-1-narmstrong@baylibre.com> References: <20200312133131.26430-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Remove unused variables from spicc data struct. Signed-off-by: Neil Armstrong --- drivers/spi/spi-meson-spicc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 7f5680fe2568..8425e5ae1273 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -130,9 +130,7 @@ struct meson_spicc_device { u8 *rx_buf; unsigned int bytes_per_word; unsigned long tx_remain; - unsigned long txb_remain; unsigned long rx_remain; - unsigned long rxb_remain; unsigned long xfer_remain; bool is_burst_end; bool is_last_burst; From patchwork Thu Mar 12 13:31:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11434251 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0EEFD6CA for ; Thu, 12 Mar 2020 13:32:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E10FF206E7 for ; Thu, 12 Mar 2020 13:32:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="JrtREJLS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727458AbgCLNcK (ORCPT ); Thu, 12 Mar 2020 09:32:10 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:39206 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726571AbgCLNbk (ORCPT ); Thu, 12 Mar 2020 09:31:40 -0400 Received: by mail-wr1-f67.google.com with SMTP id r15so7491331wrx.6 for ; Thu, 12 Mar 2020 06:31:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fhKS2QmlEqe7YF4t+EF2enhYAsFiUYK9CnO2h0EUAe8=; b=JrtREJLSfg0ful938Ewd1LT16qXXEeOh8IBaTuhMKFrcRMVSBkMsuqzNmExITbxwAx D7DHgauvoRll0zTikGxpEmneu70O3SbW6peZBRqNKP6jYcKa7GSuMOb/yzbZihxYzbSb 3O6UjNb+jYyFi3ECc54Lp7HQbP8CJ/qzsvNQeXjDd1iRRw3KUv6W3spUI1OLrcG2WQPp Me6o4fhFIXmoJIKYRf9FscwDdI21KiG+HhecDAde/fajhssQOlUhbfVtp7WDgiPJPOyE UVZmzzu7xeTevXU53/NlGrZ3QkzRZcmO7vme+8SRtgJU1urmK0aIlzGmCmauoeokY1L2 lUig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fhKS2QmlEqe7YF4t+EF2enhYAsFiUYK9CnO2h0EUAe8=; b=aqxfOFkRIbXjD+cDXo2UgajhITCTRvuqC9kIzLJDK/4WBxksgPWaFu7vIndDAXWa6C ZKx0QA3h3YGCoORaXSykd0N0X8Hr69k7Ux1q/ZMhVZQRcn5AtQC9aiATjxHWVZ3uv2vo jmalaizuKWMu2IBmUnGFBdd1Hu3CM9y/pT+hfR5N58oZvdjIsEl/2uzrKUlf31fxMy9S +e5tlFvgRJ5FwtVRMgOaM/HuoL8gvR3yWJuR0ZFLtvFf1JwGB1WBxTikbgHdoGk3geYg cqvQfeFSr+9Qc/86Pz0wKOF3ITqwWhpLdQ9+bJ23fN9oRakfKmI6NaC91ycOa1x/cuEH nHeg== X-Gm-Message-State: ANhLgQ0uLOpvInKTmNTCyRuqaGJ72vVsYXfrR9OvS5CZo7doOovF1Z8H 9C/IqtqWVkGd/DdTgA+8Tl2abw== X-Google-Smtp-Source: ADFU+vt0MdII7T+2dH+DamoAkX5rNnGfgWPSAC2NKHVuJYX+JaFCSwlEQhFIHqNbvg6KRrhi9MNm9w== X-Received: by 2002:adf:9b19:: with SMTP id b25mr11104897wrc.368.1584019896447; Thu, 12 Mar 2020 06:31:36 -0700 (PDT) Received: from bender.baylibre.local (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id m21sm12242885wmi.27.2020.03.12.06.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 06:31:35 -0700 (PDT) From: Neil Armstrong To: broonie@kernel.org Cc: Sunny Luo , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yixun Lan , Neil Armstrong Subject: [PATCH 2/9] spi: meson-spicc: enhance output enable feature Date: Thu, 12 Mar 2020 14:31:24 +0100 Message-Id: <20200312133131.26430-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200312133131.26430-1-narmstrong@baylibre.com> References: <20200312133131.26430-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Sunny Luo The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS signal lines through the idle state (between two transmission operation), which avoid the signals floating in unexpected state. Signed-off-by: Sunny Luo Signed-off-by: Yixun Lan Signed-off-by: Neil Armstrong --- drivers/spi/spi-meson-spicc.c | 53 +++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 8425e5ae1273..ba70ef94a82a 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -9,11 +9,13 @@ #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -113,12 +115,23 @@ #define SPICC_DWADDR 0x24 /* Write Address of DMA */ +#define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */ +#define SPICC_ENH_MOSI_OEN BIT(25) +#define SPICC_ENH_CLK_OEN BIT(26) +#define SPICC_ENH_CS_OEN BIT(27) +#define SPICC_ENH_CLK_CS_DELAY_EN BIT(28) +#define SPICC_ENH_MAIN_CLK_AO BIT(29) + #define writel_bits_relaxed(mask, val, addr) \ writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) #define SPICC_BURST_MAX 16 #define SPICC_FIFO_HALF 10 +struct meson_spicc_data { + bool has_oen; +}; + struct meson_spicc_device { struct spi_master *master; struct platform_device *pdev; @@ -126,6 +139,7 @@ struct meson_spicc_device { struct clk *core; struct spi_message *message; struct spi_transfer *xfer; + const struct meson_spicc_data *data; u8 *tx_buf; u8 *rx_buf; unsigned int bytes_per_word; @@ -136,6 +150,19 @@ struct meson_spicc_device { bool is_last_burst; }; +static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) +{ + u32 conf; + + if (!spicc->data->has_oen) + return; + + conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | + SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; + + writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); +} + static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc) { return !!FIELD_GET(SPICC_TF, @@ -489,6 +516,13 @@ static int meson_spicc_probe(struct platform_device *pdev) spicc = spi_master_get_devdata(master); spicc->master = master; + spicc->data = of_device_get_match_data(&pdev->dev); + if (!spicc->data) { + dev_err(&pdev->dev, "failed to get match data\n"); + ret = -EINVAL; + goto out_master; + } + spicc->pdev = pdev; platform_set_drvdata(pdev, spicc); @@ -548,6 +582,8 @@ static int meson_spicc_probe(struct platform_device *pdev) else master->max_speed_hz = rate >> 2; + meson_spicc_oen_enable(spicc); + ret = devm_spi_register_master(&pdev->dev, master); if (ret) { dev_err(&pdev->dev, "spi master registration failed\n"); @@ -577,9 +613,22 @@ static int meson_spicc_remove(struct platform_device *pdev) return 0; } +static const struct meson_spicc_data meson_spicc_gx_data = { +}; + +static const struct meson_spicc_data meson_spicc_axg_data = { + .has_oen = true, +}; + static const struct of_device_id meson_spicc_of_match[] = { - { .compatible = "amlogic,meson-gx-spicc", }, - { .compatible = "amlogic,meson-axg-spicc", }, + { + .compatible = "amlogic,meson-gx-spicc", + .data = &meson_spicc_gx_data, + }, + { + .compatible = "amlogic,meson-axg-spicc", + .data = &meson_spicc_axg_data, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, meson_spicc_of_match); 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id m21sm12242885wmi.27.2020.03.12.06.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 06:31:36 -0700 (PDT) From: Neil Armstrong To: broonie@kernel.org Cc: Sunny Luo , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yixun Lan , Neil Armstrong Subject: [PATCH 3/9] spi: meson-spicc: add a linear clock divider support Date: Thu, 12 Mar 2020 14:31:25 +0100 Message-Id: <20200312133131.26430-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200312133131.26430-1-narmstrong@baylibre.com> References: <20200312133131.26430-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Sunny Luo The SPICC controller in Meson-AXG SoC is capable of using a linear clock divider to reach a much fine tuned range of clocks, while the old controller only use a power of two clock divider, result at a more coarse clock range. Also convert the clock registration into Common Clock Framework. Signed-off-by: Sunny Luo Signed-off-by: Yixun Lan Signed-off-by: Neil Armstrong --- drivers/spi/Kconfig | 1 + drivers/spi/spi-meson-spicc.c | 204 +++++++++++++++++++++++++++------- 2 files changed, 165 insertions(+), 40 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d6ed0c355954..7f86e591fba3 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -415,6 +415,7 @@ config SPI_FSL_ESPI config SPI_MESON_SPICC tristate "Amlogic Meson SPICC controller" + depends on COMMON_CLK depends on ARCH_MESON || COMPILE_TEST help This enables master mode support for the SPICC (SPI communication diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index ba70ef94a82a..bd434d9055d9 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -116,6 +116,9 @@ #define SPICC_DWADDR 0x24 /* Write Address of DMA */ #define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */ +#define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0) +#define SPICC_ENH_DATARATE_MASK GENMASK(23, 16) +#define SPICC_ENH_DATARATE_EN BIT(24) #define SPICC_ENH_MOSI_OEN BIT(25) #define SPICC_ENH_CLK_OEN BIT(26) #define SPICC_ENH_CS_OEN BIT(27) @@ -130,6 +133,7 @@ struct meson_spicc_data { bool has_oen; + bool has_enhance_clk_div; }; struct meson_spicc_device { @@ -137,6 +141,7 @@ struct meson_spicc_device { struct platform_device *pdev; void __iomem *base; struct clk *core; + struct clk *clk; struct spi_message *message; struct spi_transfer *xfer; const struct meson_spicc_data *data; @@ -322,40 +327,6 @@ static irqreturn_t meson_spicc_irq(int irq, void *data) return IRQ_HANDLED; } -static u32 meson_spicc_setup_speed(struct meson_spicc_device *spicc, u32 conf, - u32 speed) -{ - unsigned long parent, value; - unsigned int i, div; - - parent = clk_get_rate(spicc->core); - - /* Find closest inferior/equal possible speed */ - for (i = 0 ; i < 7 ; ++i) { - /* 2^(data_rate+2) */ - value = parent >> (i + 2); - - if (value <= speed) - break; - } - - /* If provided speed it lower than max divider, use max divider */ - if (i > 7) { - div = 7; - dev_warn_once(&spicc->pdev->dev, "unable to get close to speed %u\n", - speed); - } else - div = i; - - dev_dbg(&spicc->pdev->dev, "parent %lu, speed %u -> %lu (%u)\n", - parent, speed, value, div); - - conf &= ~SPICC_DATARATE_MASK; - conf |= FIELD_PREP(SPICC_DATARATE_MASK, div); - - return conf; -} - static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, struct spi_transfer *xfer) { @@ -364,9 +335,6 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, /* Read original configuration */ conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); - /* Select closest divider */ - conf = meson_spicc_setup_speed(spicc, conf, xfer->speed_hz); - /* Setup word width */ conf &= ~SPICC_BITLENGTH_MASK; conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, @@ -375,6 +343,8 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, /* Ignore if unchanged */ if (conf != conf_orig) writel_relaxed(conf, spicc->base + SPICC_CONREG); + + clk_set_rate(spicc->clk, xfer->speed_hz); } static int meson_spicc_transfer_one(struct spi_master *master, @@ -481,9 +451,6 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master) /* Disable all IRQs */ writel(0, spicc->base + SPICC_INTREG); - /* Disable controller */ - writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG); - device_reset_optional(&spicc->pdev->dev); return 0; @@ -502,6 +469,152 @@ static void meson_spicc_cleanup(struct spi_device *spi) spi->controller_state = NULL; } +/* + * The Clock Mux + * x-----------------x x------------x x------\ + * |---| pow2 fixed div |---| pow2 div |----| | + * | x-----------------x x------------x | | + * src ---| | mux |-- out + * | x-----------------x x------------x | | + * |---| enh fixed div |---| enh div |0---| | + * x-----------------x x------------x x------/ + * + * Clk path for GX series: + * src -> pow2 fixed div -> pow2 div -> out + * + * Clk path for AXG series: + * src -> pow2 fixed div -> pow2 div -> mux -> out + * src -> enh fixed div -> enh div -> mux -> out + */ + +static int meson_spicc_clk_init(struct meson_spicc_device *spicc) +{ + struct device *dev = &spicc->pdev->dev; + struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div; + struct clk_divider *pow2_div, *enh_div; + struct clk_mux *mux; + struct clk_init_data init; + struct clk *clk; + struct clk_parent_data parent_data[2]; + char name[64]; + + memset(&init, 0, sizeof(init)); + memset(&parent_data, 0, sizeof(parent_data)); + + init.parent_data = parent_data; + + /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */ + + pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL); + if (!pow2_fixed_div) + return -ENOMEM; + + snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev)); + init.name = name; + init.ops = &clk_fixed_factor_ops; + init.flags = 0; + parent_data[0].hw = __clk_get_hw(spicc->core); + init.num_parents = 1; + + pow2_fixed_div->mult = 1, + pow2_fixed_div->div = 4, + pow2_fixed_div->hw.init = &init; + + clk = devm_clk_register(dev, &pow2_fixed_div->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); + + pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL); + if (!pow2_div) + return -ENOMEM; + + snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev)); + init.name = name; + init.ops = &clk_divider_ops; + init.flags = CLK_SET_RATE_PARENT; + parent_data[0].hw = &pow2_fixed_div->hw; + init.num_parents = 1; + + pow2_div->shift = 16, + pow2_div->width = 3, + pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO, + pow2_div->reg = spicc->base + SPICC_CONREG; + pow2_div->hw.init = &init; + + clk = devm_clk_register(dev, &pow2_div->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); + + if (!spicc->data->has_enhance_clk_div) { + spicc->clk = clk; + return 0; + } + + /* algorithm for enh div: rate = freq / 2 / (N + 1) */ + + enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL); + if (!enh_fixed_div) + return -ENOMEM; + + snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev)); + init.name = name; + init.ops = &clk_fixed_factor_ops; + init.flags = 0; + parent_data[0].hw = __clk_get_hw(spicc->core); + init.num_parents = 1; + + enh_fixed_div->mult = 1, + enh_fixed_div->div = 2, + enh_fixed_div->hw.init = &init; + + clk = devm_clk_register(dev, &enh_fixed_div->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); + + enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL); + if (!enh_div) + return -ENOMEM; + + snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev)); + init.name = name; + init.ops = &clk_divider_ops; + init.flags = CLK_SET_RATE_PARENT; + parent_data[0].hw = &enh_fixed_div->hw; + init.num_parents = 1; + + enh_div->shift = 16, + enh_div->width = 8, + enh_div->reg = spicc->base + SPICC_ENH_CTL0; + enh_div->hw.init = &init; + + clk = devm_clk_register(dev, &enh_div->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + snprintf(name, sizeof(name), "%s#sel", dev_name(dev)); + init.name = name; + init.ops = &clk_mux_ops; + parent_data[0].hw = &pow2_div->hw; + parent_data[1].hw = &enh_div->hw; + init.num_parents = 2; + init.flags = CLK_SET_RATE_PARENT; + + mux->mask = 0x1, + mux->shift = 24, + mux->reg = spicc->base + SPICC_ENH_CTL0; + mux->hw.init = &init; + + spicc->clk = devm_clk_register(dev, &mux->hw); + if (WARN_ON(IS_ERR(spicc->clk))) + return PTR_ERR(spicc->clk); + + return 0; +} + static int meson_spicc_probe(struct platform_device *pdev) { struct spi_master *master; @@ -533,6 +646,10 @@ static int meson_spicc_probe(struct platform_device *pdev) goto out_master; } + /* Set master mode and enable controller */ + writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER, + spicc->base + SPICC_CONREG); + /* Disable all IRQs */ writel_relaxed(0, spicc->base + SPICC_INTREG); @@ -584,6 +701,12 @@ static int meson_spicc_probe(struct platform_device *pdev) meson_spicc_oen_enable(spicc); + ret = meson_spicc_clk_init(spicc); + if (ret) { + dev_err(&pdev->dev, "clock registration failed\n"); + goto out_master; + } + ret = devm_spi_register_master(&pdev->dev, master); if (ret) { dev_err(&pdev->dev, "spi master registration failed\n"); @@ -618,6 +741,7 @@ static const struct meson_spicc_data meson_spicc_gx_data = { static const struct meson_spicc_data meson_spicc_axg_data = { .has_oen = true, + .has_enhance_clk_div = true, }; static const struct of_device_id meson_spicc_of_match[] = { From patchwork Thu Mar 12 13:31:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11434233 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 354366CA for ; Thu, 12 Mar 2020 13:31:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 13738206EB for ; Thu, 12 Mar 2020 13:31:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="YulRMKVU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727434AbgCLNbk (ORCPT ); Thu, 12 Mar 2020 09:31:40 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:54093 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727407AbgCLNbk (ORCPT ); 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id m21sm12242885wmi.27.2020.03.12.06.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 06:31:37 -0700 (PDT) From: Neil Armstrong To: broonie@kernel.org Cc: Neil Armstrong , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sunny Luo , Yixun Lan Subject: [PATCH 4/9] spi: meson-spicc: support max 80MHz clock Date: Thu, 12 Mar 2020 14:31:26 +0100 Message-Id: <20200312133131.26430-5-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200312133131.26430-1-narmstrong@baylibre.com> References: <20200312133131.26430-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The SPICC controller in Meson-AXG is capable of running at 80M clock. The ASIC IP is improved and the clock is actually running higher than previous old SoCs. Signed-off-by: Sunny Luo Signed-off-by: Yixun Lan Signed-off-by: Neil Armstrong --- drivers/spi/spi-meson-spicc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index bd434d9055d9..710b4e780daa 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -35,7 +35,6 @@ * to have a CS go down over the full transfer */ -#define SPICC_MAX_FREQ 30000000 #define SPICC_MAX_BURST 128 /* Register Map */ @@ -132,6 +131,7 @@ #define SPICC_FIFO_HALF 10 struct meson_spicc_data { + unsigned int max_speed_hz; bool has_oen; bool has_enhance_clk_div; }; @@ -693,11 +693,9 @@ static int meson_spicc_probe(struct platform_device *pdev) master->transfer_one = meson_spicc_transfer_one; master->use_gpio_descriptors = true; - /* Setup max rate according to the Meson GX datasheet */ - if ((rate >> 2) > SPICC_MAX_FREQ) - master->max_speed_hz = SPICC_MAX_FREQ; - else - master->max_speed_hz = rate >> 2; + /* Setup max rate according to the Meson datasheet */ + master->max_speed_hz = min_t(unsigned int, rate >> 1, + spicc->data->max_speed_hz); meson_spicc_oen_enable(spicc); @@ -737,9 +735,11 @@ static int meson_spicc_remove(struct platform_device *pdev) } static const struct meson_spicc_data meson_spicc_gx_data = { + .max_speed_hz = 30000000, }; static const struct meson_spicc_data meson_spicc_axg_data = { + .max_speed_hz = 80000000, .has_oen = true, .has_enhance_clk_div = true, }; From patchwork Thu Mar 12 13:31:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11434235 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2440792C for ; Thu, 12 Mar 2020 13:31:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0108F2072F for ; Thu, 12 Mar 2020 13:31:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="hUCDqIj0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727384AbgCLNbl (ORCPT ); Thu, 12 Mar 2020 09:31:41 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:36667 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727421AbgCLNbl (ORCPT ); Thu, 12 Mar 2020 09:31:41 -0400 Received: by mail-wr1-f65.google.com with SMTP id s5so7513670wrg.3 for ; Thu, 12 Mar 2020 06:31:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qPH/Dy/CjLCenRWLG2Luxl8lE2WdXQS9qh3kQnsN4TQ=; b=hUCDqIj0/ip1fGR0w8g9JiTgR3VggFXz6uXZBIuxQFF8RI6pPBFb0oKUQZqohHTRzJ EHaOdl7mpyqXAh2wOch+xrBgXcNlimpN9pUcYfJPjcxIWvdkyqbSg9NQI7L5ScEkAZB4 rMQWh59snVY+t+sBELnc4M5c4DmKQy+T/hQ5cw5ip7/2BS8wARxIRgItz7sfFyakw9vk mlBrjYp4ALqFRuMLjLg7MJ0VyZcGPi4hjaD+7P3BdyiA5CPOMY/d5Ix0Gesh38EQ24E6 X5/Ga0uTigrBvfoDF9cVkNYXejKr5vaVSAdDmf2Fc1HVBFXkq/IRQFrjALiYCP+VQjwE a/qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qPH/Dy/CjLCenRWLG2Luxl8lE2WdXQS9qh3kQnsN4TQ=; b=FW0z0pCs/Xjl1HU8pFUCakMMDrXvfjF1gBgXq3iTxPE5u3ILdfh6a1GfJhZ+CM01IG gWibYvUAYAHx6JdtKb0QMoQG9FbQRj1RZ8AmW62xv1j1Ix1C53MXfdyCuUnhJ3KRo1GL Ff9VpKsE3+vEcA+VTQzo1bixfa+2KQpyfpra/3yRevGCGrxRGhOoMBUGpvmkHZOzrEsy hCwsCScalI4LY4INvYOz9/5lbkNCD1flVmou3rmvfbRPrbwXu2lNtY4tuI2K6D7GwK+f qSxj+qx5uWZNN0Nkz2A6a1NoPC58+lSQRucX+ElEJet986wp6f30R8ZlgKZrNRNqpmt7 sQTA== X-Gm-Message-State: ANhLgQ3KcmpHSznhaMD1ikMe+ojQdS++FVl39FCGIQTCV3AkR9U05dtY RFvX8P+wplPyKnxDvNxc/EAYQg== X-Google-Smtp-Source: ADFU+vvDGHCmjJAEW09IY2pn/rC0cuKnx5wPrdhmLydsBiF7dyxe06aMf+3l/75LbVxspehBFH2Fng== X-Received: by 2002:adf:e911:: with SMTP id f17mr10602906wrm.87.1584019899241; Thu, 12 Mar 2020 06:31:39 -0700 (PDT) Received: from bender.baylibre.local (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id m21sm12242885wmi.27.2020.03.12.06.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 06:31:38 -0700 (PDT) From: Neil Armstrong To: broonie@kernel.org Cc: Neil Armstrong , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/9] spi: meson-spicc: add min sclk for each compatible Date: Thu, 12 Mar 2020 14:31:27 +0100 Message-Id: <20200312133131.26430-6-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200312133131.26430-1-narmstrong@baylibre.com> References: <20200312133131.26430-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The G12A SPICC controller variant takes the source clock from a specific clock instead of the bus clock. The minimal clock calculus won't work with the G12A support, thus add the minimal supported clock for each variant and pass this to the SPI core. Signed-off-by: Neil Armstrong --- drivers/spi/spi-meson-spicc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 710b4e780daa..b5bd3a897e8f 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -132,6 +132,7 @@ struct meson_spicc_data { unsigned int max_speed_hz; + unsigned int min_speed_hz; bool has_oen; bool has_enhance_clk_div; }; @@ -685,7 +686,7 @@ static int meson_spicc_probe(struct platform_device *pdev) SPI_BPW_MASK(16) | SPI_BPW_MASK(8); master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); - master->min_speed_hz = rate >> 9; + master->min_speed_hz = spicc->data->min_speed_hz; master->setup = meson_spicc_setup; master->cleanup = meson_spicc_cleanup; master->prepare_message = meson_spicc_prepare_message; @@ -736,10 +737,12 @@ static int meson_spicc_remove(struct platform_device *pdev) static const struct meson_spicc_data meson_spicc_gx_data = { .max_speed_hz = 30000000, + .min_speed_hz = 325000, }; static const struct meson_spicc_data meson_spicc_axg_data = { .max_speed_hz = 80000000, + .min_speed_hz = 325000, .has_oen = true, .has_enhance_clk_div = true, }; From patchwork Thu Mar 12 13:31:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11434247 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A529C92C for ; Thu, 12 Mar 2020 13:32:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7ACC22074B for ; Thu, 12 Mar 2020 13:32:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="crid5weI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727446AbgCLNbn (ORCPT ); Thu, 12 Mar 2020 09:31:43 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:54423 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727435AbgCLNbm (ORCPT ); Thu, 12 Mar 2020 09:31:42 -0400 Received: by mail-wm1-f68.google.com with SMTP id n8so6102550wmc.4 for ; Thu, 12 Mar 2020 06:31:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xtd57ANFwEVXtL9Ksemj5kAkfq1D3BufSA8HrwoNyGM=; b=crid5weIqLsxtB221E29RJHYKJ4O8HbVMdLMr8N6vDiqh1vo6BPFf2nP8ki8C+Hj8F +Eomn9sIwNriAp2P+lvdLmD3bLHQD41BfoRK0DA+NDGzpeqsduE/C8bCF7ddw/du1GCo Bk8QhkCflUQipTosllgUBmooWikSHyWLX41R+o7Y549gWUexa0zGki1FxTzDCyKwB3uX y7oGBx5v2Wj0zm9UF8t6TJ+FIFqG3+lrwSCDLTgST+UV7KPrFhT5JP3zGvgDqWIVdYFL ypuMa+rtMVyG3c+zwI1/YAeJckKDrQpo4SbcYzOoGd4hZELK5JKBcyBH/eGX9YrL5BLP ayfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xtd57ANFwEVXtL9Ksemj5kAkfq1D3BufSA8HrwoNyGM=; b=sKVTPkVfJy2rPXptSTrGdW6vmC4V42HTPvxE+9pxyu32LeQDlOTJqfLfPyzDlPXiAw R7tSZov3IPyGNk/0ybGB6MAumDF25lT+0kAJZZEBL2f22uiOWdWQWagcA5AwuUStx4IE BUGJRKprVmTNKwAEfIg/n4S1i/R78DZO7hcP70aJ7Zb8px7PWqETamT4mZX71M5CzLg7 KRzBGXXBtuXlJPi9OQgoNeMW4jOwYS5s+3zKstfVFTr1OoxEVfftKjHlfgwZwv93zAt6 bNn0B0CwON8RV6kFuu2OtZFGfjEKvIIaFeIPz62EB/WmZsRV+sTi0fdnKFOTMXJxvfNC wKRQ== X-Gm-Message-State: ANhLgQ0iGAkdNwNn81HRkvYRiw7C4L72xhVj9Yy16R/x5YBPj5fMI+Go sOMiE1sEViDzVui2dY4RFKn29g== X-Google-Smtp-Source: ADFU+vv/Bf0cjqi786SLwyoflMdPEUVQYzJUoEEq10USnSQe6YhOpU8nPOsloJnqi5KX9B8MoPtHgg== X-Received: by 2002:a1c:4805:: with SMTP id v5mr4776912wma.98.1584019900193; Thu, 12 Mar 2020 06:31:40 -0700 (PDT) Received: from bender.baylibre.local (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id m21sm12242885wmi.27.2020.03.12.06.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 06:31:39 -0700 (PDT) From: Neil Armstrong To: broonie@kernel.org Cc: Neil Armstrong , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/9] spi: meson-spicc: setup IO line delay Date: Thu, 12 Mar 2020 14:31:28 +0100 Message-Id: <20200312133131.26430-7-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200312133131.26430-1-narmstrong@baylibre.com> References: <20200312133131.26430-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Now the controller can support frequencies higher than 30MHz, we need the setup the I/O line delays in regard of the SPI clock frequency. Signed-off-by: Neil Armstrong --- drivers/spi/spi-meson-spicc.c | 61 ++++++++++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index b5bd3a897e8f..4494a791f4a7 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -106,7 +106,21 @@ #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */ #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */ #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */ -#define SPICC_DLYCTL_W1_MASK GENMASK(21, 16) /* Delay Control Write-Only */ +#define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */ +#define SPICC_MO_NO_DELAY 0 +#define SPICC_MO_DELAY_1_CYCLE 1 +#define SPICC_MO_DELAY_2_CYCLE 2 +#define SPICC_MO_DELAY_3_CYCLE 3 +#define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */ +#define SPICC_MI_NO_DELAY 0 +#define SPICC_MI_DELAY_1_CYCLE 1 +#define SPICC_MI_DELAY_2_CYCLE 2 +#define SPICC_MI_DELAY_3_CYCLE 3 +#define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */ +#define SPICC_CAP_AHEAD_2_CYCLE 0 +#define SPICC_CAP_AHEAD_1_CYCLE 1 +#define SPICC_CAP_NO_DELAY 2 +#define SPICC_CAP_DELAY_1_CYCLE 3 #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */ #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */ @@ -328,6 +342,49 @@ static irqreturn_t meson_spicc_irq(int irq, void *data) return IRQ_HANDLED; } +static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc) +{ + u32 div, hz; + u32 mi_delay, cap_delay; + u32 conf; + + if (spicc->data->has_enhance_clk_div) { + div = FIELD_GET(SPICC_ENH_DATARATE_MASK, + readl_relaxed(spicc->base + SPICC_ENH_CTL0)); + div++; + div <<= 1; + } else { + div = FIELD_GET(SPICC_DATARATE_MASK, + readl_relaxed(spicc->base + SPICC_CONREG)); + div += 2; + div = 1 << div; + } + + mi_delay = SPICC_MI_NO_DELAY; + cap_delay = SPICC_CAP_AHEAD_2_CYCLE; + hz = clk_get_rate(spicc->clk); + + if (hz >= 100000000) + cap_delay = SPICC_CAP_DELAY_1_CYCLE; + else if (hz >= 80000000) + cap_delay = SPICC_CAP_NO_DELAY; + else if (hz >= 40000000) + cap_delay = SPICC_CAP_AHEAD_1_CYCLE; + else if (div >= 16) + mi_delay = SPICC_MI_DELAY_3_CYCLE; + else if (div >= 8) + mi_delay = SPICC_MI_DELAY_2_CYCLE; + else if (div >= 6) + mi_delay = SPICC_MI_DELAY_1_CYCLE; + + conf = readl_relaxed(spicc->base + SPICC_TESTREG); + conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK + | SPICC_MI_CAP_DELAY_MASK); + conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay); + conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay); + writel_relaxed(conf, spicc->base + SPICC_TESTREG); +} + static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, struct spi_transfer *xfer) { @@ -346,6 +403,8 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, writel_relaxed(conf, spicc->base + SPICC_CONREG); clk_set_rate(spicc->clk, xfer->speed_hz); + + meson_spicc_auto_io_delay(spicc); } static int meson_spicc_transfer_one(struct spi_master *master, From patchwork Thu Mar 12 13:31:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11434245 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C2D56139A for ; Thu, 12 Mar 2020 13:32:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 982B12074C for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id m21sm12242885wmi.27.2020.03.12.06.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 06:31:40 -0700 (PDT) From: Neil Armstrong To: broonie@kernel.org Cc: Neil Armstrong , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/9] spi: meson-spicc: adapt burst handling for G12A support Date: Thu, 12 Mar 2020 14:31:29 +0100 Message-Id: <20200312133131.26430-8-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200312133131.26430-1-narmstrong@baylibre.com> References: <20200312133131.26430-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The G12A SPICC controller variant has a different FIFO size and doesn't handle the RX Half interrupt the same way as GXL & AXG variants. Thus simplify the burst management and take in account a variable FIFO size. Signed-off-by: Neil Armstrong --- drivers/spi/spi-meson-spicc.c | 129 +++++++++++++--------------------- 1 file changed, 50 insertions(+), 79 deletions(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 4494a791f4a7..351ccd8dd2c2 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -141,12 +141,10 @@ #define writel_bits_relaxed(mask, val, addr) \ writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) -#define SPICC_BURST_MAX 16 -#define SPICC_FIFO_HALF 10 - struct meson_spicc_data { unsigned int max_speed_hz; unsigned int min_speed_hz; + unsigned int fifo_size; bool has_oen; bool has_enhance_clk_div; }; @@ -166,8 +164,6 @@ struct meson_spicc_device { unsigned long tx_remain; unsigned long rx_remain; unsigned long xfer_remain; - bool is_burst_end; - bool is_last_burst; }; static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) @@ -191,7 +187,7 @@ static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc) static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc) { - return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF_EN, + return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF, readl_relaxed(spicc->base + SPICC_STATREG)); } @@ -246,34 +242,22 @@ static inline void meson_spicc_tx(struct meson_spicc_device *spicc) spicc->base + SPICC_TXDATA); } -static inline u32 meson_spicc_setup_rx_irq(struct meson_spicc_device *spicc, - u32 irq_ctrl) +static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc) { - if (spicc->rx_remain > SPICC_FIFO_HALF) - irq_ctrl |= SPICC_RH_EN; - else - irq_ctrl |= SPICC_RR_EN; - - return irq_ctrl; -} -static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc, - unsigned int burst_len) -{ + unsigned int burst_len = min_t(unsigned int, + spicc->xfer_remain / + spicc->bytes_per_word, + spicc->data->fifo_size); /* Setup Xfer variables */ spicc->tx_remain = burst_len; spicc->rx_remain = burst_len; spicc->xfer_remain -= burst_len * spicc->bytes_per_word; - spicc->is_burst_end = false; - if (burst_len < SPICC_BURST_MAX || !spicc->xfer_remain) - spicc->is_last_burst = true; - else - spicc->is_last_burst = false; /* Setup burst length */ writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, FIELD_PREP(SPICC_BURSTLENGTH_MASK, - burst_len), + burst_len - 1), spicc->base + SPICC_CONREG); /* Fill TX FIFO */ @@ -283,61 +267,26 @@ static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc, static irqreturn_t meson_spicc_irq(int irq, void *data) { struct meson_spicc_device *spicc = (void *) data; - u32 ctrl = readl_relaxed(spicc->base + SPICC_INTREG); - u32 stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl; - ctrl &= ~(SPICC_RH_EN | SPICC_RR_EN); + writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); /* Empty RX FIFO */ meson_spicc_rx(spicc); - /* Enable TC interrupt since we transferred everything */ - if (!spicc->tx_remain && !spicc->rx_remain) { - spicc->is_burst_end = true; - - /* Enable TC interrupt */ - ctrl |= SPICC_TC_EN; - - /* Reload IRQ status */ - stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl; - } - - /* Check transfer complete */ - if ((stat & SPICC_TC) && spicc->is_burst_end) { - unsigned int burst_len; - - /* Clear TC bit */ - writel_relaxed(SPICC_TC, spicc->base + SPICC_STATREG); - - /* Disable TC interrupt */ - ctrl &= ~SPICC_TC_EN; - - if (spicc->is_last_burst) { - /* Disable all IRQs */ - writel(0, spicc->base + SPICC_INTREG); - - spi_finalize_current_transfer(spicc->master); + if (!spicc->xfer_remain) { + /* Disable all IRQs */ + writel(0, spicc->base + SPICC_INTREG); - return IRQ_HANDLED; - } + spi_finalize_current_transfer(spicc->master); - burst_len = min_t(unsigned int, - spicc->xfer_remain / spicc->bytes_per_word, - SPICC_BURST_MAX); - - /* Setup burst */ - meson_spicc_setup_burst(spicc, burst_len); - - /* Restart burst */ - writel_bits_relaxed(SPICC_XCH, SPICC_XCH, - spicc->base + SPICC_CONREG); + return IRQ_HANDLED; } - /* Setup RX interrupt trigger */ - ctrl = meson_spicc_setup_rx_irq(spicc, ctrl); + /* Setup burst */ + meson_spicc_setup_burst(spicc); - /* Reconfigure interrupts */ - writel(ctrl, spicc->base + SPICC_INTREG); + /* Start burst */ + writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); return IRQ_HANDLED; } @@ -405,6 +354,28 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, clk_set_rate(spicc->clk, xfer->speed_hz); meson_spicc_auto_io_delay(spicc); + + writel_relaxed(0, spicc->base + SPICC_DMAREG); +} + +static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc) +{ + u32 data; + + if (spicc->data->has_oen) + writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, + SPICC_ENH_MAIN_CLK_AO, + spicc->base + SPICC_ENH_CTL0); + + writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK, + spicc->base + SPICC_TESTREG); + + while (meson_spicc_rxready(spicc)) + data = readl_relaxed(spicc->base + SPICC_RXDATA); + + if (spicc->data->has_oen) + writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0, + spicc->base + SPICC_ENH_CTL0); } static int meson_spicc_transfer_one(struct spi_master *master, @@ -412,8 +383,6 @@ static int meson_spicc_transfer_one(struct spi_master *master, struct spi_transfer *xfer) { struct meson_spicc_device *spicc = spi_master_get_devdata(master); - unsigned int burst_len; - u32 irq = 0; /* Store current transfer */ spicc->xfer = xfer; @@ -427,22 +396,22 @@ static int meson_spicc_transfer_one(struct spi_master *master, spicc->bytes_per_word = DIV_ROUND_UP(spicc->xfer->bits_per_word, 8); + if (xfer->len % spicc->bytes_per_word) + return -EINVAL; + /* Setup transfer parameters */ meson_spicc_setup_xfer(spicc, xfer); - burst_len = min_t(unsigned int, - spicc->xfer_remain / spicc->bytes_per_word, - SPICC_BURST_MAX); - - meson_spicc_setup_burst(spicc, burst_len); + meson_spicc_reset_fifo(spicc); - irq = meson_spicc_setup_rx_irq(spicc, irq); + /* Setup burst */ + meson_spicc_setup_burst(spicc); /* Start burst */ writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); /* Enable interrupts */ - writel_relaxed(irq, spicc->base + SPICC_INTREG); + writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG); return 1; } @@ -499,7 +468,7 @@ static int meson_spicc_prepare_message(struct spi_master *master, /* Setup no wait cycles by default */ writel_relaxed(0, spicc->base + SPICC_PERIODREG); - writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG); + writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG); return 0; } @@ -797,11 +766,13 @@ static int meson_spicc_remove(struct platform_device *pdev) static const struct meson_spicc_data meson_spicc_gx_data = { .max_speed_hz = 30000000, .min_speed_hz = 325000, + .fifo_size = 16, }; static const struct meson_spicc_data meson_spicc_axg_data = { .max_speed_hz = 80000000, .min_speed_hz = 325000, + .fifo_size = 16, .has_oen = true, .has_enhance_clk_div = true, }; From patchwork Thu Mar 12 13:31:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11434239 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 39F396CA for ; Thu, 12 Mar 2020 13:32:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 12DC6206E7 for ; Thu, 12 Mar 2020 13:32:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="L58sEGr8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727466AbgCLNbq (ORCPT ); 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id m21sm12242885wmi.27.2020.03.12.06.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 06:31:41 -0700 (PDT) From: Neil Armstrong To: broonie@kernel.org, devicetree@vger.kernel.org Cc: Neil Armstrong , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/9] dt-bindings: spi: amlogic,meson-gx-spicc: add Amlogic G12A compatible Date: Thu, 12 Mar 2020 14:31:30 +0100 Message-Id: <20200312133131.26430-9-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200312133131.26430-1-narmstrong@baylibre.com> References: <20200312133131.26430-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The Amlogic G12A SPICC controllers uses a secondary clock used to feed the baud rate generator and the delay control logic. Signed-off-by: Neil Armstrong --- .../bindings/spi/amlogic,meson-gx-spicc.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml index 49b617c98ae7..9147df29022a 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml @@ -22,6 +22,7 @@ properties: enum: - amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and compatible SoCs - amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and compatible SoCs + - amlogic,meson-g12a-spicc # SPICC controller on Amlogic G12A and compatible SoCs interrupts: maxItems: 1 @@ -40,6 +41,27 @@ properties: items: - const: core +if: + properties: + compatible: + contains: + enum: + - amlogic,meson-g12a-spicc + +then: + properties: + clocks: + contains: + items: + - description: controller register bus clock + - description: baud rate generator and delay control clock + + clock-names: + minItems: 2 + items: + - const: core + - const: pclk + required: - compatible - reg From patchwork Thu Mar 12 13:31:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11434241 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7629114B4 for ; Thu, 12 Mar 2020 13:32:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 47D9B206E7 for ; Thu, 12 Mar 2020 13:32:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="v6+dB29X" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727123AbgCLNb7 (ORCPT ); Thu, 12 Mar 2020 09:31:59 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:45683 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727462AbgCLNbq (ORCPT ); Thu, 12 Mar 2020 09:31:46 -0400 Received: by mail-wr1-f66.google.com with SMTP id m9so7450581wro.12 for ; Thu, 12 Mar 2020 06:31:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ysgTmW9ZLhpEDIjfoCrSPsioEcbHMMnVx5neQlx80G8=; b=v6+dB29Xyenrhk4NaFR7iQNJZSWzKs/Zq9VWJ4o/maiRmzn1FJJiRssz44fuqooP6z 191ZSbVzN+ZfzSIMcwPPQ5izObfW1BF7Qk1QO8Gdpqyu7uiVRpID+pfhATIeu61fRmGX kJmfYt3XZagBYOUJGUxz0aiM80wIeM1ZYD9BbZT9fLoxsvQznfd9IKVaBUsszl/CQjnA WuRnGkJyY5H8Uz9p/gWzt0TDCrpVcEwZO7IbCEpc97w+PuG4jmHk8im0QEqo9Ear0Ipo 2LQYb9VSrQqme4gk+K3GF1vbgfQsT9Y5pb7YOCsSw/Bb09uhhP4njCzkH0K6vC5R/JMv 9ilQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ysgTmW9ZLhpEDIjfoCrSPsioEcbHMMnVx5neQlx80G8=; b=SnwlWPay/w9b6vPaU3tA4WX1i+u5LUzvq3TuJcMfiMAAMH1CP5CJdaBC89cfM/ehQX XRlrKAT1+EqfUY+JVZ4z4qzLz1Ut6ID0hMdQYwVr1H0J7w7mp3KUMP4DGLfKZp+aWvWV Vt1rMM+goMqtXl+p6rLlO6ATtIKrBFWnhSsDab873bohAj/O5YeAnjApbczXtXhA1pjR 0obZAQBHNJn36QStXmSTn8Zf+hPy+p7he9QgYXI1CwsIEdcfRe6bgd28WaRPHohTIgHp d5LfVCWSf003QIbQoDaFU16wEvNaPh0INpFrajQI5PkI7dgf317cMfwUtQeMRb9ykrPn mOMQ== X-Gm-Message-State: ANhLgQ2CapriEwcfgYzpuG80TiftXiY/GLzJFXylKalZPAzultYgxxem dwPPqScaE25ixionERgvUaZf8A== X-Google-Smtp-Source: ADFU+vurnjaYzt7zIZenRaisc19C05PAgySImkcj7ODdYzNCIV8i6gly0uLMljAD0nLyCFdeF3tr6Q== X-Received: by 2002:adf:94c2:: with SMTP id 60mr11120426wrr.396.1584019903410; Thu, 12 Mar 2020 06:31:43 -0700 (PDT) Received: from bender.baylibre.local (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id m21sm12242885wmi.27.2020.03.12.06.31.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 06:31:42 -0700 (PDT) From: Neil Armstrong To: broonie@kernel.org Cc: Neil Armstrong , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 9/9] spi: meson-spicc: add support for Amlogic G12A Date: Thu, 12 Mar 2020 14:31:31 +0100 Message-Id: <20200312133131.26430-10-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200312133131.26430-1-narmstrong@baylibre.com> References: <20200312133131.26430-1-narmstrong@baylibre.com> MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add support for the SPICC controllers on the Amlogic G12A SoCs family. The G12A SPICC controllers inherit from the AXG enhanced registers but takes an external pclk for the baud rate generator and can achieve up to 166MHz SCLK. Signed-off-by: Neil Armstrong --- drivers/spi/spi-meson-spicc.c | 54 +++++++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 351ccd8dd2c2..77f7d0e0e46a 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -147,6 +147,7 @@ struct meson_spicc_data { unsigned int fifo_size; bool has_oen; bool has_enhance_clk_div; + bool has_pclk; }; struct meson_spicc_device { @@ -154,6 +155,7 @@ struct meson_spicc_device { struct platform_device *pdev; void __iomem *base; struct clk *core; + struct clk *pclk; struct clk *clk; struct spi_message *message; struct spi_transfer *xfer; @@ -514,6 +516,10 @@ static void meson_spicc_cleanup(struct spi_device *spi) * Clk path for AXG series: * src -> pow2 fixed div -> pow2 div -> mux -> out * src -> enh fixed div -> enh div -> mux -> out + * + * Clk path for G12A series: + * pclk -> pow2 fixed div -> pow2 div -> mux -> out + * pclk -> enh fixed div -> enh div -> mux -> out */ static int meson_spicc_clk_init(struct meson_spicc_device *spicc) @@ -542,7 +548,10 @@ static int meson_spicc_clk_init(struct meson_spicc_device *spicc) init.name = name; init.ops = &clk_fixed_factor_ops; init.flags = 0; - parent_data[0].hw = __clk_get_hw(spicc->core); + if (spicc->data->has_pclk) + parent_data[0].hw = __clk_get_hw(spicc->pclk); + else + parent_data[0].hw = __clk_get_hw(spicc->core); init.num_parents = 1; pow2_fixed_div->mult = 1, @@ -589,7 +598,10 @@ static int meson_spicc_clk_init(struct meson_spicc_device *spicc) init.name = name; init.ops = &clk_fixed_factor_ops; init.flags = 0; - parent_data[0].hw = __clk_get_hw(spicc->core); + if (spicc->data->has_pclk) + parent_data[0].hw = __clk_get_hw(spicc->pclk); + else + parent_data[0].hw = __clk_get_hw(spicc->core); init.num_parents = 1; enh_fixed_div->mult = 1, @@ -648,7 +660,7 @@ static int meson_spicc_probe(struct platform_device *pdev) { struct spi_master *master; struct meson_spicc_device *spicc; - int ret, irq, rate; + int ret, irq; master = spi_alloc_master(&pdev->dev, sizeof(*spicc)); if (!master) { @@ -697,12 +709,26 @@ static int meson_spicc_probe(struct platform_device *pdev) goto out_master; } + if (spicc->data->has_pclk) { + spicc->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(spicc->pclk)) { + dev_err(&pdev->dev, "pclk clock request failed\n"); + ret = PTR_ERR(spicc->pclk); + goto out_master; + } + } + ret = clk_prepare_enable(spicc->core); if (ret) { dev_err(&pdev->dev, "core clock enable failed\n"); goto out_master; } - rate = clk_get_rate(spicc->core); + + ret = clk_prepare_enable(spicc->pclk); + if (ret) { + dev_err(&pdev->dev, "pclk clock enable failed\n"); + goto out_master; + } device_reset_optional(&pdev->dev); @@ -715,6 +741,7 @@ static int meson_spicc_probe(struct platform_device *pdev) SPI_BPW_MASK(8); master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); master->min_speed_hz = spicc->data->min_speed_hz; + master->max_speed_hz = spicc->data->max_speed_hz; master->setup = meson_spicc_setup; master->cleanup = meson_spicc_cleanup; master->prepare_message = meson_spicc_prepare_message; @@ -722,10 +749,6 @@ static int meson_spicc_probe(struct platform_device *pdev) master->transfer_one = meson_spicc_transfer_one; master->use_gpio_descriptors = true; - /* Setup max rate according to the Meson datasheet */ - master->max_speed_hz = min_t(unsigned int, rate >> 1, - spicc->data->max_speed_hz); - meson_spicc_oen_enable(spicc); ret = meson_spicc_clk_init(spicc); @@ -744,6 +767,7 @@ static int meson_spicc_probe(struct platform_device *pdev) out_clk: clk_disable_unprepare(spicc->core); + clk_disable_unprepare(spicc->pclk); out_master: spi_master_put(master); @@ -759,6 +783,7 @@ static int meson_spicc_remove(struct platform_device *pdev) writel(0, spicc->base + SPICC_CONREG); clk_disable_unprepare(spicc->core); + clk_disable_unprepare(spicc->pclk); return 0; } @@ -777,6 +802,15 @@ static const struct meson_spicc_data meson_spicc_axg_data = { .has_enhance_clk_div = true, }; +static const struct meson_spicc_data meson_spicc_g12a_data = { + .max_speed_hz = 166666666, + .min_speed_hz = 50000, + .fifo_size = 15, + .has_oen = true, + .has_enhance_clk_div = true, + .has_pclk = true, +}; + static const struct of_device_id meson_spicc_of_match[] = { { .compatible = "amlogic,meson-gx-spicc", @@ -786,6 +820,10 @@ static const struct of_device_id meson_spicc_of_match[] = { .compatible = "amlogic,meson-axg-spicc", .data = &meson_spicc_axg_data, }, + { + .compatible = "amlogic,meson-g12a-spicc", + .data = &meson_spicc_g12a_data, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, meson_spicc_of_match);