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[79.50.50.61]) by smtp.googlemail.com with ESMTPSA id 94sm2552140eda.7.2020.03.13.12.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2020 12:15:21 -0700 (PDT) From: Ansuel Smith To: agross@kernel.org Cc: Ansuel Smith , Ajay Kishore , Bjorn Andersson , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] pinctrl: qcom: use scm_call to route GPIO irq to Apps Date: Fri, 13 Mar 2020 20:15:13 +0100 Message-Id: <20200313191513.11365-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.0 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org For IPQ806x targets, TZ protects the registers that are used to configure the routing of interrupts to a target processor. To resolve this, this patch uses scm call to route GPIO interrupts to application processor. Also the scm call interface is changed. Signed-off-by: Ajay Kishore Signed-off-by: Ansuel Smith --- drivers/pinctrl/qcom/pinctrl-msm.c | 36 ++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 9a8daa256a32..a83cfd1da219 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include @@ -710,6 +712,9 @@ static void msm_gpio_irq_mask(struct irq_data *d) const struct msm_pingroup *g; unsigned long flags; u32 val; + u32 addr; + int ret; + const __be32 *reg; if (d->parent_data) irq_chip_mask_parent(d); @@ -863,6 +868,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) const struct msm_pingroup *g; unsigned long flags; u32 val; + int ret; if (d->parent_data) irq_chip_set_type_parent(d, type); @@ -882,11 +888,33 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) else clear_bit(d->hwirq, pctrl->dual_edge_irqs); + ret = of_device_is_compatible(pctrl->dev->of_node, + "qcom,ipq8064-pinctrl"); /* Route interrupts to application cpu */ - val = msm_readl_intr_target(pctrl, g); - val &= ~(7 << g->intr_target_bit); - val |= g->intr_target_kpss_val << g->intr_target_bit; - msm_writel_intr_target(val, pctrl, g); + if (!ret) { + val = msm_readl_intr_target(pctrl, g); + val &= ~(7 << g->intr_target_bit); + val |= g->intr_target_kpss_val << g->intr_target_bit; + msm_writel_intr_target(val, pctrl, g); + } else { + const __be32 *reg = of_get_property(pctrl->dev->of_node, + "reg", NULL); + + if (reg) { + u32 addr = be32_to_cpup(reg) + g->intr_target_reg; + + qcom_scm_io_readl(addr, &val); + __iormb(); + + val &= ~(7 << g->intr_target_bit); + val |= g->intr_target_kpss_val << g->intr_target_bit; + + __iowmb(); + ret = qcom_scm_io_writel(addr, val); + if (ret) + pr_err("\n Routing interrupts to Apps proc failed"); + } + } /* Update configuration for gpio. * RAW_STATUS_EN is left on for all gpio irqs. Due to the