From patchwork Tue Mar 17 04:05:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 11441685 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B03592A for ; Tue, 17 Mar 2020 04:07:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1E61720658 for ; Tue, 17 Mar 2020 04:07:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="LHF/9M3V" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1E61720658 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:52186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jE3Vu-0001lY-OK for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Mar 2020 00:07:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45386) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jE3UW-00087a-J8 for qemu-devel@nongnu.org; Tue, 17 Mar 2020 00:06:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jE3UV-00029h-4t for qemu-devel@nongnu.org; Tue, 17 Mar 2020 00:06:08 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:38394) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jE3UU-0001ys-O0 for qemu-devel@nongnu.org; Tue, 17 Mar 2020 00:06:06 -0400 Received: by mail-pf1-x431.google.com with SMTP id z5so11185824pfn.5 for ; Mon, 16 Mar 2020 21:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=subject:date:message-id:mime-version:content-transfer-encoding:cc :from:to; bh=iNBqy/EyGYwQ63RRDbQPMjqB6icieu8FIzbCkicjV2c=; b=LHF/9M3V35NDN33t2dJlKN+4XJNsJBwuofv/9JOiPoQAAZgdD7tCc44RM/+Osu1Rc9 A9yOtIJRV2gqQLWWVdmkEdJVdJU/noxzE4iuTp03mRVjsmfgbO+9b0v5HSuAeHyWAdxe 8l5L4+FJUKUoQJc5LfLlvpuXQR3M4NGS0K21i1GW+UiyH/3OVMSGfADu/LuChAQYKnT8 eQnvWS6r+lp+qKfEsBrsleE2CbonzEueYlHR9xq9fUBDEyg8AOAo4Fw/x9iaOPRgC/gU VJbIxLLQ+D2kS3/fcCKsj6vMNjBbLCyQKA6LSMUU7K+ypiNvvi02G4JvA1sX6BBuNXHG FVuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:mime-version :content-transfer-encoding:cc:from:to; bh=iNBqy/EyGYwQ63RRDbQPMjqB6icieu8FIzbCkicjV2c=; b=eiC80wzkyjuxRXIEEMDcKYByrZrsrm809MENgsmVyrDCIxNrtdm2V7TLIzbawGO1Ir v7t9/Dv1x1UyAYNK0YAfkhhtGACaB51zr6nInk4dn/wr76mzbSgvWlf/N42Nl6CTJfgY jAAhT3o/3DhcdP0vFXd2iTexjt/5zrGN8AnRWYNAdXgOEFjApeNvNQYjFTktf9Gm2iAd GhDZY8YS7u4JO5qP31b488qfGo9q12hf0Ctt6ViKeRirZN8p6yh/1HRNFjrrjKORYGin VPsJxojBvfBxoKGjbqBzvMGw3XGo86LhbPfyy1yavGI3Z/vJ+TRFR7qxhf93UHaPXoEu kmvQ== X-Gm-Message-State: ANhLgQ1AMft/hMO3uDw5YdK3lIFogjKeI5wCetbLvUu0RqKmOwt4o/JH L3LaJZMyp6V9BLQbEmm+Wd9N5g== X-Google-Smtp-Source: ADFU+vu4KijjLwxveeTDD/6FM+mzdNt3hMowVffwXj0NpXu0qmYVmSpKZuJWn4gXGUoXt+B+HNV7tQ== X-Received: by 2002:a63:28c:: with SMTP id 134mr3009660pgc.165.1584417961985; Mon, 16 Mar 2020 21:06:01 -0700 (PDT) Received: from localhost (c-67-161-15-180.hsd1.ca.comcast.net. [67.161.15.180]) by smtp.gmail.com with ESMTPSA id 26sm849506pgs.85.2020.03.16.21.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 21:06:01 -0700 (PDT) Subject: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 5 Date: Mon, 16 Mar 2020 21:05:41 -0700 Message-Id: <20200317040547.222501-1-palmerdabbelt@google.com> X-Mailer: git-send-email 2.25.1.481.gfbce0eb801-goog MIME-Version: 1.0 Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::431 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit a98135f727595382e200d04c2996e868b7925a01: Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request' into staging (2020-03-16 14:55:59 +0000) are available in the Git repository at: git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf5 for you to fetch changes up to c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264: target/riscv: Fix VS mode interrupts forwarding. (2020-03-16 17:03:51 -0700) ---------------------------------------------------------------- RISC-V Patches for the 5.0 Soft Freeze, Part 5 This tag contains the last of the patches I'd like to target for the 5.0 soft freeze. At this point we're mostly collecting fixes, but there are a few new features. The changes include: * An OpenSBI update, including the various bits necessary to put CI together and an image for the 32-bit sifive_u board. * A fix that disallows TSR when outside of machine mode. * A fix for VS-mode interrupt forwarding. ---------------------------------------------------------------- Alistair Francis (1): target/riscv: Correctly implement TSR trap Bin Meng (4): roms: opensbi: Upgrade from v0.5 to v0.6 roms: opensbi: Add 32-bit firmware image for sifive_u machine riscv: sifive_u: Update BIOS_FILENAME for 32-bit gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries Rajnesh Kanwal (1): target/riscv: Fix VS mode interrupts forwarding. .gitlab-ci-opensbi.yml | 63 +++++++++++++++++++++++++++ .gitlab-ci.d/opensbi/Dockerfile | 33 ++++++++++++++ .gitlab-ci.yml | 1 + Makefile | 2 +- hw/riscv/sifive_u.c | 6 ++- pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin | Bin 0 -> 49472 bytes pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 40984 -> 41280 bytes pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 49160 -> 53760 bytes pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin 45064 -> 49664 bytes roms/Makefile | 7 +++ roms/opensbi | 2 +- target/riscv/cpu_helper.c | 9 +++- target/riscv/op_helper.c | 2 +- 13 files changed, 120 insertions(+), 5 deletions(-) create mode 100644 .gitlab-ci-opensbi.yml create mode 100644 .gitlab-ci.d/opensbi/Dockerfile create mode 100644 pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin From patchwork Tue Mar 17 04:05:43 2020 Content-Type: text/plain; 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[67.161.15.180]) by smtp.gmail.com with ESMTPSA id b10sm1232101pfo.215.2020.03.16.21.06.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 21:06:05 -0700 (PDT) Subject: [PULL 2/6] roms: opensbi: Upgrade from v0.5 to v0.6 Date: Mon, 16 Mar 2020 21:05:43 -0700 Message-Id: <20200317040547.222501-3-palmerdabbelt@google.com> X-Mailer: git-send-email 2.25.1.481.gfbce0eb801-goog In-Reply-To: <20200317040547.222501-1-palmerdabbelt@google.com> References: <20200317040547.222501-1-palmerdabbelt@google.com> MIME-Version: 1.0 Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Bin Meng , Alistair Francis , Palmer Dabbelt From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::102a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Upgrade OpenSBI from v0.5 to v0.6 and the pre-built bios images. The v0.6 release includes the following commits: dd8ef28 firmware: Fix compile error for FW_PAYLOAD with latest GCC binutils 98f4a20 firmware: Introduce relocation lottery f728a0b include: Sync-up encoding with priv v1.12-draft and hypervisor v0.5-draft 18897aa include: Use _UL() and _ULL() for defines in riscv_encoding.h 7a13beb firmware: Add preferred boot HART field in struct fw_dynamic_info 215421c lib: Remove date and time from init message 838657c include: Remove ilen member of struct unpriv_trap b1d8c98 lib: No need to set VSSTATUS.MXR bit in get_insn() 0e1322b lib: Better naming of unpriv APIs for wider use 75f903d lib: Simplify trap parameters in sbi_ecall functions c96cc03 lib: Fix CPU capabilities detection function ab14f94 lib: Fix probe extension 813f7f4 lib: Add error detection for misa_extension dc40042 include: sbi_platform: fix compilation for GCC-9 bd732ae include: Add guest external interrupt related defines 6590a7d lib: Delegate guest page faults to HS-mode 4370f18 include: Extend struct sbi_trap_info for mtval2 and mtinst 086dbdf lib: Fix sbi_get_insn() for load guest page fault 2be424b lib: Extend trap redirection for hypervisor v0.5 spec 7219477 lib: Use MTINST CSR in misaligned load/store emulation b8732fe lib: Add replacement extension and function ids aa0ed1d lib: Remove redundant IPI types 1092663 lib: Add TIME extension in SBI 9777aee lib: Add IPI extension in SBI 9407202 lib: Add hfence instruction encoding 331ff6a lib: Support stage1 and stage2 tlb flushing 86a31f5 lib: Implement RFENCE extension c7d1b12 firmware: Return real DTB address when FW_xyz_FDT_ADDR is not defined 9beb573 firmware: Improve comments for fw_prev_arg1() and fw_next_arg1() fc6bd90 docs: Improve docs for FDT address passing 46a90d9 lib: utils: Support CLINT with 32bit MMIO access on RV64 system c0849cd platform: Add T-head C910 initial support e746673 lib: Remove unnecessary checks from init_coldboot() and init_warmboot() c3e406f lib: Add initial sbi_exit() API 55e191e lib: Add system early_exit and final_exit APIs 6469ed1 lib: Add timer exit API b325f6b lib: Add ipi exit API 1993182 lib: Add irqchip exit API 2aa43a1 lib: save/restore MIE CSR in sbi_hart_wait_for_coldboot() b0c9787 lib: do sbi_exit() upon halt IPI 15ed1e7 lib: improve system reboot and shutdown implementation 73c19e6 lib: zero-out memory allocated using sbi_scratch_alloc_offset() a67fd68 lib: Add sbi_init_count() API 049ad0b build: Use -ffreestanding e340bbf include: Add OPENSBI_EXTERNAL_SBI_TYPES in sbi_types.h b28b8ac docs: Add description of using OPENSBI_EXTERNAL_SBI_TYPES adf8b73 platform: thead/c910: Remove SBI_PLATFORM_HAS_PMP f95dd39 docs: platform: Update SiFive FU540 doc as-per U-Boot v2020.01 6ffe1be firmware: Fix placement of .align directives 7daccae platform: thead/c910: Don't enable L2 cache in warm boot a73d45c platform: thead/c910: Don't set plic/clint address in warm boot 30cdf00 scripts: Add C910 to platform list in the binary archive script 0492c5d include: Typo fix in comment for SBI_SCRATCH_SIZE define 046cc16 lib: Move struct sbi_ipi_data definition to sbi_ipi.c 3d2aaac lib: Introduce sbi_ipi_send_smode() API da9b76b lib: Introduce sbi_ipi_send_halt() API a8b4b83 lib: Introduce sbi_tlb_fifo_request() API 5f762d1 lib: Introduce sbi_ipi_event_create/destroy() APIs 817d50d lib: Drop _fifo from the name of various sbi_tlb_fifo_xyz() functions 84cd4fc lib: Initialize TLB management directly from coldboot/warmboot path 0a411bf include: Add generic and simple list handling APIs 37923c4 lib: Add dynamic registration of SBI extensions 7668502 lib: Factor-out SBI legacy extension 161b348 lib: Factor-out SBI replacement extensions 43ac621 lib: Factor-out SBI vendor extension 021b9e7 lib: Factor-out SBI base extension 85647a1 platform: template: typo fix in system reboot/shutdown names ac1c229 platform: Update UART base addresses for qemu/sifve_u d79173b platform: Add an platform ops to return platform specific tlb flush limit 2c2bbe7 platform: sifive/fu540: Set tlb range flush limit to zero 5ff1ab0 makefile: add support for building on macOS 6d0b4c5 platform: Drop qemu/sifive_u support 9a717ec platform: sifive: fu540: Add platform specific 'make run' cmd d6fa7f9 doc: sifive: fu540: Update QEMU instruction when using U-Boot as the payload 179edde lib: sbi_scratch: use bitwise ops in sbi_scratch_alloc_offset() 897b8fb lib: Use __builtin_ctzl() in pmp_get() 1a8ca08 lib: Initialize out value in SBI calls c2bfa2b lib: irqchip/plic: Disable all contexts and IRQs c2f23cc platform: Add Spike initial support a062200 platform: Remove stale options from config.mk files c03c8a1 scripts: Add Spike to platform list of binary archive script 29bb2a6 docs: platform: Add documentation for Spike platform 48b06ad ThirdPartyNotices: Fix doc styles 892e879 doc: coreboot: Fix doc styles fdfb533 doc: payload_linux: Fix doc styles 44d1296 doc: andes-ae350: Fix doc styles a8ef0b5 doc: ariane-fpga: Fix doc styles 82fd42f doc: qemu_virt: Fix doc styles f8ce996 doc: sifive_fu540: Fix doc styles 27a5c7f doc: thead-c910: Fix doc styles 0b41453 Revert "lib: Use __builtin_ctzl() in pmp_get()" c66543d lib: utils: htif: Fix 32-bit build bc874e3 lib: Don't check MIDELEG and MEDELEG at end of delegate_traps() 24c3082 lib: Print interrupt and exception delegation in boot prints 66fb729 platform: sifive: fu540: Add 32-bit specific fdt/payload addresses 3e7d666 platform: qemu: virt: Correct the typo in config.mk c3b3b8f lib: Fix typo in atomic exchange functions 3936243 lib: Use available hart mask for correct hbase value f8b3bb8 lib: Simplify the for-loop in sbi_ipi_send_many() ac5e821 include: Bump-up version to 0.6 Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 40984 -> 41280 bytes pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 49160 -> 53760 bytes pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin 45064 -> 49664 bytes roms/opensbi | 2 +- 4 files changed, 1 insertion(+), 1 deletion(-) diff --git a/pc-bios/opensbi-riscv32-virt-fw_jump.bin b/pc-bios/opensbi-riscv32-virt-fw_jump.bin index 6c5b7b89f676392b687d9835ac9fbdc34f3052cd..c9654e70471764b0ee13e4d10b6f9368c6bcbf57 100644 GIT binary patch delta 19518 zcmcJ13s@7!7VvB~yGcML7$m5ukw6esMC0RXEAk2vs)!b}+K0-DueMrCZEIU^z_7uf zh&pPd)n2p;%5ANcD%N``$SYv0Qmd$~Rcb`4wGCD&f&%}UY@%q}d++~$-ygr@?9QAy zbLO0xGc)JRvb{`HRxUDV#SALSV31bEqLBewDLgS^RK$ysmX)E7=Qyzs#SLH-N-07L zsWh6OJYopscu9L(LzVW0yx6FJ@A5%=seG=9I3v*Br1 z&d6QPoHnHg;CguUa+RDs!08N7YdLDn=c+0w?pqtxc7Q%WBXwRmwMn#zww*}sT(g1u zzMLUU8L-hdmaBReao<)@FCGy1q#x!a(T)0c}Io(`n=rk1p4ZRNauTnb? ztQfdLVN~}*YE>!{8WJSpcT*`yDU?WqGbd{Vx*QIq0u5J(IZKBJkyX)}La=_42$TrgpXuu)w2$v1no0N3IgP$M1Yjz zpKV)mXL|UJ;8b~dD8Ohz7!svR7^y?UZ*w!=br*yp`Vya^{htezrpjl9-U&ZCP}diW?4?mK(M?z8!4PSly|Pn|mRb^VF&YA#o&`4nc@!{;So zIqORYn|I+6>^N!&Uc?SCeAdM4l!u`mrfQ>IRreIHr>$Ekx;lg6+**1Yt$QeA_2-nI zWO`1yrD^ebVT5g5e_VBvV#y~feYqN)MRHo}Ryd5P>SlLF!oZ#U( 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[67.161.15.180]) by smtp.gmail.com with ESMTPSA id k189sm888748pgc.24.2020.03.16.21.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 21:06:07 -0700 (PDT) Subject: [PULL 3/6] roms: opensbi: Add 32-bit firmware image for sifive_u machine Date: Mon, 16 Mar 2020 21:05:44 -0700 Message-Id: <20200317040547.222501-4-palmerdabbelt@google.com> X-Mailer: git-send-email 2.25.1.481.gfbce0eb801-goog In-Reply-To: <20200317040547.222501-1-palmerdabbelt@google.com> References: <20200317040547.222501-1-palmerdabbelt@google.com> MIME-Version: 1.0 Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Bin Meng , Alistair Francis , Palmer Dabbelt From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Although the real world SiFive HiFive Unleashed board is a 64-bit hardware configuration, with QEMU it is possible to test 32-bit configuration with the same hardware features. This updates the roms Makefile to add the build rules for creating the 32-bit OpenSBI firmware image for sifive_u machine. A pre-built OpenSBI v0.6 image has been added as the default bios for 32-bit sifive_u machine. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- Makefile | 2 +- pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin | Bin 0 -> 49472 bytes roms/Makefile | 7 +++++++ 3 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin diff --git a/Makefile b/Makefile index 7df22fcc5d..ea0e08fc57 100644 --- a/Makefile +++ b/Makefile @@ -848,7 +848,7 @@ u-boot.e500 u-boot-sam460-20100605.bin \ qemu_vga.ndrv \ edk2-licenses.txt \ hppa-firmware.img \ -opensbi-riscv32-virt-fw_jump.bin \ +opensbi-riscv32-sifive_u-fw_jump.bin opensbi-riscv32-virt-fw_jump.bin \ opensbi-riscv64-sifive_u-fw_jump.bin opensbi-riscv64-virt-fw_jump.bin diff --git a/pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin b/pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin new file mode 100644 index 0000000000000000000000000000000000000000..bab13f597ac9da31518f0a2bb22c2a1dbd56380d GIT binary patch literal 49472 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[67.161.15.180]) by smtp.gmail.com with ESMTPSA id 129sm1294079pfw.84.2020.03.16.21.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 21:06:09 -0700 (PDT) Subject: [PULL 4/6] riscv: sifive_u: Update BIOS_FILENAME for 32-bit Date: Mon, 16 Mar 2020 21:05:45 -0700 Message-Id: <20200317040547.222501-5-palmerdabbelt@google.com> X-Mailer: git-send-email 2.25.1.481.gfbce0eb801-goog In-Reply-To: <20200317040547.222501-1-palmerdabbelt@google.com> References: <20200317040547.222501-1-palmerdabbelt@google.com> MIME-Version: 1.0 Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Bin Meng , Alistair Francis , Palmer Dabbelt From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Update BIOS_FILENAME to consider 32-bit bios image file name. Tested booting Linux v5.5 32-bit image (built from rv32_defconfig plus CONFIG_SOC_SIFIVE) with the default 32-bit bios image. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 156a003642..4409ea1ccc 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -56,7 +56,11 @@ #include -#define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" +#if defined(TARGET_RISCV32) +# define BIOS_FILENAME "opensbi-riscv32-sifive_u-fw_jump.bin" +#else +# define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" +#endif static const struct MemmapEntry { hwaddr base; From patchwork Tue Mar 17 04:05:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 11441697 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 99A54913 for ; Tue, 17 Mar 2020 04:09:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 70B4320658 for ; Tue, 17 Mar 2020 04:09:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="Y1cY+rt5" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 70B4320658 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:52223 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jE3XQ-0004yF-JZ for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Mar 2020 00:09:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45551) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jE3Ud-0008GI-85 for qemu-devel@nongnu.org; Tue, 17 Mar 2020 00:06:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jE3Ub-00032d-Aa for qemu-devel@nongnu.org; Tue, 17 Mar 2020 00:06:15 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:33622) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jE3Ub-0002vx-3F for qemu-devel@nongnu.org; Tue, 17 Mar 2020 00:06:13 -0400 Received: by mail-pg1-x541.google.com with SMTP id m5so10982719pgg.0 for ; Mon, 16 Mar 2020 21:06:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding:cc:from:to; bh=Nva8E1OWcJIE1NilXnKldlirFJKhPrI+ipIaZ9JueS4=; b=Y1cY+rt5n7KA4ighproX33aPZqsdJq7Gm/xEzl9xnQbF/VHEZICGwx+kVpBLzfpHYz 43MVl6OXwMshlQOdjVjOlZklAkI8RgL4+Q8AaEEX1aMRGpVt+irJ8R15sAlxK9ZW+MbC +EMZ3NGepkPw+gbwTJ/rELcyQ1hSAvaDtDh6BZpZftR0hdEGDvMxeKtO65GwoC2cvSzo /j0U77QIZ+vf2k3vSG2F82NWlYAmkVzO74b3FzNUecnCYbEW9FhW5qsYyfbQcgiIXVcR gOhXlLOqaWu7DsK9qo4RS0y8q52dJVuqa1T8LbII6uQz7hBtRT3kBA5nqMYRHTiPjwVT /YZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=Nva8E1OWcJIE1NilXnKldlirFJKhPrI+ipIaZ9JueS4=; b=Upofs4qgLjqGFhNapfI7G4K+OCsc9/5+bBi6ox6gujaqRmnxo0rpsE56X4EUgadS7r b8CzvqCdBVCTkNEIIYOpjEXW+VI0Gli1SkBMYuysBzNaH6Kngx2imWqf3us2rriIp2h6 PtVw8WzrArpAsYfn/c0UAUzTxGIGGzqRRJDCUUMsxa/rEgWBCXe+5Zl2LjbjOYH5K7Y+ nMDOjk707Za/KvdbCBjQB+1QKdGQ1SaidMO+dJti6Pd8UGuWgPLNoAEuqv4FPeeqW3ap cRlcjHP2yxPhIaW6MLz24zTCpdEbRohCbS5Uw9zT91YlIp9w0rh/DDvj9Pemnx6FHTYn AbWQ== X-Gm-Message-State: ANhLgQ3to5VhmZnN3iFb12sYiQ8Ai7PSgKS7OzDMDcLDbfMVJPg/4XQf c5ZzeHaOyLWa32lx08y1XT73dA== X-Google-Smtp-Source: ADFU+vu8N20pler5Np9qBBnMysikZGCu9zHc/x2SfAPvlZUf3DHzGd4MYjRZUaTb7ykutlLAI+ftrQ== X-Received: by 2002:a63:4752:: with SMTP id w18mr2929264pgk.379.1584417971766; Mon, 16 Mar 2020 21:06:11 -0700 (PDT) Received: from localhost (c-67-161-15-180.hsd1.ca.comcast.net. [67.161.15.180]) by smtp.gmail.com with ESMTPSA id y7sm1268552pfq.159.2020.03.16.21.06.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 21:06:11 -0700 (PDT) Subject: [PULL 5/6] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries Date: Mon, 16 Mar 2020 21:05:46 -0700 Message-Id: <20200317040547.222501-6-palmerdabbelt@google.com> X-Mailer: git-send-email 2.25.1.481.gfbce0eb801-goog In-Reply-To: <20200317040547.222501-1-palmerdabbelt@google.com> References: <20200317040547.222501-1-palmerdabbelt@google.com> MIME-Version: 1.0 Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Bin Meng , ilippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Add two GitLab jobs to build the OpenSBI firmware binaries. The first job builds a Docker image with the packages requisite to build OpenSBI, and stores this image in the GitLab registry. The second job pulls the image from the registry and builds the OpenSBI firmware binaries. The docker image is only rebuilt if the GitLab YAML or the Dockerfile is updated. The second job is only built when the roms/opensbi/ submodule is updated, when a git-ref starts with 'opensbi' or when the last commit contains 'OpenSBI'. The files generated are archived in the artifacts.zip file. With OpenSBI v0.6, it took 2 minutes 56 seconds to build the docker image, and 1 minute 24 seconds to generate the artifacts.zip with the firmware binaries (filesize: 111KiB). See: https://gitlab.com/lbmeng/qemu/pipelines/120520138 Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Bin Meng Signed-off-by: Palmer Dabbelt --- .gitlab-ci-opensbi.yml | 63 +++++++++++++++++++++++++++++++++ .gitlab-ci.d/opensbi/Dockerfile | 33 +++++++++++++++++ .gitlab-ci.yml | 1 + 3 files changed, 97 insertions(+) create mode 100644 .gitlab-ci-opensbi.yml create mode 100644 .gitlab-ci.d/opensbi/Dockerfile diff --git a/.gitlab-ci-opensbi.yml b/.gitlab-ci-opensbi.yml new file mode 100644 index 0000000000..dd051c0124 --- /dev/null +++ b/.gitlab-ci-opensbi.yml @@ -0,0 +1,63 @@ +docker-opensbi: + stage: build + rules: # Only run this job when the Dockerfile is modified + - changes: + - .gitlab-ci-opensbi.yml + - .gitlab-ci.d/opensbi/Dockerfile + when: always + image: docker:19.03.1 + services: + - docker:19.03.1-dind + variables: + GIT_DEPTH: 3 + IMAGE_TAG: $CI_REGISTRY_IMAGE:opensbi-cross-build + # We don't use TLS + DOCKER_HOST: tcp://docker:2375 + DOCKER_TLS_CERTDIR: "" + before_script: + - docker login -u $CI_REGISTRY_USER -p $CI_REGISTRY_PASSWORD $CI_REGISTRY + script: + - docker pull $IMAGE_TAG || true + - docker build --cache-from $IMAGE_TAG --tag $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA + --tag $IMAGE_TAG .gitlab-ci.d/opensbi + - docker push $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA + - docker push $IMAGE_TAG + +build-opensbi: + rules: # Only run this job when ... + - changes: # ... roms/opensbi/ is modified (submodule updated) + - roms/opensbi/* + when: always + - if: '$CI_COMMIT_REF_NAME =~ /^opensbi/' # or the branch/tag starts with 'opensbi' + when: always + - if: '$CI_COMMIT_MESSAGE =~ /opensbi/i' # or last commit description contains 'OpenSBI' + when: always + artifacts: + paths: # 'artifacts.zip' will contains the following files: + - pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin + - pc-bios/opensbi-riscv32-virt-fw_jump.bin + - pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin + - pc-bios/opensbi-riscv64-virt-fw_jump.bin + - opensbi32-virt-stdout.log + - opensbi32-virt-stderr.log + - opensbi64-virt-stdout.log + - opensbi64-virt-stderr.log + - opensbi32-sifive_u-stdout.log + - opensbi32-sifive_u-stderr.log + - opensbi64-sifive_u-stdout.log + - opensbi64-sifive_u-stderr.log + image: $CI_REGISTRY_IMAGE:opensbi-cross-build + variables: + GIT_DEPTH: 3 + script: # Clone the required submodules and build OpenSBI + - git submodule update --init roms/opensbi + - export JOBS=$(($(getconf _NPROCESSORS_ONLN) + 1)) + - echo "=== Using ${JOBS} simultaneous jobs ===" + - make -j${JOBS} -C roms/opensbi clean + - make -j${JOBS} -C roms opensbi32-virt 2>&1 1>opensbi32-virt-stdout.log | tee -a opensbi32-virt-stderr.log >&2 + - make -j${JOBS} -C roms/opensbi clean + - make -j${JOBS} -C roms opensbi64-virt 2>&1 1>opensbi64-virt-stdout.log | tee -a opensbi64-virt-stderr.log >&2 + - make -j${JOBS} -C roms/opensbi clean + - make -j${JOBS} -C roms opensbi32-sifive_u 2>&1 1>opensbi32-sifive_u-stdout.log | tee -a opensbi32-sifive_u-stderr.log >&2 + - make -j${JOBS} -C roms/opensbi clean + - make -j${JOBS} -C roms opensbi64-sifive_u 2>&1 1>opensbi64-sifive_u-stdout.log | tee -a opensbi64-sifive_u-stderr.log >&2 diff --git a/.gitlab-ci.d/opensbi/Dockerfile b/.gitlab-ci.d/opensbi/Dockerfile new file mode 100644 index 0000000000..4ba8a4de86 --- /dev/null +++ b/.gitlab-ci.d/opensbi/Dockerfile @@ -0,0 +1,33 @@ +# +# Docker image to cross-compile OpenSBI firmware binaries +# +FROM ubuntu:18.04 + +MAINTAINER Bin Meng + +# Install packages required to build OpenSBI +RUN apt update \ + && \ + \ + DEBIAN_FRONTEND=noninteractive \ + apt install --assume-yes --no-install-recommends \ + build-essential \ + ca-certificates \ + git \ + make \ + wget \ + && \ + \ + rm -rf /var/lib/apt/lists/* + +# Manually install the kernel.org "Crosstool" based toolchains for gcc-8.3 +RUN wget -O - \ + https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/8.3.0/x86_64-gcc-8.3.0-nolibc-riscv32-linux.tar.xz \ + | tar -C /opt -xJ +RUN wget -O - \ + https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/8.3.0/x86_64-gcc-8.3.0-nolibc-riscv64-linux.tar.xz \ + | tar -C /opt -xJ + +# Export the toolchains to the system path +ENV PATH="/opt/gcc-8.3.0-nolibc/riscv32-linux/bin:${PATH}" +ENV PATH="/opt/gcc-8.3.0-nolibc/riscv64-linux/bin:${PATH}" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 72f8b8aa51..b889fb96b6 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,5 +1,6 @@ include: - local: '/.gitlab-ci-edk2.yml' + - local: '/.gitlab-ci-opensbi.yml' before_script: - apt-get update -qq From patchwork Tue Mar 17 04:05:47 2020 Content-Type: text/plain; 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[67.161.15.180]) by smtp.gmail.com with ESMTPSA id o128sm1328213pfg.5.2020.03.16.21.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 21:06:12 -0700 (PDT) Subject: [PULL 6/6] target/riscv: Fix VS mode interrupts forwarding. Date: Mon, 16 Mar 2020 21:05:47 -0700 Message-Id: <20200317040547.222501-7-palmerdabbelt@google.com> X-Mailer: git-send-email 2.25.1.481.gfbce0eb801-goog In-Reply-To: <20200317040547.222501-1-palmerdabbelt@google.com> References: <20200317040547.222501-1-palmerdabbelt@google.com> MIME-Version: 1.0 Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Rajnesh Kanwal , Palmer Dabbelt From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Rajnesh Kanwal Currently riscv_cpu_local_irq_pending is used to find out pending interrupt and VS mode interrupts are being shifted to represent S mode interrupts in this function. So when the cause returned by this function is passed to riscv_cpu_do_interrupt to actually forward the interrupt, the VS mode forwarding check does not work as intended and interrupt is actually forwarded to hypervisor. This patch fixes this issue. Signed-off-by: Rajnesh Kanwal Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5ea5d133aa..d3ba9efb02 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) target_ulong pending = env->mip & env->mie & ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); target_ulong vspending = (env->mip & env->mie & - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1; + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)); target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); @@ -907,6 +907,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) && !force_hs_execp) { + /* + * See if we need to adjust cause. Yes if its VS mode interrupt + * no if hypervisor has delegated one of hs mode's interrupt + */ + if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || + cause == IRQ_VS_EXT) + cause = cause - 1; /* Trap to VS mode */ } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */