From patchwork Fri Mar 20 01:03:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Stabellini X-Patchwork-Id: 11448221 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A24B8913 for ; Fri, 20 Mar 2020 01:05:32 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D8A820740 for ; Fri, 20 Mar 2020 01:05:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="mU/vPVg8" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7D8A820740 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1jF64Z-0006Ga-9x; Fri, 20 Mar 2020 01:03:39 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1jF64Y-0006GV-2N for xen-devel@lists.xenproject.org; Fri, 20 Mar 2020 01:03:38 +0000 X-Inumbo-ID: a116e854-6a46-11ea-b34e-bc764e2007e4 Received: from mail.kernel.org (unknown [198.145.29.99]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id a116e854-6a46-11ea-b34e-bc764e2007e4; Fri, 20 Mar 2020 01:03:37 +0000 (UTC) Received: from localhost (c-67-164-102-47.hsd1.ca.comcast.net [67.164.102.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8ADAF20740; Fri, 20 Mar 2020 01:03:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584666216; bh=fe+X7bF39oYc+QF+L+y6m7dnhWjqAtGe6lhYNYgdaTw=; h=Date:From:To:cc:Subject:From; b=mU/vPVg8u619Xb4twUUklZ9nZQYdGktLcYUxokzuglJNg1AKKF9EsXB27mSy/4EY5 bJnD9W4sSyusaOg9bwUkG0D8ep6Hq/FfwsHAl+B2+76pRzr9ovqN1MQ+8x5/+KEEFV z2NVwmSNKU+8o6ZUkMsy4IU0TkJIbPX0DobH92SA= Date: Thu, 19 Mar 2020 18:03:36 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@sstabellini-ThinkPad-T480s To: julien@xen.org Message-ID: User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Subject: [Xen-devel] [PATCH] xen/arm: implement GICD_I[S/C]ACTIVER reads X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, peng.fan@nxp.com, sstabellini@kernel.org, xuwei5@hisilicon.com Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This is a simple implementation of GICD_ICACTIVER / GICD_ISACTIVER reads. It doesn't take into account the latest state of interrupts on other processors. Only the local processor is up-to-date. Signed-off-by: Stefano Stabellini Tested-by: Wei Xu Tested-by: Peng Fan diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 4e60ba15cc..c9755ba45b 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -713,9 +713,38 @@ static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v, goto read_as_zero; /* Read the active status of an IRQ via GICD/GICR is not supported */ - case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVER): + case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN): case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN): - goto read_as_zero; + { + bool invert = false; + struct pending_irq *p; + unsigned int start_irq, irq; + + if ( reg < GICD_ISACTIVERN ) + start_irq = (reg - GICD_ISACTIVER) * 8; + else + { + start_irq = (reg - GICD_ICACTIVER) * 8; + invert = true; + } + + *r = 0; + + /* + * The following won't reflect the latest status of interrupts on + * other vcpus. + */ + for ( irq = start_irq; irq < start_irq + 32; irq++ ) + { + p = irq_to_pending(v, irq); + if ( p != NULL && test_bit(GIC_IRQ_GUEST_ACTIVE, &p->status) ) + *r |= 1 << (irq - start_irq); + } + if ( invert ) + *r = ~(*r); + + return 1; + } case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN): {