From patchwork Tue Mar 24 16:15:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 11455951 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F13C114B4 for ; Tue, 24 Mar 2020 16:19:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BE82E2073E for ; Tue, 24 Mar 2020 16:19:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="AjaNNAvl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727948AbgCXQTw (ORCPT ); Tue, 24 Mar 2020 12:19:52 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:55444 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727688AbgCXQTw (ORCPT ); Tue, 24 Mar 2020 12:19:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=UtULx5L9tTkKUjNc3EavCQG/o3g4X2jMZn5gHRuZvMM=; b=AjaNNAvlu6x3i3GgMPQfhSfRxL fisn9fmLvBIUREG9VrP7B+p/8rtfSGF0PmAQEA+Dd2MUI4T+n0ckiVWDQUggu/XstiB+a80Y7ahDz qkEOJNhqRPyVp0DnhV1pyCBU4k97Plum6Z61L4xZFDFIE+yCd3aOp9V6lDXxV64EBqorKfa+bqlqW X8in/4mJVWmBRvW5540mt32Eetw1gz+r5sUbk7TFYSbAg6jeXDl8btn+gzWprVbkrlANYuiwLdweo A7f9gGVQdb1xZ3nsQT0eQfDFjStigxyLge1Kbl6cIJk0MHvhaA/e1ydTGI+OH3di4HjoypZNAzHQ9 j8vJE22Q==; Received: from 213-225-10-87.nat.highway.a1.net ([213.225.10.87] helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1jGmHP-0003FP-KG; Tue, 24 Mar 2020 16:19:52 +0000 From: Christoph Hellwig To: Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] MIPS: remove cpu_has_64bit_gp_regs and cpu_has_64bit_addresses Date: Tue, 24 Mar 2020 17:15:20 +0100 Message-Id: <20200324161525.754181-2-hch@lst.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200324161525.754181-1-hch@lst.de> References: <20200324161525.754181-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Both macros are always identical to CONFIG_64BIT. Signed-off-by: Christoph Hellwig --- arch/mips/include/asm/cpu-features.h | 12 ------------ arch/mips/include/asm/io.h | 4 ++-- .../include/asm/mach-ath25/cpu-feature-overrides.h | 2 -- .../include/asm/mach-ath79/cpu-feature-overrides.h | 2 -- .../asm/mach-lantiq/falcon/cpu-feature-overrides.h | 2 -- .../asm/mach-ralink/mt7620/cpu-feature-overrides.h | 2 -- .../asm/mach-ralink/mt7621/cpu-feature-overrides.h | 2 -- .../asm/mach-ralink/rt288x/cpu-feature-overrides.h | 2 -- .../asm/mach-ralink/rt305x/cpu-feature-overrides.h | 2 -- .../asm/mach-ralink/rt3883/cpu-feature-overrides.h | 2 -- .../include/asm/mach-rc32434/cpu-feature-overrides.h | 2 -- arch/mips/mm/page.c | 12 ++++++------ 12 files changed, 8 insertions(+), 38 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index de44c92b1c1f..2798ea0d5fff 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -432,12 +432,6 @@ # ifndef cpu_has_64bit_zero_reg # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) # endif -# ifndef cpu_has_64bit_gp_regs -# define cpu_has_64bit_gp_regs 0 -# endif -# ifndef cpu_has_64bit_addresses -# define cpu_has_64bit_addresses 0 -# endif # ifndef cpu_vmbits # define cpu_vmbits 31 # endif @@ -453,12 +447,6 @@ # ifndef cpu_has_64bit_zero_reg # define cpu_has_64bit_zero_reg 1 # endif -# ifndef cpu_has_64bit_gp_regs -# define cpu_has_64bit_gp_regs 1 -# endif -# ifndef cpu_has_64bit_addresses -# define cpu_has_64bit_addresses 1 -# endif # ifndef cpu_vmbits # define cpu_vmbits cpu_data[0].vmbits # define __NEED_VMBITS_PROBE diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index cf1f2a4a2418..7be323ed2bfd 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -166,7 +166,7 @@ static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long si #define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL)) - if (cpu_has_64bit_addresses) { + if (IS_ENABLED(CONFIG_64BIT)) { u64 base = UNCAC_BASE; /* @@ -275,7 +275,7 @@ static inline void iounmap(const volatile void __iomem *addr) #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) - if (cpu_has_64bit_addresses || + if (IS_ENABLED(CONFIG_64BIT) || (__builtin_constant_p(addr) && __IS_KSEG1(addr))) return; diff --git a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h index 95a0b580909d..91f638ee68e0 100644 --- a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h @@ -55,7 +55,5 @@ #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 #endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h index e7c972fccd9f..bc52a75d77a8 100644 --- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h @@ -44,8 +44,6 @@ #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h index f03c1c42dd90..0fdec83af64b 100644 --- a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h @@ -45,8 +45,6 @@ #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h index 6ea5908f0c11..945e0fd4a884 100644 --- a/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h @@ -44,8 +44,6 @@ #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h index e06f517b2588..21f73ef8f695 100644 --- a/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h @@ -45,8 +45,6 @@ #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h index 9c069646d0bd..c314c3cec130 100644 --- a/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h @@ -43,8 +43,6 @@ #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 #define cpu_dcache_line_size() 16 #define cpu_icache_line_size() 16 diff --git a/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h index 2e423fd15384..9fb175dc9b78 100644 --- a/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h @@ -43,8 +43,6 @@ #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h index 7cee0e232580..57857566e5df 100644 --- a/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h @@ -42,8 +42,6 @@ #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 #define cpu_dcache_line_size() 32 #define cpu_icache_line_size() 32 diff --git a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h index bc46179fdf40..852f15c8853b 100644 --- a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h @@ -53,8 +53,6 @@ /* #define cpu_has_nofpuex ? */ #define cpu_has_64bits 0 #define cpu_has_64bit_zero_reg 0 -#define cpu_has_64bit_gp_regs 0 -#define cpu_has_64bit_addresses 0 #define cpu_has_inclusive_pcaches 0 diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index c5578897a4fa..6bc6540dc9de 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -104,7 +104,7 @@ static int cache_line_size; static inline void pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off) { - if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) { + if (IS_ENABLED(CONFIG_64BIT) && DADDI_WAR && r4k_daddiu_bug()) { if (off > 0x7fff) { uasm_i_lui(buf, T9, uasm_rel_hi(off)); uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off)); @@ -123,12 +123,12 @@ pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off) static void set_prefetch_parameters(void) { - if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) + if (IS_ENABLED(CONFIG_64BIT) || cpu_has_64bit_zero_reg) clear_word_size = 8; else clear_word_size = 4; - if (cpu_has_64bit_gp_regs) + if (IS_ENABLED(CONFIG_64BIT)) copy_word_size = 8; else copy_word_size = 4; @@ -232,7 +232,7 @@ static void set_prefetch_parameters(void) static void build_clear_store(u32 **buf, int off) { - if (cpu_has_64bit_gp_regs || cpu_has_64bit_zero_reg) { + if (IS_ENABLED(CONFIG_64BIT) || cpu_has_64bit_zero_reg) { uasm_i_sd(buf, ZERO, off, A0); } else { uasm_i_sw(buf, ZERO, off, A0); @@ -366,7 +366,7 @@ void build_clear_page(void) static void build_copy_load(u32 **buf, int reg, int off) { - if (cpu_has_64bit_gp_regs) { + if (IS_ENABLED(CONFIG_64BIT)) { uasm_i_ld(buf, reg, off, A1); } else { uasm_i_lw(buf, reg, off, A1); @@ -375,7 +375,7 @@ static void build_copy_load(u32 **buf, int reg, int off) static void build_copy_store(u32 **buf, int reg, int off) { - if (cpu_has_64bit_gp_regs) { + if (IS_ENABLED(CONFIG_64BIT)) { uasm_i_sd(buf, reg, off, A0); } else { uasm_i_sw(buf, reg, off, A0); From patchwork Tue Mar 24 16:15:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 11455959 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CBB5314B4 for ; Tue, 24 Mar 2020 16:20:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AC7AF20788 for ; Tue, 24 Mar 2020 16:20:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="BzBuNjIa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727600AbgCXQTy (ORCPT ); Tue, 24 Mar 2020 12:19:54 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:55446 "EHLO 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+0000 From: Christoph Hellwig To: Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] MIPS: cleanup fixup_bigphys_addr handling Date: Tue, 24 Mar 2020 17:15:21 +0100 Message-Id: <20200324161525.754181-3-hch@lst.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200324161525.754181-1-hch@lst.de> References: <20200324161525.754181-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org fixup_bigphys_addr is only provided by the alchemy platform. Remove all the stubs, and ensure we only call it if it is actually implemented. Also don't bother implementing io_remap_pfn_range if we don't have to, and move the remaining implementation to alchemy platform code. Signed-off-by: Christoph Hellwig --- arch/mips/Kconfig | 4 +++ arch/mips/alchemy/common/setup.c | 16 ++++++--- arch/mips/include/asm/mach-au1x00/ioremap.h | 38 -------------------- arch/mips/include/asm/mach-bcm63xx/ioremap.h | 5 --- arch/mips/include/asm/mach-bmips/ioremap.h | 5 --- arch/mips/include/asm/mach-generic/ioremap.h | 9 ----- arch/mips/include/asm/mach-tx39xx/ioremap.h | 9 ----- arch/mips/include/asm/mach-tx49xx/ioremap.h | 9 ----- arch/mips/include/asm/pgtable.h | 23 ++++++------ arch/mips/pci/pci-alchemy.c | 2 +- 10 files changed, 27 insertions(+), 93 deletions(-) delete mode 100644 arch/mips/include/asm/mach-au1x00/ioremap.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 797d7f1ad5fe..091e524e5ab4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -92,6 +92,9 @@ config MIPS select SYSCTL_EXCEPTION_TRACE select VIRT_TO_BUS +config MIPS_FIXUP_BIGPHYS_ADDR + bool + menu "Machine selection" choice @@ -157,6 +160,7 @@ config MIPS_ALCHEMY select CSRC_R4K select IRQ_MIPS_CPU select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is + select MIPS_FIXUP_BIGPHYS_ADDR if PCI select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 7faaa6d593a7..a8cbc552bd64 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -72,9 +72,9 @@ void __init plat_mem_setup(void) iomem_resource.end = IOMEM_RESOURCE_END; } -#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI) +#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR /* This routine should be valid for all Au1x based boards */ -phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) +phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) { unsigned long start = ALCHEMY_PCI_MEMWIN_START; unsigned long end = ALCHEMY_PCI_MEMWIN_END; @@ -90,5 +90,13 @@ phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) /* default nop */ return phys_addr; } -EXPORT_SYMBOL(__fixup_bigphys_addr); -#endif + +int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr, + unsigned long pfn, unsigned long size, pgprot_t prot) +{ + phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); + + return remap_pfn_range(vma, vaddr, phys_addr >> PAGE_SHIFT, size, prot); +} +EXPORT_SYMBOL(io_remap_pfn_range); +#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */ diff --git a/arch/mips/include/asm/mach-au1x00/ioremap.h b/arch/mips/include/asm/mach-au1x00/ioremap.h deleted file mode 100644 index f6877ed8b8d0..000000000000 --- a/arch/mips/include/asm/mach-au1x00/ioremap.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * include/asm-mips/mach-au1x00/ioremap.h - */ -#ifndef __ASM_MACH_AU1X00_IOREMAP_H -#define __ASM_MACH_AU1X00_IOREMAP_H - -#include - -#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI) -extern phys_addr_t __fixup_bigphys_addr(phys_addr_t, phys_addr_t); -#else -static inline phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) -{ - return phys_addr; -} -#endif - -/* - * Allow physical addresses to be fixed up to help 36-bit peripherals. - */ -static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) -{ - return __fixup_bigphys_addr(phys_addr, size); -} - -static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, - unsigned long flags) -{ - return NULL; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return 0; -} - -#endif /* __ASM_MACH_AU1X00_IOREMAP_H */ diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h index 8cd261ec0a75..73f31825bbf3 100644 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h @@ -4,11 +4,6 @@ #include -static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) -{ - return phys_addr; -} - static inline int is_bcm63xx_internal_registers(phys_addr_t offset) { switch (bcm63xx_get_cpu_id()) { diff --git a/arch/mips/include/asm/mach-bmips/ioremap.h b/arch/mips/include/asm/mach-bmips/ioremap.h index 52632ebc705f..63b4af9916b6 100644 --- a/arch/mips/include/asm/mach-bmips/ioremap.h +++ b/arch/mips/include/asm/mach-bmips/ioremap.h @@ -4,11 +4,6 @@ #include -static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) -{ - return phys_addr; -} - static inline int is_bmips_internal_registers(phys_addr_t offset) { if (offset >= 0xfff80000) diff --git a/arch/mips/include/asm/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h index 4e36ea25ed33..f2442b84545c 100644 --- a/arch/mips/include/asm/mach-generic/ioremap.h +++ b/arch/mips/include/asm/mach-generic/ioremap.h @@ -7,15 +7,6 @@ #include -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) -{ - return phys_addr; -} - static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, unsigned long flags) { diff --git a/arch/mips/include/asm/mach-tx39xx/ioremap.h b/arch/mips/include/asm/mach-tx39xx/ioremap.h index 077b3c9971f7..157a7292397e 100644 --- a/arch/mips/include/asm/mach-tx39xx/ioremap.h +++ b/arch/mips/include/asm/mach-tx39xx/ioremap.h @@ -7,15 +7,6 @@ #include -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) -{ - return phys_addr; -} - static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, unsigned long flags) { diff --git a/arch/mips/include/asm/mach-tx49xx/ioremap.h b/arch/mips/include/asm/mach-tx49xx/ioremap.h index c6b9e05f44c4..b1f3710acf8e 100644 --- a/arch/mips/include/asm/mach-tx49xx/ioremap.h +++ b/arch/mips/include/asm/mach-tx49xx/ioremap.h @@ -7,15 +7,6 @@ #include -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) -{ - return phys_addr; -} - static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, unsigned long flags) { diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index aef5378f909c..80a2ef213777 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -491,20 +491,17 @@ static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, #define kern_addr_valid(addr) (1) -#ifdef CONFIG_PHYS_ADDR_T_64BIT -extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); - -static inline int io_remap_pfn_range(struct vm_area_struct *vma, - unsigned long vaddr, - unsigned long pfn, - unsigned long size, - pgprot_t prot) -{ - phys_addr_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); - return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot); -} +/* + * Allow physical addresses to be fixed up to help 36-bit peripherals. + */ +#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR +phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size); +int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr, + unsigned long pfn, unsigned long size, pgprot_t prot); #define io_remap_pfn_range io_remap_pfn_range -#endif +#else +#define fixup_bigphys_addr(addr, size) (addr) +#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */ #ifdef CONFIG_TRANSPARENT_HUGEPAGE diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index 01a2af8215c8..7285b5667568 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c @@ -52,7 +52,7 @@ struct alchemy_pci_context { static struct alchemy_pci_context *__alchemy_pci_ctx; -/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr +/* IO/MEM resources for PCI. Keep the memres in sync with fixup_bigphys_addr * in arch/mips/alchemy/common/setup.c */ static struct resource alchemy_pci_def_memres = { From patchwork Tue Mar 24 16:15:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 11455957 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94E0D15AB for ; Tue, 24 Mar 2020 16:20:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7558420788 for ; Tue, 24 Mar 2020 16:20:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="L33QL+FC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728005AbgCXQT5 (ORCPT ); Tue, 24 Mar 2020 12:19:57 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:55478 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727688AbgCXQT5 (ORCPT ); Tue, 24 Mar 2020 12:19:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=hWBzE7+Ma89SOv/SxY3UdWgMQO5IxVxE22FLaZEKh/I=; b=L33QL+FC6OUtXe/Qh46Prloa5b lLkZ6Ka3AxwHJu22+ZmBfRkwiKA6Cz8EJJzIvTqIQnwXHBHKb+J/gzj7DILgquMOgdhJuMbEu0UBh DzczfY2x82db+KHQ2P82uOBjljl1KlHb7hUi8U2lO12oH/GwWRZSpOleZzm8EpWFH4qe/6pSPzl6O 0IyWoemmFV2lFqm9lS2IrNc1Bsqqr0mOtn3zBvM52/Xy4nC66wks2vGQzyQ5X6Vj000HzbYjtaDdi jd5YaXNSgE35IIRa6y4WL4c0QEwN1BZEtwWxv2LLxFufeIrAWLiepC4XPVRThZDq9lHZCxDsBYKco SuicTaWQ==; Received: from [2001:4bb8:18c:2a9e:999c:283e:b14a:9189] (helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1jGmHU-0003Ft-EK; Tue, 24 Mar 2020 16:19:56 +0000 From: Christoph Hellwig To: Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] MIPS: merge __ioremap_mode into ioremap_prot Date: Tue, 24 Mar 2020 17:15:22 +0100 Message-Id: <20200324161525.754181-4-hch@lst.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200324161525.754181-1-hch@lst.de> References: <20200324161525.754181-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org There is no reason to have two ioremap with flags interfaces. Merge the historic mips __ioremap_mode into ioremap_prot which is a generic kernel interface. Signed-off-by: Christoph Hellwig --- arch/mips/include/asm/io.h | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 7be323ed2bfd..60513250f8f8 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -156,9 +156,17 @@ static inline void *isa_bus_to_virt(unsigned long address) extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags); extern void __iounmap(const volatile void __iomem *addr); -static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size, - unsigned long flags) +/* + * ioremap_prot - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + + * ioremap_prot gives the caller control over cache coherency attributes (CCA) + */ +static inline void __iomem *ioremap_prot(phys_addr_t offset, + unsigned long size, unsigned long prot_val) { + unsigned long flags = prot_val & _CACHE_MASK; void __iomem *addr = plat_ioremap(offset, size, flags); if (addr) @@ -202,18 +210,6 @@ static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long si #undef __IS_LOW512 } -/* - * ioremap_prot - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map - - * ioremap_prot gives the caller control over cache coherency attributes (CCA) - */ -static inline void __iomem *ioremap_prot(phys_addr_t offset, - unsigned long size, unsigned long prot_val) { - return __ioremap_mode(offset, size, prot_val & _CACHE_MASK); -} - /* * ioremap - map bus memory into CPU space * @offset: bus address of the memory @@ -226,7 +222,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset, * address. */ #define ioremap(offset, size) \ - __ioremap_mode((offset), (size), _CACHE_UNCACHED) + ioremap_prot((offset), (size), _CACHE_UNCACHED) #define ioremap_uc ioremap /* @@ -245,7 +241,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset, * memory-like regions on I/O busses. */ #define ioremap_cache(offset, size) \ - __ioremap_mode((offset), (size), _page_cachable_default) + ioremap_prot((offset), (size), _page_cachable_default) /* * ioremap_wc - map bus memory into CPU space @@ -266,7 +262,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset, * _CACHE_UNCACHED option (see cpu_probe() method). */ #define ioremap_wc(offset, size) \ - __ioremap_mode((offset), (size), boot_cpu_data.writecombine) + ioremap_prot((offset), (size), boot_cpu_data.writecombine) static inline void iounmap(const volatile void __iomem *addr) { From patchwork Tue Mar 24 16:15:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 11455953 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7AC2615AB for ; Tue, 24 Mar 2020 16:20:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5BD5720774 for ; Tue, 24 Mar 2020 16:20:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="OciYbK/I" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728782AbgCXQT7 (ORCPT ); Tue, 24 Mar 2020 12:19:59 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:55510 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727444AbgCXQT7 (ORCPT ); Tue, 24 Mar 2020 12:19:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=S0lIA/D9gWt+6MqKJrlRkinxSTiEVCtRIMKBgvJLedI=; b=OciYbK/IlASgDILE7n0ioDsgqy 7AGIivU04MyeYUvwoS471vq7KpdJ/tp76SH/613gs2qaShr8lUBu4Tz+CnwjdRkw/MsVC4HK2TPrJ USeIHucirJuZlYcZQxItpL/a/clLG9oa9cDcQDOAFWZ9DudAg2MfnA8iFF9fTaQC+Ano5cH20bVzk tqmN/v8KfA9uvCpy2tjrvlJse0u+GyiAWpOCc1qLbk9iCiQUQSZOE+seob0uyVMyh4hxUrmWObjsy dV+uvzZEH4MLiwkGraD3Ww9b3B3vgLFIkuqC8iLZyfjkdcWrtxRKMKxhO8auI3K+6BVTWuwbuGq5w xKuqGBWQ==; Received: from [2001:4bb8:18c:2a9e:999c:283e:b14a:9189] (helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1jGmHW-0003Gq-Rs; Tue, 24 Mar 2020 16:19:59 +0000 From: Christoph Hellwig To: Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] MIPS: split out the 64-bit ioremap implementation Date: Tue, 24 Mar 2020 17:15:23 +0100 Message-Id: <20200324161525.754181-5-hch@lst.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200324161525.754181-1-hch@lst.de> References: <20200324161525.754181-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Split out the mips64 ioremap implementation entirely, as it will never use page table based remapping. Signed-off-by: Christoph Hellwig --- arch/mips/include/asm/io.h | 65 ++++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 28 deletions(-) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 60513250f8f8..f007571e036d 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -153,6 +153,25 @@ static inline void *isa_bus_to_virt(unsigned long address) */ #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) +#ifdef CONFIG_64BIT +static inline void __iomem *ioremap_prot(phys_addr_t offset, + unsigned long size, unsigned long prot_val) +{ + unsigned long flags = prot_val & _CACHE_MASK; + u64 base = (flags == _CACHE_UNCACHED ? IO_BASE : UNCAC_BASE); + void __iomem *addr; + + addr = plat_ioremap(offset, size, flags); + if (!addr) + addr = (void __iomem *)(unsigned long)(base + offset); + return addr; +} + +static inline void iounmap(const volatile void __iomem *addr) +{ + plat_iounmap(addr); +} +#else /* CONFIG_64BIT */ extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags); extern void __iounmap(const volatile void __iomem *addr); @@ -174,18 +193,8 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset, #define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL)) - if (IS_ENABLED(CONFIG_64BIT)) { - u64 base = UNCAC_BASE; - - /* - * R10000 supports a 2 bit uncached attribute therefore - * UNCAC_BASE may not equal IO_BASE. - */ - if (flags == _CACHE_UNCACHED) - base = (u64) IO_BASE; - return (void __iomem *) (unsigned long) (base + offset); - } else if (__builtin_constant_p(offset) && - __builtin_constant_p(size) && __builtin_constant_p(flags)) { + if (__builtin_constant_p(offset) && + __builtin_constant_p(size) && __builtin_constant_p(flags)) { phys_addr_t phys_addr, last_addr; phys_addr = fixup_bigphys_addr(offset, size); @@ -210,6 +219,22 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset, #undef __IS_LOW512 } +static inline void iounmap(const volatile void __iomem *addr) +{ + if (plat_iounmap(addr)) + return; + +#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) + + if (__builtin_constant_p(addr) && __IS_KSEG1(addr)) + return; + + __iounmap(addr); + +#undef __IS_KSEG1 +} +#endif /* !CONFIG_64BIT */ + /* * ioremap - map bus memory into CPU space * @offset: bus address of the memory @@ -264,22 +289,6 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset, #define ioremap_wc(offset, size) \ ioremap_prot((offset), (size), boot_cpu_data.writecombine) -static inline void iounmap(const volatile void __iomem *addr) -{ - if (plat_iounmap(addr)) - return; - -#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) - - if (IS_ENABLED(CONFIG_64BIT) || - (__builtin_constant_p(addr) && __IS_KSEG1(addr))) - return; - - __iounmap(addr); - -#undef __IS_KSEG1 -} - #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64) #define war_io_reorder_wmb() wmb() #else From patchwork Tue Mar 24 16:15:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 11455955 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 07BE814B4 for ; Tue, 24 Mar 2020 16:20:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D3F5720836 for ; Tue, 24 Mar 2020 16:20:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="NWzQQaZO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728817AbgCXQUD (ORCPT ); Tue, 24 Mar 2020 12:20:03 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:55790 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727444AbgCXQUC (ORCPT ); Tue, 24 Mar 2020 12:20:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=ra8fh5EfKLWroTBF+kGRKZFmzx8N1zRxk5+K8iQb9NE=; b=NWzQQaZOguX+S5an6JDzbnjMxy miZnzmvWv8YWPrZKrb6fglGzx6gk+tSVSSy7TLy53iAYfH6LL2TCnGKVdnri4UB6ViJg2kvC81/Qg 9hDGqRUrn0pwlwTnCpjVyDCaUn3vfluAI/wpBuKk5h4Wk7GL7yzEwnRjLWN0K36Mi8tI2mJSlffLJ C+E2Sfvxi34bLvKXY3b0dQheKIOOVGZG3zXbeWu9bg/oFf+vBpgYMRnmDqSoe4UZwEKzdkKmQK+yJ fMw6DnKFBWcbj3iW7Zk1RcjXV2A3qkGPBuZWx4sBBqOcWJSoBzn4Y9pCfXcHjk3SFlPrNu2XIc4l0 tKO3Gdxw==; Received: from [2001:4bb8:18c:2a9e:999c:283e:b14a:9189] (helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1jGmHZ-0003Ih-BP; Tue, 24 Mar 2020 16:20:01 +0000 From: Christoph Hellwig To: Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] MIPS: move ioremap_prot und iounmap out of line Date: Tue, 24 Mar 2020 17:15:24 +0100 Message-Id: <20200324161525.754181-6-hch@lst.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200324161525.754181-1-hch@lst.de> References: <20200324161525.754181-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Neither of these interfaces is anywhere near the fast path. Move them out of line and avoid exposing implementation details to the drivers. Signed-off-by: Christoph Hellwig --- arch/mips/include/asm/io.h | 86 ++------------------------------------ arch/mips/mm/Makefile | 2 +- arch/mips/mm/ioremap.c | 45 ++++++++++---------- arch/mips/mm/ioremap64.c | 23 ++++++++++ 4 files changed, 49 insertions(+), 107 deletions(-) create mode 100644 arch/mips/mm/ioremap64.c diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index f007571e036d..346fffd9e972 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -30,8 +30,6 @@ #include #include #include - -#include #include /* @@ -153,87 +151,9 @@ static inline void *isa_bus_to_virt(unsigned long address) */ #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) -#ifdef CONFIG_64BIT -static inline void __iomem *ioremap_prot(phys_addr_t offset, - unsigned long size, unsigned long prot_val) -{ - unsigned long flags = prot_val & _CACHE_MASK; - u64 base = (flags == _CACHE_UNCACHED ? IO_BASE : UNCAC_BASE); - void __iomem *addr; - - addr = plat_ioremap(offset, size, flags); - if (!addr) - addr = (void __iomem *)(unsigned long)(base + offset); - return addr; -} - -static inline void iounmap(const volatile void __iomem *addr) -{ - plat_iounmap(addr); -} -#else /* CONFIG_64BIT */ -extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags); -extern void __iounmap(const volatile void __iomem *addr); - -/* - * ioremap_prot - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map - - * ioremap_prot gives the caller control over cache coherency attributes (CCA) - */ -static inline void __iomem *ioremap_prot(phys_addr_t offset, - unsigned long size, unsigned long prot_val) -{ - unsigned long flags = prot_val & _CACHE_MASK; - void __iomem *addr = plat_ioremap(offset, size, flags); - - if (addr) - return addr; - -#define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL)) - - if (__builtin_constant_p(offset) && - __builtin_constant_p(size) && __builtin_constant_p(flags)) { - phys_addr_t phys_addr, last_addr; - - phys_addr = fixup_bigphys_addr(offset, size); - - /* Don't allow wraparound or zero size. */ - last_addr = phys_addr + size - 1; - if (!size || last_addr < phys_addr) - return NULL; - - /* - * Map uncached objects in the low 512MB of address - * space using KSEG1. - */ - if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && - flags == _CACHE_UNCACHED) - return (void __iomem *) - (unsigned long)CKSEG1ADDR(phys_addr); - } - - return __ioremap(offset, size, flags); - -#undef __IS_LOW512 -} - -static inline void iounmap(const volatile void __iomem *addr) -{ - if (plat_iounmap(addr)) - return; - -#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) - - if (__builtin_constant_p(addr) && __IS_KSEG1(addr)) - return; - - __iounmap(addr); - -#undef __IS_KSEG1 -} -#endif /* !CONFIG_64BIT */ +void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, + unsigned long prot_val); +void iounmap(const volatile void __iomem *addr); /* * ioremap - map bus memory into CPU space diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 46f483e952c8..865926a37775 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -23,7 +23,7 @@ obj-y += uasm-mips.o endif obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o -obj-$(CONFIG_64BIT) += pgtable-64.o +obj-$(CONFIG_64BIT) += ioremap64.o pgtable-64.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_DMA_NONCOHERENT) += dma-noncoherent.o diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c index 8317f337a86e..c5b5181c7cd0 100644 --- a/arch/mips/mm/ioremap.c +++ b/arch/mips/mm/ioremap.c @@ -17,6 +17,10 @@ #include #include #include +#include + +#define IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL)) +#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) static inline void remap_area_pte(pte_t * pte, unsigned long address, phys_addr_t size, phys_addr_t phys_addr, unsigned long flags) @@ -118,27 +122,25 @@ static int __ioremap_check_ram(unsigned long start_pfn, unsigned long nr_pages, } /* - * Generic mapping function (not visible outside): - */ - -/* - * Remap an arbitrary physical address space into the kernel virtual - * address space. Needed when the kernel wants to access high addresses - * directly. + * ioremap_prot - map bus memory into CPU space + * @phys_addr: bus address of the memory + * @size: size of the resource to map * - * NOTE! We need to allow non-page-aligned mappings too: we will obviously - * have to convert them into an offset in a page-aligned mapping, but the - * caller shouldn't need to know that small detail. + * ioremap_prot gives the caller control over cache coherency attributes (CCA) */ - -#define IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL)) - -void __iomem * __ioremap(phys_addr_t phys_addr, phys_addr_t size, unsigned long flags) +void __iomem *ioremap_prot(phys_addr_t phys_addr, unsigned long size, + unsigned long prot_val) { + unsigned long flags = prot_val & _CACHE_MASK; unsigned long offset, pfn, last_pfn; - struct vm_struct * area; + struct vm_struct *area; phys_addr_t last_addr; - void * addr; + void *addr; + void __iomem *cpu_addr; + + cpu_addr = plat_ioremap(phys_addr, size, flags); + if (cpu_addr) + return cpu_addr; phys_addr = fixup_bigphys_addr(phys_addr, size); @@ -189,14 +191,13 @@ void __iomem * __ioremap(phys_addr_t phys_addr, phys_addr_t size, unsigned long return (void __iomem *) (offset + (char *)addr); } +EXPORT_SYMBOL(ioremap_prot); -#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) - -void __iounmap(const volatile void __iomem *addr) +void iounmap(const volatile void __iomem *addr) { struct vm_struct *p; - if (IS_KSEG1(addr)) + if (plat_iounmap(addr) || IS_KSEG1(addr)) return; p = remove_vm_area((void *) (PAGE_MASK & (unsigned long __force) addr)); @@ -205,6 +206,4 @@ void __iounmap(const volatile void __iomem *addr) kfree(p); } - -EXPORT_SYMBOL(__ioremap); -EXPORT_SYMBOL(__iounmap); +EXPORT_SYMBOL(iounmap); diff --git a/arch/mips/mm/ioremap64.c b/arch/mips/mm/ioremap64.c new file mode 100644 index 000000000000..15e7820d6a5f --- /dev/null +++ b/arch/mips/mm/ioremap64.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include + +void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, + unsigned long prot_val) +{ + unsigned long flags = prot_val & _CACHE_MASK; + u64 base = (flags == _CACHE_UNCACHED ? IO_BASE : UNCAC_BASE); + void __iomem *addr; + + addr = plat_ioremap(offset, size, flags); + if (!addr) + addr = (void __iomem *)(unsigned long)(base + offset); + return addr; +} +EXPORT_SYMBOL(ioremap_prot); + +void iounmap(const volatile void __iomem *addr) +{ + plat_iounmap(addr); +} +EXPORT_SYMBOL(iounmap); From patchwork Tue Mar 24 16:15:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 11455961 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E78B315AB for ; Tue, 24 Mar 2020 16:20:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C95BA208DB for ; Tue, 24 Mar 2020 16:20:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="aRhKBcCC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728840AbgCXQUH (ORCPT ); Tue, 24 Mar 2020 12:20:07 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:56062 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727951AbgCXQUG (ORCPT ); Tue, 24 Mar 2020 12:20:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=yyuJrtfVyD3fUEUFSeqLWA3IrF2yJjSqrC/bf4Fe8oE=; b=aRhKBcCCDp5rWVHuLJVj2GR1VF qk/OKAziUNpNfEjiYSZLkTOU11V5e3nwUyYl9IP1OO+LX5zJKHNipJ4WgQhlSYo2bwtiO4On2Cxf8 vhn4uf1XDH76MK4/rvHxTYula2UEomkUU75pRE9CfDDXfIub8UDjez6t8CM1N+h0emCQvQRrlzuYZ h63Ov535QYsewymF4p4C/p1CY4tXa+q9pNNKKqbybvnpGV3hVjiyaY0GV+GADzMj9UDPbNtC3nYSL 91UVuhq8TLFJ80V58VrgM9sOU+Q/vCEVDrSLQ9EWCQCbIbco1Ey9XgOuBgqhG0rim6PVjGxiW9wCG vq2lQGvw==; Received: from [2001:4bb8:18c:2a9e:999c:283e:b14a:9189] (helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1jGmHc-0003PT-Vq; Tue, 24 Mar 2020 16:20:05 +0000 From: Christoph Hellwig To: Thomas Bogendoerfer Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] MIPS: use ioremap_page_range Date: Tue, 24 Mar 2020 17:15:25 +0100 Message-Id: <20200324161525.754181-7-hch@lst.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200324161525.754181-1-hch@lst.de> References: <20200324161525.754181-1-hch@lst.de> MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Use the generic ioremap_page_range helper instead of reimplementing it. Signed-off-by: Christoph Hellwig --- arch/mips/mm/ioremap.c | 112 ++++------------------------------------- 1 file changed, 11 insertions(+), 101 deletions(-) diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c index c5b5181c7cd0..b6dad2fd5575 100644 --- a/arch/mips/mm/ioremap.c +++ b/arch/mips/mm/ioremap.c @@ -14,99 +14,14 @@ #include #include #include +#include #include -#include #include #include #define IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL)) #define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) -static inline void remap_area_pte(pte_t * pte, unsigned long address, - phys_addr_t size, phys_addr_t phys_addr, unsigned long flags) -{ - phys_addr_t end; - unsigned long pfn; - pgprot_t pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | __READABLE - | __WRITEABLE | flags); - - address &= ~PMD_MASK; - end = address + size; - if (end > PMD_SIZE) - end = PMD_SIZE; - BUG_ON(address >= end); - pfn = phys_addr >> PAGE_SHIFT; - do { - if (!pte_none(*pte)) { - printk("remap_area_pte: page already exists\n"); - BUG(); - } - set_pte(pte, pfn_pte(pfn, pgprot)); - address += PAGE_SIZE; - pfn++; - pte++; - } while (address && (address < end)); -} - -static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, - phys_addr_t size, phys_addr_t phys_addr, unsigned long flags) -{ - phys_addr_t end; - - address &= ~PGDIR_MASK; - end = address + size; - if (end > PGDIR_SIZE) - end = PGDIR_SIZE; - phys_addr -= address; - BUG_ON(address >= end); - do { - pte_t * pte = pte_alloc_kernel(pmd, address); - if (!pte) - return -ENOMEM; - remap_area_pte(pte, address, end - address, address + phys_addr, flags); - address = (address + PMD_SIZE) & PMD_MASK; - pmd++; - } while (address && (address < end)); - return 0; -} - -static int remap_area_pages(unsigned long address, phys_addr_t phys_addr, - phys_addr_t size, unsigned long flags) -{ - int error; - pgd_t * dir; - unsigned long end = address + size; - - phys_addr -= address; - dir = pgd_offset(&init_mm, address); - flush_cache_all(); - BUG_ON(address >= end); - do { - p4d_t *p4d; - pud_t *pud; - pmd_t *pmd; - - error = -ENOMEM; - p4d = p4d_alloc(&init_mm, dir, address); - if (!p4d) - break; - pud = pud_alloc(&init_mm, p4d, address); - if (!pud) - break; - pmd = pmd_alloc(&init_mm, pud, address); - if (!pmd) - break; - if (remap_area_pmd(pmd, address, end - address, - phys_addr + address, flags)) - break; - error = 0; - address = (address + PGDIR_SIZE) & PGDIR_MASK; - dir++; - } while (address && (address < end)); - flush_tlb_all(); - return error; -} - static int __ioremap_check_ram(unsigned long start_pfn, unsigned long nr_pages, void *arg) { @@ -135,7 +50,7 @@ void __iomem *ioremap_prot(phys_addr_t phys_addr, unsigned long size, unsigned long offset, pfn, last_pfn; struct vm_struct *area; phys_addr_t last_addr; - void *addr; + unsigned long vaddr; void __iomem *cpu_addr; cpu_addr = plat_ioremap(phys_addr, size, flags); @@ -183,27 +98,22 @@ void __iomem *ioremap_prot(phys_addr_t phys_addr, unsigned long size, area = get_vm_area(size, VM_IOREMAP); if (!area) return NULL; - addr = area->addr; - if (remap_area_pages((unsigned long) addr, phys_addr, size, flags)) { - vunmap(addr); + vaddr = (unsigned long)area->addr; + + flags |= _PAGE_GLOBAL | _PAGE_PRESENT | __READABLE | __WRITEABLE; + if (ioremap_page_range(vaddr, vaddr + size, phys_addr, + __pgprot(flags))) { + free_vm_area(area); return NULL; } - return (void __iomem *) (offset + (char *)addr); + return (void __iomem *)(vaddr + offset); } EXPORT_SYMBOL(ioremap_prot); void iounmap(const volatile void __iomem *addr) { - struct vm_struct *p; - - if (plat_iounmap(addr) || IS_KSEG1(addr)) - return; - - p = remove_vm_area((void *) (PAGE_MASK & (unsigned long __force) addr)); - if (!p) - printk(KERN_ERR "iounmap: bad address %p\n", addr); - - kfree(p); + if (!plat_iounmap(addr) && !IS_KSEG1(addr)) + vunmap((void *)((unsigned long)addr & PAGE_MASK)); } EXPORT_SYMBOL(iounmap);