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[14.202.190.183]) by smtp.gmail.com with ESMTPSA id 93sm4609599pjo.43.2020.03.25.07.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2020 07:42:38 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [PATCH 1/5] ppc/spapr: tweak change system reset helper Date: Thu, 26 Mar 2020 00:41:43 +1000 Message-Id: <20200325144147.221875-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200325144147.221875-1-npiggin@gmail.com> References: <20200325144147.221875-1-npiggin@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Mahesh Salgaonkar , qemu-devel@nongnu.org, Nicholas Piggin , Greg Kurz , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Ganesh Goudar , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Rather than have the helper take an optional vector address override, instead have its caller modify env->nip itself. This is more consistent when adding pnv nmi support, and also with mce injection added later. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater --- hw/ppc/spapr.c | 9 ++++++--- target/ppc/cpu.h | 2 +- target/ppc/excp_helper.c | 5 +---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 9a2bd501aa..785c41d205 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3385,13 +3385,13 @@ static void spapr_machine_finalizefn(Object *obj) void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) { SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; cpu_synchronize_state(cs); /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ if (spapr->fwnmi_system_reset_addr != -1) { uint64_t rtas_addr, addr; - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; /* get rtas addr from fdt */ rtas_addr = spapr_get_rtas_addr(); @@ -3405,7 +3405,10 @@ void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); env->gpr[3] = addr; } - ppc_cpu_do_system_reset(cs, spapr->fwnmi_system_reset_addr); + ppc_cpu_do_system_reset(cs); + if (spapr->fwnmi_system_reset_addr != -1) { + env->nip = spapr->fwnmi_system_reset_addr; + } } static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 88d9449555..f4a5304d43 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1220,7 +1220,7 @@ int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); #ifndef CONFIG_USER_ONLY -void ppc_cpu_do_system_reset(CPUState *cs, target_ulong vector); +void ppc_cpu_do_system_reset(CPUState *cs); void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector); extern const VMStateDescription vmstate_ppc_cpu; #endif diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 08bc885ca6..7f2b5899d3 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -961,15 +961,12 @@ static void ppc_hw_interrupt(CPUPPCState *env) } } -void ppc_cpu_do_system_reset(CPUState *cs, target_ulong vector) +void ppc_cpu_do_system_reset(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); - if (vector != -1) { - env->nip = vector; - } } void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) From patchwork Wed Mar 25 14:41:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 11458017 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 48BDF17D4 for ; Wed, 25 Mar 2020 14:45:28 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1E7CE20775 for ; Wed, 25 Mar 2020 14:45:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="siYyMHML" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1E7CE20775 Authentication-Results: mail.kernel.org; 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[14.202.190.183]) by smtp.gmail.com with ESMTPSA id 93sm4609599pjo.43.2020.03.25.07.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2020 07:42:43 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [PATCH 2/5] ppc/pnv: Add support for NMI interface Date: Thu, 26 Mar 2020 00:41:44 +1000 Message-Id: <20200325144147.221875-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200325144147.221875-1-npiggin@gmail.com> References: <20200325144147.221875-1-npiggin@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Mahesh Salgaonkar , qemu-devel@nongnu.org, Nicholas Piggin , Greg Kurz , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Ganesh Goudar , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This implements the NMI interface for the PNV machine, similarly to commit 3431648272d ("spapr: Add support for new NMI interface") for SPAPR. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater --- hw/ppc/pnv.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index b75ad06390..671535ebe6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -27,6 +27,7 @@ #include "sysemu/runstate.h" #include "sysemu/cpus.h" #include "sysemu/device_tree.h" +#include "sysemu/hw_accel.h" #include "target/ppc/cpu.h" #include "qemu/log.h" #include "hw/ppc/fdt.h" @@ -34,6 +35,7 @@ #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_core.h" #include "hw/loader.h" +#include "hw/nmi.h" #include "exec/address-spaces.h" #include "qapi/visitor.h" #include "monitor/monitor.h" @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) } } +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + cpu_synchronize_state(cs); + ppc_cpu_do_system_reset(cs); + /* + * SRR1[42:45] is set to 0100 which the ISA defines as implementation + * dependent. POWER processors use this for xscom triggered interrupts, + * which come from the BMC or NMI IPIs. + */ + env->spr[SPR_SRR1] |= PPC_BIT(43); +} + +static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) +{ + CPUState *cs; + + CPU_FOREACH(cs) { + async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); + } +} + static void pnv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); + NMIClass *nc = NMI_CLASS(oc); mc->desc = "IBM PowerNV (Non-Virtualized)"; mc->init = pnv_init; @@ -1975,6 +2002,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; mc->default_ram_id = "pnv.ram"; ispc->print_info = pnv_pic_print_info; + nc->nmi_monitor_handler = pnv_nmi; object_class_property_add_bool(oc, "hb-mode", pnv_machine_get_hb, pnv_machine_set_hb, @@ -2038,7 +2066,7 @@ static const TypeInfo types[] = { .class_size = sizeof(PnvMachineClass), .interfaces = (InterfaceInfo[]) { { TYPE_INTERRUPT_STATS_PROVIDER }, - { }, + { TYPE_NMI }, }, }, { From patchwork Wed Mar 25 14:41:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 11458011 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 545051392 for ; Wed, 25 Mar 2020 14:43:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2B440208E0 for ; Wed, 25 Mar 2020 14:43:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XFM5Y+Ld" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2B440208E0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:37354 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jH7G0-0005qp-8T for patchwork-qemu-devel@patchwork.kernel.org; Wed, 25 Mar 2020 10:43:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37097) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jH7F7-00041f-Pl for qemu-devel@nongnu.org; Wed, 25 Mar 2020 10:42:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jH7F6-0005ed-Aj for qemu-devel@nongnu.org; Wed, 25 Mar 2020 10:42:53 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:42676) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jH7F3-0005bp-8e; Wed, 25 Mar 2020 10:42:49 -0400 Received: by mail-pg1-x52c.google.com with SMTP id h8so1230972pgs.9; Wed, 25 Mar 2020 07:42:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WKYOGG0g9s481Vm+dxBUu5LtOyPszMxI1/G7LP+9Ut4=; b=XFM5Y+LdZSJf1fyJHzHaYC4KPs45aN1EYpypio/bBbiz/n4uGllxriKLqdCNtfKlb0 1/sOh6mCHxdxO0urXnusWoVqXdAwgGyXTQTYG3mbbCDQgyfRsv/Uky5NhnHBlQNWrlof kNzQJ7YrYO07N0tz9zML9axbcg5mTwny9kYJHCvhVwtEfZppsw5BTiTpVpkjmcpVQlUm OALoejT2EJrrVRZ8NZ4ZK9+Oy5zZJQ7QEnLQiuOC27arv7AfuKSv+k2EzVbpT2Aqa7Ym XTYtdno8arx99PvyEsgR0z2c1punlhJI8xD1cRnR02EfQ5XA0yTpVBzeoTPnsOZPkOye Eb0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WKYOGG0g9s481Vm+dxBUu5LtOyPszMxI1/G7LP+9Ut4=; b=U65kPHmUGxgJqiIE5iepujDy59LJxaEynyALhvCfH8deI4L1sYiHl9GiK7FKea6Lwk 3Pe0ordizwirnPNn/rzcMWY5NVFGBc7I4FLcrSn3Lfcd/gUYGpdINZ9S5414p/WJMSwP oOL/+dgYdalPiFVQZtdX0ZFDvqga27DBvkzb7vlMzRniwQUaML6myO12fGyBScPFKxXI EV4dcCS59UNq1I5XZ639D0/wFbtqmCHucsUMwy0tRRecwmYD1Car6WOuWOZZlEokVK3d Asse1cZV47710B5XDNtayS0qPVhB87XY94lLVoPjrxRQ3u09pt6Pxbs7FmenlBWs6s5F QN8Q== X-Gm-Message-State: ANhLgQ2hOHFFznhewDGXLmIU0LL30hBng5OpPpvEu8UfN/KYDsrRE8Df oYP/DJAoSFUvli6KxEngVzGF5el7 X-Google-Smtp-Source: ADFU+vuwJ60gCy3xAzXdh0hle4Cjf/kHhSwoM17PGT+Hnf2LoDXKtGmm/y1xK6LmySTBtL1jcnwJ0g== X-Received: by 2002:a63:794d:: with SMTP id u74mr3491417pgc.15.1585147367982; Wed, 25 Mar 2020 07:42:47 -0700 (PDT) Received: from bobo.ibm.com (14-202-190-183.tpgi.com.au. [14.202.190.183]) by smtp.gmail.com with ESMTPSA id 93sm4609599pjo.43.2020.03.25.07.42.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2020 07:42:47 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [PATCH 3/5] nmi: add MCE class for implementing machine check injection commands Date: Thu, 26 Mar 2020 00:41:45 +1000 Message-Id: <20200325144147.221875-4-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200325144147.221875-1-npiggin@gmail.com> References: <20200325144147.221875-1-npiggin@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Mahesh Salgaonkar , qemu-devel@nongnu.org, Nicholas Piggin , Greg Kurz , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Ganesh Goudar , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Like commit 9cb805fd26 ("cpus: Define callback for QEMU "nmi" command") this implements a machine check injection command framework and defines a monitor command for ppc. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater Tested-by: Cédric Le Goater --- hmp-commands.hx | 20 +++++++++++- hw/core/nmi.c | 61 ++++++++++++++++++++++++++++++++++++ include/hw/nmi.h | 20 ++++++++++++ include/monitor/hmp-target.h | 1 - include/monitor/hmp.h | 1 + monitor/hmp-cmds.c | 1 + target/ppc/monitor.c | 11 +++++++ 7 files changed, 113 insertions(+), 2 deletions(-) diff --git a/hmp-commands.hx b/hmp-commands.hx index 7f0f3974ad..4a9089b431 100644 --- a/hmp-commands.hx +++ b/hmp-commands.hx @@ -1581,12 +1581,30 @@ ERST .cmd = hmp_mce, }, -#endif SRST ``mce`` *cpu* *bank* *status* *mcgstatus* *addr* *misc* Inject an MCE on the given CPU (x86 only). ERST +#endif + +#if defined(TARGET_PPC) + + { + .name = "mce", + .args_type = "cpu_index:i,srr1_mask:l,dsisr:i,dar:l,recovered:i", + .params = "cpu srr1_mask dsisr dar recovered", + .help = "inject a MCE on the given CPU", + .cmd = hmp_mce, + }, + +SRST +``mce`` *cpu* *srr1_mask* *dsisr* *dar* *recovered* + Inject an MCE on the given CPU (PPC only). +ERST + +#endif + { .name = "getfd", .args_type = "fdname:s", diff --git a/hw/core/nmi.c b/hw/core/nmi.c index 481c4b3c7e..2a79500967 100644 --- a/hw/core/nmi.c +++ b/hw/core/nmi.c @@ -86,3 +86,64 @@ static void nmi_register_types(void) } type_init(nmi_register_types) + +struct do_mce_s { + const QDict *qdict; + Error *err; + bool handled; +}; + +static void mce_children(Object *o, struct do_mce_s *ns); + +static int do_mce(Object *o, void *opaque) +{ + struct do_mce_s *ms = opaque; + MCEState *m = (MCEState *) object_dynamic_cast(o, TYPE_MCE); + + if (m) { + MCEClass *mc = MCE_GET_CLASS(m); + + ms->handled = true; + mc->mce_monitor_handler(m, ms->qdict, &ms->err); + if (ms->err) { + return -1; + } + } + mce_children(o, ms); + + return 0; +} + +static void mce_children(Object *o, struct do_mce_s *ms) +{ + object_child_foreach(o, do_mce, ms); +} + +void mce_monitor_handle(const QDict *qdict, Error **errp) +{ + struct do_mce_s ms = { + .qdict = qdict, + .err = NULL, + .handled = false + }; + + mce_children(object_get_root(), &ms); + if (ms.handled) { + error_propagate(errp, ms.err); + } else { + error_setg(errp, QERR_UNSUPPORTED); + } +} + +static const TypeInfo mce_info = { + .name = TYPE_MCE, + .parent = TYPE_INTERFACE, + .class_size = sizeof(MCEClass), +}; + +static void mce_register_types(void) +{ + type_register_static(&mce_info); +} + +type_init(mce_register_types) diff --git a/include/hw/nmi.h b/include/hw/nmi.h index fe37ce3ad8..de39d95c9a 100644 --- a/include/hw/nmi.h +++ b/include/hw/nmi.h @@ -43,4 +43,24 @@ typedef struct NMIClass { void nmi_monitor_handle(int cpu_index, Error **errp); + +#define TYPE_MCE "mce" + +#define MCE_CLASS(klass) \ + OBJECT_CLASS_CHECK(MCEClass, (klass), TYPE_MCE) +#define MCE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MCEClass, (obj), TYPE_MCE) +#define MCE(obj) \ + INTERFACE_CHECK(MCEState, (obj), TYPE_MCE) + +typedef struct MCEState MCEState; + +typedef struct MCEClass { + InterfaceClass parent_class; + + void (*mce_monitor_handler)(MCEState *n, const QDict *qdict, Error **errp); +} MCEClass; + +void mce_monitor_handle(const QDict *qdict, Error **errp); + #endif /* NMI_H */ diff --git a/include/monitor/hmp-target.h b/include/monitor/hmp-target.h index 8b7820a3ad..afb8f5bca2 100644 --- a/include/monitor/hmp-target.h +++ b/include/monitor/hmp-target.h @@ -45,7 +45,6 @@ CPUState *mon_get_cpu(void); void hmp_info_mem(Monitor *mon, const QDict *qdict); void hmp_info_tlb(Monitor *mon, const QDict *qdict); -void hmp_mce(Monitor *mon, const QDict *qdict); void hmp_info_local_apic(Monitor *mon, const QDict *qdict); void hmp_info_io_apic(Monitor *mon, const QDict *qdict); diff --git a/include/monitor/hmp.h b/include/monitor/hmp.h index e33ca5a911..f747a5e214 100644 --- a/include/monitor/hmp.h +++ b/include/monitor/hmp.h @@ -54,6 +54,7 @@ void hmp_ringbuf_read(Monitor *mon, const QDict *qdict); void hmp_cont(Monitor *mon, const QDict *qdict); void hmp_system_wakeup(Monitor *mon, const QDict *qdict); void hmp_nmi(Monitor *mon, const QDict *qdict); +void hmp_mce(Monitor *mon, const QDict *qdict); void hmp_set_link(Monitor *mon, const QDict *qdict); void hmp_balloon(Monitor *mon, const QDict *qdict); void hmp_loadvm(Monitor *mon, const QDict *qdict); diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c index 58724031ea..3664ef2a4f 100644 --- a/monitor/hmp-cmds.c +++ b/monitor/hmp-cmds.c @@ -52,6 +52,7 @@ #include "exec/ramlist.h" #include "hw/intc/intc.h" #include "hw/rdma/rdma.h" +#include "hw/nmi.h" #include "migration/snapshot.h" #include "migration/misc.h" diff --git a/target/ppc/monitor.c b/target/ppc/monitor.c index a5a177d717..6daf543efc 100644 --- a/target/ppc/monitor.c +++ b/target/ppc/monitor.c @@ -28,6 +28,8 @@ #include "qemu/ctype.h" #include "monitor/hmp-target.h" #include "monitor/hmp.h" +#include "qapi/qmp/qdict.h" +#include "hw/nmi.h" static target_long monitor_get_ccr(const struct MonitorDef *md, int val) { @@ -72,6 +74,15 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) dump_mmu(env1); } +void hmp_mce(Monitor *mon, const QDict *qdict) +{ + Error *err = NULL; + + mce_monitor_handle(qdict, &err); + + hmp_handle_error(mon, err); +} + const MonitorDef monitor_defs[] = { { "fpscr", offsetof(CPUPPCState, fpscr) }, /* Next instruction pointer */ From patchwork Wed Mar 25 14:41:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 11458015 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2CEE8139A for ; Wed, 25 Mar 2020 14:45:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0240820775 for ; Wed, 25 Mar 2020 14:45:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="uHjrQk2h" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0240820775 Authentication-Results: mail.kernel.org; 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[14.202.190.183]) by smtp.gmail.com with ESMTPSA id 93sm4609599pjo.43.2020.03.25.07.42.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2020 07:42:52 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [PATCH 4/5] ppc/spapr: Implement mce injection Date: Thu, 26 Mar 2020 00:41:46 +1000 Message-Id: <20200325144147.221875-5-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200325144147.221875-1-npiggin@gmail.com> References: <20200325144147.221875-1-npiggin@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Mahesh Salgaonkar , qemu-devel@nongnu.org, Nicholas Piggin , Greg Kurz , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Ganesh Goudar , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This implements mce injection for spapr. (qemu) mce 0 0x200000 0x80 0xdeadbeef 1 Disabling lock debugging due to kernel taint MCE: CPU0: machine check (Severe) Host SLB Multihit DAR: 00000000deadbeef [Recovered] MCE: CPU0: machine check (Severe) Host SLB Multihit [Recovered] MCE: CPU0: PID: 495 Comm: a NIP: [0000000130ee07c8] MCE: CPU0: Initiator CPU MCE: CPU0: Unknown [ 71.567193] MCE: CPU0: NIP: [c0000000000d7f6c] plpar_hcall_norets+0x1c/0x28 [ 71.567249] MCE: CPU0: Initiator CPU [ 71.567308] MCE: CPU0: Unknown Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater --- hw/ppc/spapr.c | 54 ++++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/spapr.h | 3 +++ 2 files changed, 57 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 785c41d205..6dbd1858f4 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -83,6 +83,7 @@ #include "hw/ppc/spapr_nvdimm.h" #include "monitor/monitor.h" +#include "qapi/qmp/qdict.h" #include @@ -3420,6 +3421,56 @@ static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) } } +typedef struct MCEInjectionParams { + uint64_t srr1_mask; + uint32_t dsisr; + uint64_t dar; + bool recovered; +} MCEInjectionParams; + +static void spapr_do_mce_on_cpu(CPUState *cs, run_on_cpu_data data) +{ + MCEInjectionParams *params = data.host_ptr; + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + uint64_t srr1_mce_bits = PPC_BITMASK(42, 45) | PPC_BIT(36); + + cpu_synchronize_state(cs); + + env->spr[SPR_SRR0] = env->nip; + env->spr[SPR_SRR1] = (env->msr & ~srr1_mce_bits) | + (params->srr1_mask & srr1_mce_bits); + if (params->dsisr) { + env->spr[SPR_DSISR] = params->dsisr; + env->spr[SPR_DAR] = params->dar; + } + + spapr_mce_req_event(cpu, params->recovered); +} + +static void spapr_mce(MCEState *m, const QDict *qdict, Error **errp) +{ + int cpu_index = qdict_get_int(qdict, "cpu_index"); + uint64_t srr1_mask = qdict_get_int(qdict, "srr1_mask"); + uint32_t dsisr = qdict_get_int(qdict, "dsisr"); + uint64_t dar = qdict_get_int(qdict, "dar"); + bool recovered = qdict_get_int(qdict, "recovered"); + CPUState *cs; + + cs = qemu_get_cpu(cpu_index); + + if (cs != NULL) { + MCEInjectionParams params = { + .srr1_mask = srr1_mask, + .dsisr = dsisr, + .dar = dar, + .recovered = recovered, + }; + + run_on_cpu(cs, spapr_do_mce_on_cpu, RUN_ON_CPU_HOST_PTR(¶ms)); + } +} + int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, void *fdt, int *fdt_start_offset, Error **errp) { @@ -4467,6 +4518,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); NMIClass *nc = NMI_CLASS(oc); + MCEClass *mcec = MCE_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); @@ -4511,6 +4563,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; fwc->get_dev_path = spapr_get_fw_dev_path; nc->nmi_monitor_handler = spapr_nmi; + mcec->mce_monitor_handler = spapr_mce; smc->phb_placement = spapr_phb_placement; vhc->hypercall = emulate_spapr_hypercall; vhc->hpt_mask = spapr_hpt_mask; @@ -4566,6 +4619,7 @@ static const TypeInfo spapr_machine_info = { .interfaces = (InterfaceInfo[]) { { TYPE_FW_PATH_PROVIDER }, { TYPE_NMI }, + { TYPE_MCE }, { TYPE_HOTPLUG_HANDLER }, { TYPE_PPC_VIRTUAL_HYPERVISOR }, { TYPE_XICS_FABRIC }, diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 42d64a0368..72f86a2ee8 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -929,4 +929,7 @@ void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); hwaddr spapr_get_rtas_addr(void); + +void spapr_mce_inject(CPUState *cs, uint64_t srr1_mask, uint32_t dsisr, + uint64_t dar, bool recovered); #endif /* HW_SPAPR_H */ From patchwork Wed Mar 25 14:41:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 11458013 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C7E3B913 for ; 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[14.202.190.183]) by smtp.gmail.com with ESMTPSA id 93sm4609599pjo.43.2020.03.25.07.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2020 07:42:56 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Subject: [PATCH 5/5] ppc/pnv: Implement mce injection Date: Thu, 26 Mar 2020 00:41:47 +1000 Message-Id: <20200325144147.221875-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200325144147.221875-1-npiggin@gmail.com> References: <20200325144147.221875-1-npiggin@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Mahesh Salgaonkar , qemu-devel@nongnu.org, Nicholas Piggin , Greg Kurz , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Ganesh Goudar , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This implements mce injection for pnv. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv.c | 55 ++++++++++++++++++++++++++++++++++++++++ target/ppc/cpu.h | 1 + target/ppc/excp_helper.c | 12 +++++++++ 3 files changed, 68 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 671535ebe6..9c515bfeed 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -38,6 +38,7 @@ #include "hw/nmi.h" #include "exec/address-spaces.h" #include "qapi/visitor.h" +#include "qapi/qmp/qdict.h" #include "monitor/monitor.h" #include "hw/intc/intc.h" #include "hw/ipmi/ipmi.h" @@ -1981,11 +1982,63 @@ static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) } } +typedef struct MCEInjectionParams { + uint64_t srr1_mask; + uint32_t dsisr; + uint64_t dar; + bool recovered; +} MCEInjectionParams; + +static void pnv_do_mce_on_cpu(CPUState *cs, run_on_cpu_data data) +{ + MCEInjectionParams *params = data.host_ptr; + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + uint64_t srr1_mce_bits = PPC_BITMASK(42, 45) | PPC_BIT(36); + + cpu_synchronize_state(cs); + ppc_cpu_do_machine_check(cs); + + env->spr[SPR_SRR1] |= (params->srr1_mask & srr1_mce_bits); + if (params->dsisr) { + env->spr[SPR_DSISR] = params->dsisr; + env->spr[SPR_DAR] = params->dar; + } + + if (!params->recovered) { + env->msr &= ~MSR_RI; + } +} + +static void pnv_mce(MCEState *m, const QDict *qdict, Error **errp) +{ + int cpu_index = qdict_get_int(qdict, "cpu_index"); + uint64_t srr1_mask = qdict_get_int(qdict, "srr1_mask"); + uint32_t dsisr = qdict_get_int(qdict, "dsisr"); + uint64_t dar = qdict_get_int(qdict, "dar"); + bool recovered = qdict_get_int(qdict, "recovered"); + CPUState *cs; + + cs = qemu_get_cpu(cpu_index); + + if (cs != NULL) { + MCEInjectionParams params = { + .srr1_mask = srr1_mask, + .dsisr = dsisr, + .dar = dar, + .recovered = recovered, + }; + + run_on_cpu(cs, pnv_do_mce_on_cpu, RUN_ON_CPU_HOST_PTR(¶ms)); + } +} + static void pnv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); NMIClass *nc = NMI_CLASS(oc); + MCEClass *mcec = MCE_CLASS(oc); mc->desc = "IBM PowerNV (Non-Virtualized)"; mc->init = pnv_init; @@ -2003,6 +2056,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) mc->default_ram_id = "pnv.ram"; ispc->print_info = pnv_pic_print_info; nc->nmi_monitor_handler = pnv_nmi; + mcec->mce_monitor_handler = pnv_mce; object_class_property_add_bool(oc, "hb-mode", pnv_machine_get_hb, pnv_machine_set_hb, @@ -2067,6 +2121,7 @@ static const TypeInfo types[] = { .interfaces = (InterfaceInfo[]) { { TYPE_INTERRUPT_STATS_PROVIDER }, { TYPE_NMI }, + { TYPE_MCE }, }, }, { diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f4a5304d43..9be27f59c5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1221,6 +1221,7 @@ int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); #ifndef CONFIG_USER_ONLY void ppc_cpu_do_system_reset(CPUState *cs); +void ppc_cpu_do_machine_check(CPUState *cs); void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector); extern const VMStateDescription vmstate_ppc_cpu; #endif diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7f2b5899d3..81dd8b6f8e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -279,6 +279,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) cs->halted = 1; cpu_interrupt_exittb(cs); } + if (msr_pow) { + /* indicate that we resumed from power save mode */ + msr |= 0x10000; + } if (env->msr_mask & MSR_HVB) { /* * ISA specifies HV, but can be delivered to guest with HV @@ -969,6 +973,14 @@ void ppc_cpu_do_system_reset(CPUState *cs) powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); } +void ppc_cpu_do_machine_check(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK); +} + void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) { PowerPCCPU *cpu = POWERPC_CPU(cs);